paul@0 | 1 | /* |
paul@0 | 2 | * LCD peripheral support for the JZ4740 and related SoCs. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> |
paul@64 | 5 | * Copyright (C) 2015, 2016, 2017, 2018, |
paul@268 | 6 | * 2020, 2024 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 7 | * |
paul@0 | 8 | * This program is free software; you can redistribute it and/or |
paul@0 | 9 | * modify it under the terms of the GNU General Public License as |
paul@0 | 10 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 11 | * the License, or (at your option) any later version. |
paul@0 | 12 | * |
paul@0 | 13 | * This program is distributed in the hope that it will be useful, |
paul@0 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 16 | * GNU General Public License for more details. |
paul@0 | 17 | * |
paul@0 | 18 | * You should have received a copy of the GNU General Public License |
paul@0 | 19 | * along with this program; if not, write to the Free Software |
paul@0 | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 21 | * Boston, MA 02110-1301, USA |
paul@0 | 22 | */ |
paul@0 | 23 | |
paul@0 | 24 | #include <l4/devices/hw_mmio_register_block.h> |
paul@0 | 25 | #include <l4/sys/cache.h> |
paul@69 | 26 | #include <l4/sys/irq.h> |
paul@268 | 27 | #include <l4/sys/rcv_endpoint.h> |
paul@0 | 28 | #include <l4/sys/types.h> |
paul@69 | 29 | #include <l4/util/util.h> |
paul@0 | 30 | |
paul@268 | 31 | #include <pthread.h> |
paul@268 | 32 | #include <pthread-l4.h> |
paul@268 | 33 | |
paul@0 | 34 | #include "lcd-jz4740.h" |
paul@0 | 35 | #include "lcd-jz4740-config.h" |
paul@75 | 36 | #include "lcd-jz4740-regs.h" |
paul@0 | 37 | |
paul@0 | 38 | #include <stdint.h> |
paul@0 | 39 | |
paul@0 | 40 | |
paul@0 | 41 | |
paul@0 | 42 | // Utility functions. |
paul@0 | 43 | |
paul@0 | 44 | // Round values up according to the resolution. |
paul@0 | 45 | |
paul@0 | 46 | static uint32_t align(uint32_t value, uint32_t resolution) |
paul@0 | 47 | { |
paul@0 | 48 | return (value + (resolution - 1)) & ~(resolution - 1); |
paul@0 | 49 | } |
paul@0 | 50 | |
paul@0 | 51 | // Value pair encoding. |
paul@0 | 52 | |
paul@0 | 53 | static uint32_t encode_pair(uint32_t start, uint32_t end) |
paul@0 | 54 | { |
paul@0 | 55 | return (start << Value_first) | (end << Value_second); |
paul@0 | 56 | } |
paul@0 | 57 | |
paul@0 | 58 | // RGB conversions. |
paul@0 | 59 | |
paul@0 | 60 | static uint16_t rgb8_to_rgb16(uint8_t rgb) |
paul@0 | 61 | { |
paul@0 | 62 | return ((((rgb & 0xe0) >> 5) * 4) << 11) | ((((rgb & 0x1c) >> 2) * 9) << 6) | ((rgb & 0x03) * 10); |
paul@0 | 63 | } |
paul@0 | 64 | |
paul@0 | 65 | static uint16_t rgb4_to_rgb16(uint8_t rgb) |
paul@0 | 66 | { |
paul@0 | 67 | return ((((rgb & 8) >> 3) * 0x1f) << 11) | ((((rgb & 6) >> 1) * 0x15) << 5) | ((rgb & 1) * 0x1f); |
paul@0 | 68 | } |
paul@0 | 69 | |
paul@0 | 70 | |
paul@0 | 71 | |
paul@0 | 72 | |
paul@0 | 73 | // If implemented as a Hw::Device, various properties would be |
paul@0 | 74 | // initialised in the constructor and obtained from the device tree |
paul@0 | 75 | // definitions. |
paul@0 | 76 | |
paul@0 | 77 | Lcd_jz4740_chip::Lcd_jz4740_chip(l4_addr_t addr, Jz4740_lcd_panel *panel) |
paul@0 | 78 | : _panel(panel) |
paul@0 | 79 | { |
paul@0 | 80 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@75 | 81 | _burst_size = 16; // 16-word burst size |
paul@0 | 82 | } |
paul@0 | 83 | |
paul@0 | 84 | struct Jz4740_lcd_panel * |
paul@0 | 85 | Lcd_jz4740_chip::get_panel() |
paul@0 | 86 | { |
paul@0 | 87 | return _panel; |
paul@0 | 88 | } |
paul@0 | 89 | |
paul@0 | 90 | void |
paul@0 | 91 | Lcd_jz4740_chip::disable() |
paul@0 | 92 | { |
paul@0 | 93 | // Set the disable bit for normal shutdown. |
paul@0 | 94 | |
paul@69 | 95 | _regs[Lcd_control] = _regs[Lcd_control] | (1U << Control_disable); |
paul@0 | 96 | } |
paul@0 | 97 | |
paul@0 | 98 | void |
paul@0 | 99 | Lcd_jz4740_chip::disable_quick() |
paul@0 | 100 | { |
paul@0 | 101 | // Clear the enable bit for quick shutdown. |
paul@0 | 102 | |
paul@69 | 103 | _regs[Lcd_control] = _regs[Lcd_control] & ~(1U << Control_enable); |
paul@0 | 104 | } |
paul@0 | 105 | |
paul@0 | 106 | void |
paul@0 | 107 | Lcd_jz4740_chip::enable() |
paul@0 | 108 | { |
paul@0 | 109 | // Clear the disable bit and set the enable bit. |
paul@0 | 110 | |
paul@69 | 111 | _regs[Lcd_status] = 0; |
paul@69 | 112 | _regs[Lcd_control] = (_regs[Lcd_control] & ~(1U << Control_disable)) | (1U << Control_enable); |
paul@69 | 113 | } |
paul@69 | 114 | |
paul@69 | 115 | bool |
paul@69 | 116 | Lcd_jz4740_chip::enabled() |
paul@69 | 117 | { |
paul@69 | 118 | return !(_regs[Lcd_status] & (1U << Status_disabled)); |
paul@0 | 119 | } |
paul@0 | 120 | |
paul@0 | 121 | // Calculate and return the pixel clock frequency. |
paul@0 | 122 | |
paul@0 | 123 | int |
paul@0 | 124 | Lcd_jz4740_chip::get_pixel_clock() |
paul@0 | 125 | { |
paul@0 | 126 | int pclk, multiplier; |
paul@0 | 127 | |
paul@0 | 128 | // Serial mode: 3 pixel clock cycles per pixel (one per channel). |
paul@0 | 129 | // Parallel mode: 1 pixel clock cycle per pixel. |
paul@0 | 130 | |
paul@0 | 131 | multiplier = have_serial_tft() ? 3 : 1; |
paul@0 | 132 | |
paul@0 | 133 | // Derive pixel clock rate from frame rate. |
paul@0 | 134 | // This multiplies the number of pixel periods in a line by the number of |
paul@0 | 135 | // lines in a frame, thus obtaining the number of such periods in a frame. |
paul@0 | 136 | // Multiplying this result with the frame rate yields the pixel frequency. |
paul@0 | 137 | |
paul@0 | 138 | pclk = _panel->frame_rate * |
paul@0 | 139 | (_panel->width * multiplier + |
paul@0 | 140 | _panel->hsync + _panel->line_start + _panel->line_end) * |
paul@0 | 141 | (_panel->height + |
paul@0 | 142 | _panel->vsync + _panel->frame_start + _panel->frame_end); |
paul@0 | 143 | |
paul@0 | 144 | // STN panel adjustments. |
paul@0 | 145 | |
paul@0 | 146 | if (have_stn_panel()) |
paul@0 | 147 | { |
paul@0 | 148 | // Colour STN panels apparently need to be driven at three times the rate. |
paul@0 | 149 | |
paul@0 | 150 | if (have_colour_stn()) pclk = (pclk * 3); |
paul@0 | 151 | |
paul@0 | 152 | // Reduce the rate according to the width of the STN connection. |
paul@0 | 153 | // Since the pins setting employs log2(pins), a shift by this value is |
paul@0 | 154 | // equivalent to a division by the number of pins. |
paul@0 | 155 | |
paul@0 | 156 | pclk = pclk >> ((_panel->config & Config_stn_pins_mask) >> Jz4740_lcd_config_stn_pins); |
paul@0 | 157 | |
paul@0 | 158 | // Divide the rate by the number of panels. |
paul@0 | 159 | |
paul@0 | 160 | pclk /= get_panels(); |
paul@0 | 161 | } |
paul@0 | 162 | |
paul@0 | 163 | return pclk; |
paul@0 | 164 | } |
paul@0 | 165 | |
paul@0 | 166 | |
paul@0 | 167 | |
paul@0 | 168 | // Return the panel mode. |
paul@0 | 169 | |
paul@0 | 170 | uint32_t |
paul@0 | 171 | Lcd_jz4740_chip::_mode() |
paul@0 | 172 | { |
paul@0 | 173 | return _panel->config & Config_mode_mask; |
paul@0 | 174 | } |
paul@0 | 175 | |
paul@0 | 176 | // Return the number of panels available. |
paul@0 | 177 | |
paul@0 | 178 | int |
paul@0 | 179 | Lcd_jz4740_chip::get_panels() |
paul@0 | 180 | { |
paul@0 | 181 | uint32_t mode = _mode(); |
paul@0 | 182 | |
paul@0 | 183 | return (mode == Jz4740_lcd_mode_stn_dual_colour) || |
paul@0 | 184 | (mode == Jz4740_lcd_mode_stn_dual_mono) ? 2 : 1; |
paul@0 | 185 | } |
paul@0 | 186 | |
paul@0 | 187 | // Return whether the panel is STN. |
paul@0 | 188 | |
paul@0 | 189 | int |
paul@0 | 190 | Lcd_jz4740_chip::have_stn_panel() |
paul@0 | 191 | { |
paul@0 | 192 | uint32_t mode = _mode(); |
paul@0 | 193 | |
paul@0 | 194 | return ((mode == Jz4740_lcd_mode_stn_single_colour) || |
paul@0 | 195 | (mode == Jz4740_lcd_mode_stn_dual_colour) || |
paul@0 | 196 | (mode == Jz4740_lcd_mode_stn_single_mono) || |
paul@0 | 197 | (mode == Jz4740_lcd_mode_stn_dual_mono)); |
paul@0 | 198 | } |
paul@0 | 199 | |
paul@0 | 200 | // Return whether the panel is colour STN. |
paul@0 | 201 | |
paul@0 | 202 | int |
paul@0 | 203 | Lcd_jz4740_chip::have_colour_stn() |
paul@0 | 204 | { |
paul@0 | 205 | uint32_t mode = _mode(); |
paul@0 | 206 | |
paul@0 | 207 | return ((mode == Jz4740_lcd_mode_stn_single_colour) || |
paul@0 | 208 | (mode == Jz4740_lcd_mode_stn_dual_colour)); |
paul@0 | 209 | } |
paul@0 | 210 | |
paul@0 | 211 | // Return whether the panel is colour STN. |
paul@0 | 212 | |
paul@0 | 213 | int |
paul@0 | 214 | Lcd_jz4740_chip::have_serial_tft() |
paul@0 | 215 | { |
paul@0 | 216 | return _mode() == Jz4740_lcd_mode_tft_serial; |
paul@0 | 217 | } |
paul@0 | 218 | |
paul@0 | 219 | |
paul@0 | 220 | |
paul@69 | 221 | // Return the pixel memory size in bits. |
paul@69 | 222 | |
paul@69 | 223 | l4_size_t |
paul@69 | 224 | Lcd_jz4740_chip::get_pixel_size() |
paul@69 | 225 | { |
paul@69 | 226 | if (_panel->bpp > 16) |
paul@69 | 227 | return 32; |
paul@69 | 228 | else if (_panel->bpp > 8) |
paul@69 | 229 | return 16; |
paul@69 | 230 | else |
paul@69 | 231 | return _panel->bpp; |
paul@69 | 232 | } |
paul@69 | 233 | |
paul@0 | 234 | // Return the line memory size. |
paul@0 | 235 | |
paul@0 | 236 | l4_size_t |
paul@0 | 237 | Lcd_jz4740_chip::get_line_size() |
paul@0 | 238 | { |
paul@0 | 239 | // Lines must be aligned to a word boundary. |
paul@0 | 240 | |
paul@69 | 241 | return align((_panel->width * get_pixel_size()) / 8, sizeof(uint32_t)); |
paul@0 | 242 | } |
paul@0 | 243 | |
paul@0 | 244 | // Return the screen memory size. |
paul@0 | 245 | |
paul@0 | 246 | l4_size_t |
paul@0 | 247 | Lcd_jz4740_chip::get_screen_size() |
paul@0 | 248 | { |
paul@0 | 249 | return get_line_size() * _panel->height; |
paul@0 | 250 | } |
paul@0 | 251 | |
paul@0 | 252 | // Return the aligned size for the DMA transfer. |
paul@0 | 253 | |
paul@0 | 254 | l4_size_t |
paul@0 | 255 | Lcd_jz4740_chip::get_aligned_size() |
paul@0 | 256 | { |
paul@0 | 257 | return align(get_screen_size(), _burst_size * sizeof(uint32_t)); |
paul@0 | 258 | } |
paul@0 | 259 | |
paul@0 | 260 | // Return the size of the palette. |
paul@0 | 261 | |
paul@0 | 262 | l4_size_t |
paul@0 | 263 | Lcd_jz4740_chip::get_palette_size() |
paul@0 | 264 | { |
paul@0 | 265 | // No palette for modes with more than eight bits per pixel. |
paul@0 | 266 | |
paul@0 | 267 | if (_panel->bpp > 8) return 0; |
paul@0 | 268 | |
paul@0 | 269 | // Get the size of a collection of two-byte entries, one per colour. |
paul@0 | 270 | |
paul@69 | 271 | return (1U << (_panel->bpp)) * sizeof(uint16_t); |
paul@0 | 272 | } |
paul@0 | 273 | |
paul@0 | 274 | // Return the aligned size of the palette for the DMA transfer. |
paul@0 | 275 | |
paul@0 | 276 | l4_size_t |
paul@0 | 277 | Lcd_jz4740_chip::get_aligned_palette_size() |
paul@0 | 278 | { |
paul@0 | 279 | return align(get_palette_size(), _burst_size * sizeof(uint32_t)); |
paul@0 | 280 | } |
paul@0 | 281 | |
paul@0 | 282 | // Return the total memory requirements of the framebuffers and palette. |
paul@0 | 283 | |
paul@0 | 284 | l4_size_t |
paul@0 | 285 | Lcd_jz4740_chip::get_total_size() |
paul@0 | 286 | { |
paul@0 | 287 | return get_aligned_size() * get_panels() + get_aligned_palette_size(); |
paul@0 | 288 | } |
paul@0 | 289 | |
paul@0 | 290 | // Return the total memory requirements of any DMA descriptors. |
paul@0 | 291 | |
paul@0 | 292 | l4_size_t |
paul@0 | 293 | Lcd_jz4740_chip::get_descriptors_size() |
paul@0 | 294 | { |
paul@0 | 295 | return 3 * sizeof(struct Jz4740_lcd_descriptor); |
paul@0 | 296 | } |
paul@0 | 297 | |
paul@0 | 298 | |
paul@0 | 299 | |
paul@0 | 300 | // Functions returning addresses of each data region. |
paul@0 | 301 | // The base parameter permits the retrieval of virtual or physical addresses. |
paul@0 | 302 | |
paul@0 | 303 | l4_addr_t |
paul@0 | 304 | Lcd_jz4740_chip::get_palette(l4_addr_t base) |
paul@0 | 305 | { |
paul@0 | 306 | // Use memory at the end of the allocated region for the palette. |
paul@0 | 307 | |
paul@0 | 308 | return base + (get_panels() * get_aligned_size()) - get_aligned_palette_size(); |
paul@0 | 309 | } |
paul@0 | 310 | |
paul@0 | 311 | l4_addr_t |
paul@0 | 312 | Lcd_jz4740_chip::get_framebuffer(int panel, l4_addr_t base) |
paul@0 | 313 | { |
paul@0 | 314 | // Framebuffers for panels are allocated at the start of the region. |
paul@0 | 315 | |
paul@0 | 316 | return base + (panel * get_aligned_size()); |
paul@0 | 317 | } |
paul@0 | 318 | |
paul@0 | 319 | |
paul@0 | 320 | |
paul@0 | 321 | // Palette initialisation. |
paul@0 | 322 | |
paul@0 | 323 | void |
paul@0 | 324 | Lcd_jz4740_chip::init_palette(l4_addr_t palette) |
paul@0 | 325 | { |
paul@69 | 326 | uint8_t colours = 1U << (_panel->bpp); |
paul@0 | 327 | uint16_t *entry = (uint16_t *) palette; |
paul@0 | 328 | uint16_t *end = entry + colours; |
paul@0 | 329 | uint8_t value = 0; |
paul@0 | 330 | |
paul@0 | 331 | while (entry < end) |
paul@0 | 332 | { |
paul@0 | 333 | switch (_panel->bpp) |
paul@0 | 334 | { |
paul@0 | 335 | case 4: |
paul@0 | 336 | *entry = rgb4_to_rgb16(value); |
paul@0 | 337 | break; |
paul@0 | 338 | |
paul@0 | 339 | case 8: |
paul@0 | 340 | *entry = rgb8_to_rgb16(value); |
paul@0 | 341 | break; |
paul@0 | 342 | |
paul@0 | 343 | default: |
paul@0 | 344 | break; |
paul@0 | 345 | } |
paul@0 | 346 | |
paul@0 | 347 | value++; |
paul@0 | 348 | entry++; |
paul@0 | 349 | } |
paul@0 | 350 | } |
paul@0 | 351 | |
paul@0 | 352 | |
paul@0 | 353 | |
paul@0 | 354 | // Return colour depth control value. |
paul@0 | 355 | // NOTE: Not supporting JZ4780 options. |
paul@0 | 356 | |
paul@0 | 357 | uint32_t |
paul@0 | 358 | Lcd_jz4740_chip::_control_bpp() |
paul@0 | 359 | { |
paul@0 | 360 | switch (_panel->bpp) |
paul@0 | 361 | { |
paul@0 | 362 | case 1: return Control_bpp_1bpp; |
paul@0 | 363 | case 2: return Control_bpp_2bpp; |
paul@0 | 364 | case 3 ... 4: return Control_bpp_4bpp; |
paul@0 | 365 | case 5 ... 8: return Control_bpp_8bpp; |
paul@0 | 366 | case 9 ... 15: return Control_bpp_15bpp | (Rgb_mode_555 << Control_rgb_mode); |
paul@0 | 367 | case 17 ... 18: return Control_bpp_18bpp; |
paul@0 | 368 | case 19 ... 32: return Control_bpp_24bpp; |
paul@0 | 369 | case 16: |
paul@0 | 370 | default: return Control_bpp_16bpp; |
paul@0 | 371 | } |
paul@0 | 372 | } |
paul@0 | 373 | |
paul@0 | 374 | // Return a panel-related control value. |
paul@0 | 375 | |
paul@0 | 376 | uint32_t |
paul@0 | 377 | Lcd_jz4740_chip::_control_panel() |
paul@0 | 378 | { |
paul@0 | 379 | if (have_stn_panel()) |
paul@69 | 380 | return _control_stn_frc() << Control_frc_algorithm; |
paul@0 | 381 | else |
paul@0 | 382 | return 0; |
paul@0 | 383 | } |
paul@0 | 384 | |
paul@0 | 385 | // Return a STN-related control value. |
paul@0 | 386 | |
paul@0 | 387 | uint32_t |
paul@0 | 388 | Lcd_jz4740_chip::_control_stn_frc() |
paul@0 | 389 | { |
paul@0 | 390 | if (_panel->bpp <= 2) |
paul@0 | 391 | return Frc_greyscales_2; |
paul@0 | 392 | if (_panel->bpp <= 4) |
paul@0 | 393 | return Frc_greyscales_4; |
paul@0 | 394 | return Frc_greyscales_16; |
paul@0 | 395 | } |
paul@0 | 396 | |
paul@0 | 397 | // Return a transfer-related control value. |
paul@0 | 398 | |
paul@0 | 399 | uint32_t |
paul@0 | 400 | Lcd_jz4740_chip::_control_transfer() |
paul@0 | 401 | { |
paul@0 | 402 | uint32_t length; |
paul@0 | 403 | |
paul@0 | 404 | switch (_burst_size) |
paul@0 | 405 | { |
paul@0 | 406 | case 4: length = Burst_length_4; break; |
paul@0 | 407 | case 8: length = Burst_length_8; break; |
paul@0 | 408 | case 32: length = Burst_length_32; break; |
paul@0 | 409 | case 64: length = Burst_length_64; break; |
paul@0 | 410 | case 16: |
paul@0 | 411 | default: length = Burst_length_16; break; |
paul@0 | 412 | } |
paul@0 | 413 | |
paul@138 | 414 | // NOTE: Underrun supposedly not needed. |
paul@138 | 415 | |
paul@69 | 416 | return (length << Control_burst_length) | (1U << Control_out_underrun); |
paul@69 | 417 | } |
paul@69 | 418 | |
paul@69 | 419 | // Return an interrupt-related control value. |
paul@69 | 420 | |
paul@69 | 421 | uint32_t |
paul@69 | 422 | Lcd_jz4740_chip::_control_irq() |
paul@69 | 423 | { |
paul@73 | 424 | return ((_irq_conditions & Lcd_irq_frame_start) ? (1U << Control_frame_start_irq_enable) : 0) | |
paul@69 | 425 | ((_irq_conditions & Lcd_irq_frame_end) ? (1U << Control_frame_end_irq_enable) : 0); |
paul@69 | 426 | } |
paul@69 | 427 | |
paul@69 | 428 | // Return an interrupt-related command value. |
paul@69 | 429 | |
paul@69 | 430 | uint32_t |
paul@69 | 431 | Lcd_jz4740_chip::_command_irq() |
paul@69 | 432 | { |
paul@69 | 433 | return ((_irq_conditions & Lcd_irq_frame_start) ? (1U << Command_frame_start_irq) : 0) | |
paul@69 | 434 | ((_irq_conditions & Lcd_irq_frame_end) ? (1U << Command_frame_end_irq) : 0); |
paul@69 | 435 | } |
paul@69 | 436 | |
paul@69 | 437 | // Return an interrupt-related status value. |
paul@69 | 438 | |
paul@69 | 439 | uint32_t |
paul@69 | 440 | Lcd_jz4740_chip::_status_irq() |
paul@69 | 441 | { |
paul@73 | 442 | return ((_irq_conditions & Lcd_irq_frame_start) ? (1U << Status_frame_start_irq) : 0) | |
paul@69 | 443 | ((_irq_conditions & Lcd_irq_frame_end) ? (1U << Status_frame_end_irq) : 0); |
paul@69 | 444 | } |
paul@69 | 445 | |
paul@0 | 446 | // STN panel-specific initialisation. |
paul@0 | 447 | |
paul@0 | 448 | void |
paul@0 | 449 | Lcd_jz4740_chip::_init_stn() |
paul@0 | 450 | { |
paul@0 | 451 | // Divide the height by the number of panels. |
paul@0 | 452 | |
paul@0 | 453 | uint32_t height = _panel->height / get_panels(); |
paul@0 | 454 | |
paul@0 | 455 | // Since the value is log2(pins), 1 << value yields the number of pins. |
paul@0 | 456 | |
paul@0 | 457 | int pins = 1 << ((_panel->config & Config_stn_pins_mask) >> Jz4740_lcd_config_stn_pins); |
paul@0 | 458 | |
paul@0 | 459 | // Round parameters up to a multiple of the number of pins. |
paul@0 | 460 | |
paul@0 | 461 | uint32_t hsync = align(_panel->hsync, pins); |
paul@0 | 462 | uint32_t line_start = align(_panel->line_start, pins); |
paul@0 | 463 | uint32_t line_end = align(_panel->line_end, pins); |
paul@0 | 464 | |
paul@0 | 465 | // Define the start and end positions of visible data on a line and in a frame. |
paul@0 | 466 | // Visible frame data is anchored at line zero, with the start region |
paul@0 | 467 | // preceding this line (and thus appearing at the end of the preceding frame). |
paul@0 | 468 | |
paul@0 | 469 | uint32_t line_start_pos = line_start; |
paul@0 | 470 | uint32_t line_end_pos = line_start_pos + _panel->width; |
paul@0 | 471 | uint32_t frame_start_pos = 0; |
paul@0 | 472 | uint32_t frame_end_pos = frame_start_pos + height; |
paul@0 | 473 | |
paul@0 | 474 | // Define sync pulse locations, with hsync occurring after the visible data. |
paul@0 | 475 | |
paul@0 | 476 | _regs[Lcd_hsync] = encode_pair(line_end_pos, line_end_pos + hsync); |
paul@0 | 477 | _regs[Lcd_vsync] = encode_pair(0, _panel->vsync); |
paul@0 | 478 | |
paul@0 | 479 | // Set the display area and limits. |
paul@0 | 480 | |
paul@69 | 481 | _regs[Virtual_area] = encode_pair(line_end_pos + hsync + line_end, |
paul@69 | 482 | frame_end_pos + _panel->vsync + _panel->frame_end + _panel->frame_start); |
paul@0 | 483 | |
paul@0 | 484 | _regs[Display_hlimits] = encode_pair(line_start_pos, line_end_pos); |
paul@0 | 485 | _regs[Display_vlimits] = encode_pair(frame_start_pos, frame_end_pos); |
paul@0 | 486 | |
paul@0 | 487 | // Set the AC bias signal. |
paul@0 | 488 | |
paul@0 | 489 | _regs[Lcd_ps] = encode_pair(0, _panel->frame_start + height + _panel->vsync + _panel->frame_end); |
paul@0 | 490 | } |
paul@0 | 491 | |
paul@0 | 492 | // TFT panel-specific initialisation. |
paul@0 | 493 | |
paul@0 | 494 | void |
paul@0 | 495 | Lcd_jz4740_chip::_init_tft() |
paul@0 | 496 | { |
paul@0 | 497 | // Define the start and end positions of visible data on a line and in a frame. |
paul@0 | 498 | |
paul@0 | 499 | uint32_t line_start_pos = _panel->line_start + _panel->hsync; |
paul@0 | 500 | uint32_t line_end_pos = line_start_pos + _panel->width; |
paul@0 | 501 | uint32_t frame_start_pos = _panel->frame_start + _panel->vsync; |
paul@0 | 502 | uint32_t frame_end_pos = frame_start_pos + _panel->height; |
paul@0 | 503 | |
paul@0 | 504 | // Define sync pulse locations, with pulses appearing before visible data. |
paul@0 | 505 | |
paul@0 | 506 | _regs[Lcd_hsync] = encode_pair(0, _panel->hsync); |
paul@0 | 507 | _regs[Lcd_vsync] = encode_pair(0, _panel->vsync); |
paul@0 | 508 | |
paul@0 | 509 | // Set the display area and limits. |
paul@0 | 510 | |
paul@69 | 511 | _regs[Virtual_area] = encode_pair(line_end_pos + _panel->line_end, |
paul@69 | 512 | frame_end_pos + _panel->frame_end); |
paul@0 | 513 | |
paul@0 | 514 | _regs[Display_hlimits] = encode_pair(line_start_pos, line_end_pos); |
paul@0 | 515 | _regs[Display_vlimits] = encode_pair(frame_start_pos, frame_end_pos); |
paul@0 | 516 | } |
paul@0 | 517 | |
paul@0 | 518 | // Initialise the panel. |
paul@0 | 519 | // NOTE: Only generic STN and TFT panels are supported. |
paul@0 | 520 | |
paul@0 | 521 | void |
paul@0 | 522 | Lcd_jz4740_chip::_init_panel() |
paul@0 | 523 | { |
paul@0 | 524 | if (have_stn_panel()) |
paul@0 | 525 | _init_stn(); |
paul@0 | 526 | else |
paul@0 | 527 | switch (_mode()) |
paul@0 | 528 | { |
paul@0 | 529 | case Jz4740_lcd_mode_tft_generic: |
paul@0 | 530 | case Jz4740_lcd_mode_tft_casio: |
paul@0 | 531 | case Jz4740_lcd_mode_tft_serial: _init_tft(); |
paul@0 | 532 | |
paul@0 | 533 | default: break; |
paul@0 | 534 | } |
paul@0 | 535 | } |
paul@0 | 536 | |
paul@0 | 537 | // Initialise a DMA descriptor. |
paul@0 | 538 | |
paul@0 | 539 | void |
paul@0 | 540 | Lcd_jz4740_chip::_set_descriptor(struct Jz4740_lcd_descriptor &desc, |
paul@0 | 541 | l4_addr_t source, l4_size_t size, |
paul@0 | 542 | struct Jz4740_lcd_descriptor *next, |
paul@75 | 543 | uint32_t flags) |
paul@0 | 544 | { |
paul@0 | 545 | // In the command, indicate the number of words from the source for transfer. |
paul@0 | 546 | |
paul@0 | 547 | desc.next = next; |
paul@75 | 548 | desc.source = source; |
paul@69 | 549 | desc.identifier = source; |
paul@69 | 550 | desc.command = ((size / sizeof(uint32_t)) & Command_buffer_length_mask) | |
paul@69 | 551 | flags; |
paul@0 | 552 | } |
paul@0 | 553 | |
paul@0 | 554 | // Initialise the LCD controller with the memory, panel and framebuffer details. |
paul@0 | 555 | // Any palette must be initialised separately using get_palette and init_palette. |
paul@0 | 556 | |
paul@0 | 557 | void |
paul@0 | 558 | Lcd_jz4740_chip::config(struct Jz4740_lcd_descriptor *desc_vaddr, |
paul@0 | 559 | struct Jz4740_lcd_descriptor *desc_paddr, |
paul@0 | 560 | l4_addr_t fb_paddr) |
paul@0 | 561 | { |
paul@0 | 562 | int have_palette = (_panel->bpp <= 8); |
paul@0 | 563 | |
paul@0 | 564 | // Provide the first framebuffer descriptor in single and dual modes. |
paul@0 | 565 | // Flip back and forth between any palette and the framebuffer. |
paul@0 | 566 | |
paul@0 | 567 | _set_descriptor(desc_vaddr[0], get_framebuffer(0, fb_paddr), |
paul@69 | 568 | get_aligned_size(), |
paul@69 | 569 | have_palette ? desc_paddr + 2 : desc_paddr, |
paul@69 | 570 | _command_irq()); |
paul@0 | 571 | |
paul@0 | 572 | // Provide the second framebuffer descriptor only in dual-panel mode. |
paul@0 | 573 | // Only employ this descriptor in the second DMA channel. |
paul@0 | 574 | |
paul@75 | 575 | if (get_panels() == 2) |
paul@0 | 576 | _set_descriptor(desc_vaddr[1], get_framebuffer(1, fb_paddr), |
paul@69 | 577 | get_aligned_size(), |
paul@69 | 578 | desc_paddr + 1, |
paul@75 | 579 | _command_irq()); |
paul@0 | 580 | |
paul@0 | 581 | // Initialise palette descriptor details for lower colour depths. |
paul@0 | 582 | |
paul@0 | 583 | if (have_palette) |
paul@0 | 584 | _set_descriptor(desc_vaddr[2], get_palette(fb_paddr), |
paul@69 | 585 | get_aligned_palette_size(), |
paul@0 | 586 | desc_paddr, |
paul@0 | 587 | Command_palette_buffer); |
paul@0 | 588 | |
paul@0 | 589 | // Flush cached structure data. |
paul@0 | 590 | |
paul@0 | 591 | l4_cache_clean_data((unsigned long) desc_vaddr, |
paul@0 | 592 | (unsigned long) desc_vaddr + get_descriptors_size()); |
paul@0 | 593 | |
paul@0 | 594 | // Configure DMA by setting frame descriptor addresses. |
paul@0 | 595 | |
paul@0 | 596 | // Provide the palette descriptor address first, if employed. |
paul@0 | 597 | |
paul@0 | 598 | _regs[Desc_address_0] = (uint32_t) (have_palette ? desc_paddr + 2 : desc_paddr); |
paul@0 | 599 | |
paul@0 | 600 | // Provide a descriptor for the second DMA channel in dual-panel mode. |
paul@0 | 601 | |
paul@75 | 602 | if (get_panels() == 2) |
paul@0 | 603 | _regs[Desc_address_1] = (uint32_t) (desc_paddr + 1); |
paul@0 | 604 | |
paul@0 | 605 | // Initialise panel-related registers. |
paul@0 | 606 | |
paul@0 | 607 | _init_panel(); |
paul@0 | 608 | |
paul@0 | 609 | // Initialise the control and configuration registers. |
paul@0 | 610 | |
paul@69 | 611 | _regs[Lcd_control] = _control_panel() | _control_bpp() | _control_transfer() | _control_irq(); |
paul@0 | 612 | _regs[Lcd_config] = _panel->config; |
paul@69 | 613 | } |
paul@69 | 614 | |
paul@69 | 615 | // Set the interrupt for controller-related events. |
paul@69 | 616 | |
paul@69 | 617 | void |
paul@69 | 618 | Lcd_jz4740_chip::set_irq(l4_cap_idx_t irq, enum Jz4740_lcd_irq_condition conditions) |
paul@69 | 619 | { |
paul@69 | 620 | _irq = irq; |
paul@69 | 621 | _irq_conditions = conditions; |
paul@69 | 622 | } |
paul@69 | 623 | |
paul@69 | 624 | // Wait for an interrupt condition. |
paul@69 | 625 | |
paul@69 | 626 | long |
paul@69 | 627 | Lcd_jz4740_chip::wait_for_irq() |
paul@69 | 628 | { |
paul@69 | 629 | l4_msgtag_t tag; |
paul@69 | 630 | |
paul@69 | 631 | _regs[Lcd_status] = _regs[Lcd_status] & ~(_status_irq()); |
paul@69 | 632 | |
paul@268 | 633 | long err = l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0)); |
paul@268 | 634 | |
paul@268 | 635 | if (err) |
paul@268 | 636 | return err; |
paul@268 | 637 | |
paul@69 | 638 | // Wait for a condition. |
paul@69 | 639 | |
paul@72 | 640 | tag = l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(2000000))); |
paul@72 | 641 | |
paul@69 | 642 | // Acknowledge interrupts. |
paul@69 | 643 | |
paul@72 | 644 | _regs[Lcd_status] = 0; |
paul@69 | 645 | |
paul@72 | 646 | // Return errors. |
paul@72 | 647 | |
paul@72 | 648 | return l4_error(tag); |
paul@0 | 649 | } |
paul@0 | 650 | |
paul@0 | 651 | |
paul@0 | 652 | |
paul@0 | 653 | // C language interface functions. |
paul@0 | 654 | |
paul@0 | 655 | void * |
paul@0 | 656 | jz4740_lcd_init(l4_addr_t lcd_base, struct Jz4740_lcd_panel *panel) |
paul@0 | 657 | { |
paul@0 | 658 | return (void *) new Lcd_jz4740_chip(lcd_base, panel); |
paul@0 | 659 | } |
paul@0 | 660 | |
paul@0 | 661 | void |
paul@0 | 662 | jz4740_lcd_config(void *lcd, struct Jz4740_lcd_descriptor *desc_vaddr, |
paul@0 | 663 | struct Jz4740_lcd_descriptor *desc_paddr, |
paul@0 | 664 | l4_addr_t fb_paddr) |
paul@0 | 665 | { |
paul@0 | 666 | static_cast<Lcd_jz4740_chip *>(lcd)->config(desc_vaddr, desc_paddr, fb_paddr); |
paul@0 | 667 | } |
paul@0 | 668 | |
paul@0 | 669 | void |
paul@69 | 670 | jz4740_lcd_set_irq(void *lcd, l4_cap_idx_t irq, enum Jz4740_lcd_irq_condition conditions) |
paul@69 | 671 | { |
paul@69 | 672 | static_cast<Lcd_jz4740_chip *>(lcd)->set_irq(irq, conditions); |
paul@69 | 673 | } |
paul@69 | 674 | |
paul@69 | 675 | long |
paul@69 | 676 | jz4740_lcd_wait_for_irq(void *lcd) |
paul@69 | 677 | { |
paul@69 | 678 | return static_cast<Lcd_jz4740_chip *>(lcd)->wait_for_irq(); |
paul@69 | 679 | } |
paul@69 | 680 | |
paul@69 | 681 | void |
paul@0 | 682 | jz4740_lcd_disable(void *lcd) |
paul@0 | 683 | { |
paul@0 | 684 | static_cast<Lcd_jz4740_chip *>(lcd)->disable(); |
paul@0 | 685 | } |
paul@0 | 686 | |
paul@0 | 687 | void |
paul@0 | 688 | jz4740_lcd_disable_quick(void *lcd) |
paul@0 | 689 | { |
paul@0 | 690 | static_cast<Lcd_jz4740_chip *>(lcd)->disable_quick(); |
paul@0 | 691 | } |
paul@0 | 692 | |
paul@0 | 693 | void |
paul@0 | 694 | jz4740_lcd_enable(void *lcd) |
paul@0 | 695 | { |
paul@0 | 696 | static_cast<Lcd_jz4740_chip *>(lcd)->enable(); |
paul@0 | 697 | } |
paul@0 | 698 | |
paul@0 | 699 | int |
paul@69 | 700 | jz4740_lcd_enabled(void *lcd) |
paul@69 | 701 | { |
paul@69 | 702 | return (int) static_cast<Lcd_jz4740_chip *>(lcd)->enabled(); |
paul@69 | 703 | } |
paul@69 | 704 | |
paul@69 | 705 | int |
paul@0 | 706 | jz4740_lcd_get_pixel_clock(void *lcd) |
paul@0 | 707 | { |
paul@0 | 708 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_pixel_clock(); |
paul@0 | 709 | } |
paul@0 | 710 | |
paul@69 | 711 | l4_size_t |
paul@69 | 712 | jz4740_lcd_get_descriptors_size(void *lcd) |
paul@69 | 713 | { |
paul@69 | 714 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_descriptors_size(); |
paul@69 | 715 | } |
paul@69 | 716 | |
paul@69 | 717 | l4_size_t |
paul@72 | 718 | jz4740_lcd_get_line_size(void *lcd) |
paul@72 | 719 | { |
paul@72 | 720 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_line_size(); |
paul@72 | 721 | } |
paul@72 | 722 | |
paul@72 | 723 | l4_size_t |
paul@69 | 724 | jz4740_lcd_get_screen_size(void *lcd) |
paul@69 | 725 | { |
paul@69 | 726 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_screen_size(); |
paul@69 | 727 | } |
paul@69 | 728 | |
paul@0 | 729 | l4_addr_t |
paul@0 | 730 | jz4740_lcd_get_palette(void *lcd, l4_addr_t base) |
paul@0 | 731 | { |
paul@0 | 732 | return static_cast<Lcd_jz4740_chip *>(lcd)->get_palette(base); |
paul@0 | 733 | } |
paul@0 | 734 | |
paul@0 | 735 | void |
paul@0 | 736 | jz4740_lcd_init_palette(void *lcd, l4_addr_t palette) |
paul@0 | 737 | { |
paul@0 | 738 | static_cast<Lcd_jz4740_chip *>(lcd)->init_palette(palette); |
paul@0 | 739 | } |