paul@250 | 1 | /* |
paul@250 | 2 | * Timer/counter unit support. |
paul@250 | 3 | * |
paul@250 | 4 | * Copyright (C) 2024 Paul Boddie <paul@boddie.org.uk> |
paul@250 | 5 | * |
paul@250 | 6 | * This program is free software; you can redistribute it and/or |
paul@250 | 7 | * modify it under the terms of the GNU General Public License as |
paul@250 | 8 | * published by the Free Software Foundation; either version 2 of |
paul@250 | 9 | * the License, or (at your option) any later version. |
paul@250 | 10 | * |
paul@250 | 11 | * This program is distributed in the hope that it will be useful, |
paul@250 | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@250 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@250 | 14 | * GNU General Public License for more details. |
paul@250 | 15 | * |
paul@250 | 16 | * You should have received a copy of the GNU General Public License |
paul@250 | 17 | * along with this program; if not, write to the Free Software |
paul@250 | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@250 | 19 | * Boston, MA 02110-1301, USA |
paul@250 | 20 | */ |
paul@250 | 21 | |
paul@250 | 22 | #include <l4/devices/hw_mmio_register_block.h> |
paul@250 | 23 | #include <l4/sys/err.h> |
paul@252 | 24 | #include <l4/sys/irq.h> |
paul@268 | 25 | #include <l4/sys/rcv_endpoint.h> |
paul@252 | 26 | #include <l4/util/util.h> |
paul@250 | 27 | |
paul@268 | 28 | #include <pthread.h> |
paul@268 | 29 | #include <pthread-l4.h> |
paul@268 | 30 | |
paul@252 | 31 | #include <math.h> // log2 |
paul@250 | 32 | |
paul@250 | 33 | #include "tcu-common.h" |
paul@250 | 34 | |
paul@250 | 35 | |
paul@250 | 36 | |
paul@250 | 37 | // Register locations. |
paul@250 | 38 | |
paul@250 | 39 | enum Regs : unsigned |
paul@250 | 40 | { |
paul@250 | 41 | Tcu_enable_status = 0x010, // TER |
paul@250 | 42 | Tcu_set_enable = 0x014, // TESR |
paul@250 | 43 | Tcu_clear_enable = 0x018, // TECR |
paul@250 | 44 | Tcu_stop_status = 0x01c, // TSR |
paul@250 | 45 | Tcu_set_stop = 0x02c, // TSSR |
paul@250 | 46 | Tcu_clear_stop = 0x03c, // TSCR |
paul@250 | 47 | Tcu_flag_status = 0x020, // TFR |
paul@250 | 48 | Tcu_set_flag = 0x024, // TFSR |
paul@250 | 49 | Tcu_clear_flag = 0x028, // TFCR |
paul@250 | 50 | Tcu_mask_status = 0x030, // TMR |
paul@250 | 51 | Tcu_set_mask = 0x034, // TMSR |
paul@250 | 52 | Tcu_clear_mask = 0x038, // TMCR |
paul@250 | 53 | |
paul@250 | 54 | // Channel-related locations. |
paul@250 | 55 | |
paul@250 | 56 | Tcu_full_data_value_base = 0x040, // TDFRn |
paul@250 | 57 | Tcu_half_data_value_base = 0x044, // TDHRn |
paul@250 | 58 | Tcu_counter_base = 0x048, // TCNTn |
paul@250 | 59 | Tcu_control_base = 0x04c, // TCRn |
paul@250 | 60 | |
paul@250 | 61 | // Block size/step/offset for the above register set. |
paul@250 | 62 | |
paul@250 | 63 | Tcu_data_block_offset = 0x010, |
paul@250 | 64 | }; |
paul@250 | 65 | |
paul@250 | 66 | // Field definitions. |
paul@250 | 67 | |
paul@250 | 68 | // Enable/stop register bits. |
paul@250 | 69 | |
paul@250 | 70 | enum Channel_bit_numbers : unsigned |
paul@250 | 71 | { |
paul@250 | 72 | Channel_wdt = 16, // WDTS only |
paul@250 | 73 | |
paul@250 | 74 | // Enable/stop/flag/mask bit numbers. |
paul@250 | 75 | |
paul@250 | 76 | Channel_ost = 15, // OSTEN/OSTS/OSTFLAG |
paul@250 | 77 | Channel_tcu7 = 7, // TCEN7/STOP7/FFLAG7/SFLAG7 |
paul@250 | 78 | Channel_tcu6 = 6, // TCEN6/STOP6/FFLAG6/SFLAG6 |
paul@250 | 79 | Channel_tcu5 = 5, // TCEN5/STOP5/FFLAG5/SFLAG5 |
paul@250 | 80 | Channel_tcu4 = 4, // TCEN4/STOP4/FFLAG4/SFLAG4 |
paul@250 | 81 | Channel_tcu3 = 3, // TCEN3/STOP3/FFLAG3/SFLAG3 |
paul@250 | 82 | Channel_tcu2 = 2, // TCEN2/STOP2/FFLAG2/SFLAG2 |
paul@250 | 83 | Channel_tcu1 = 1, // TCEN1/STOP1/FFLAG1/SFLAG1 |
paul@250 | 84 | Channel_tcu0 = 0, // TCEN0/STOP0/FFLAG0/SFLAG0 |
paul@250 | 85 | }; |
paul@250 | 86 | |
paul@252 | 87 | // Flag/mask register bits. |
paul@252 | 88 | |
paul@252 | 89 | enum Flag_bit_numbers : unsigned |
paul@252 | 90 | { |
paul@252 | 91 | Half_match_wdt = 24, // HFLAGW |
paul@252 | 92 | |
paul@252 | 93 | // Flag/mask group bit offsets. |
paul@252 | 94 | |
paul@252 | 95 | Half_match_shift = 16, |
paul@252 | 96 | Full_match_shift = 0, |
paul@252 | 97 | }; |
paul@252 | 98 | |
paul@250 | 99 | // Counter data constraints. |
paul@250 | 100 | |
paul@250 | 101 | enum Data_masks : unsigned |
paul@250 | 102 | { |
paul@250 | 103 | Data_mask = 0xffff, |
paul@250 | 104 | }; |
paul@250 | 105 | |
paul@250 | 106 | enum Control_bits : unsigned |
paul@250 | 107 | { |
paul@250 | 108 | Count_prescale_field_mask = 0x7, // PRESCALE |
paul@250 | 109 | Count_prescale_max = 5, // CLK/1024 |
paul@250 | 110 | Count_prescale_field_shift = 3, |
paul@250 | 111 | |
paul@250 | 112 | Count_clock_field_mask = 0x7, |
paul@250 | 113 | Count_clock_exclk = 4, // EXT_EN |
paul@250 | 114 | Count_clock_rtclk = 2, // RTC_EN |
paul@250 | 115 | Count_clock_pclk = 1, // PCK_EN |
paul@250 | 116 | Count_clock_field_shift = 0, |
paul@250 | 117 | }; |
paul@250 | 118 | |
paul@250 | 119 | |
paul@250 | 120 | |
paul@250 | 121 | // Channel abstraction. |
paul@250 | 122 | |
paul@252 | 123 | Tcu_channel::Tcu_channel(l4_addr_t addr, uint8_t channel, l4_cap_idx_t irq) |
paul@252 | 124 | : _channel(channel), _irq(irq) |
paul@250 | 125 | { |
paul@250 | 126 | _regs = new Hw::Mmio_register_block<32>(addr); |
paul@250 | 127 | } |
paul@250 | 128 | |
paul@250 | 129 | // Utility methods. |
paul@250 | 130 | // NOTE: Also defined in the CPM abstraction, should be consolidated. |
paul@250 | 131 | |
paul@250 | 132 | uint32_t |
paul@250 | 133 | Tcu_channel::get_field(uint32_t reg, uint32_t mask, uint8_t shift) |
paul@250 | 134 | { |
paul@250 | 135 | return (_regs[reg] & (mask << shift)) >> shift; |
paul@250 | 136 | } |
paul@250 | 137 | |
paul@250 | 138 | void |
paul@250 | 139 | Tcu_channel::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) |
paul@250 | 140 | { |
paul@250 | 141 | _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); |
paul@250 | 142 | } |
paul@250 | 143 | |
paul@250 | 144 | // Operation methods. |
paul@250 | 145 | |
paul@250 | 146 | uint8_t |
paul@250 | 147 | Tcu_channel::get_clock() |
paul@250 | 148 | { |
paul@250 | 149 | return (uint8_t) get_field(Tcu_control_base + _channel * Tcu_data_block_offset, |
paul@250 | 150 | Count_clock_field_mask, Count_clock_field_shift); |
paul@250 | 151 | } |
paul@250 | 152 | |
paul@250 | 153 | void |
paul@250 | 154 | Tcu_channel::set_clock(uint8_t clock) |
paul@250 | 155 | { |
paul@250 | 156 | |
paul@250 | 157 | set_field(Tcu_control_base + _channel * Tcu_data_block_offset, |
paul@250 | 158 | Count_clock_field_mask, Count_clock_field_shift, clock); |
paul@250 | 159 | } |
paul@250 | 160 | |
paul@250 | 161 | uint32_t |
paul@250 | 162 | Tcu_channel::get_prescale() |
paul@250 | 163 | { |
paul@250 | 164 | return 1UL << (2 * get_field(Tcu_control_base + _channel * Tcu_data_block_offset, |
paul@250 | 165 | Count_prescale_field_mask, Count_prescale_field_shift)); |
paul@250 | 166 | } |
paul@250 | 167 | |
paul@250 | 168 | void |
paul@250 | 169 | Tcu_channel::set_prescale(uint32_t prescale) |
paul@250 | 170 | { |
paul@250 | 171 | // Obtain the log4 value for prescale. |
paul@250 | 172 | |
paul@250 | 173 | uint32_t value = (uint32_t) log2(prescale) / 2; |
paul@250 | 174 | |
paul@250 | 175 | set_field(Tcu_control_base + _channel * Tcu_data_block_offset, |
paul@250 | 176 | Count_prescale_field_mask, Count_prescale_field_shift, |
paul@250 | 177 | value > Count_prescale_max ? Count_prescale_max : value); |
paul@250 | 178 | } |
paul@250 | 179 | |
paul@250 | 180 | void |
paul@250 | 181 | Tcu_channel::disable() |
paul@250 | 182 | { |
paul@250 | 183 | _regs[Tcu_clear_enable] = 1UL << _channel; |
paul@250 | 184 | } |
paul@250 | 185 | |
paul@250 | 186 | void |
paul@250 | 187 | Tcu_channel::enable() |
paul@250 | 188 | { |
paul@250 | 189 | _regs[Tcu_set_enable] = 1UL << _channel; |
paul@250 | 190 | } |
paul@250 | 191 | |
paul@250 | 192 | bool |
paul@250 | 193 | Tcu_channel::is_enabled() |
paul@250 | 194 | { |
paul@250 | 195 | return _regs[Tcu_enable_status] & (1UL << _channel); |
paul@250 | 196 | } |
paul@250 | 197 | |
paul@250 | 198 | uint32_t |
paul@250 | 199 | Tcu_channel::get_counter() |
paul@250 | 200 | { |
paul@250 | 201 | return _regs[Tcu_counter_base + _channel * Tcu_data_block_offset] & Data_mask; |
paul@250 | 202 | } |
paul@250 | 203 | |
paul@250 | 204 | void |
paul@250 | 205 | Tcu_channel::set_counter(uint32_t value) |
paul@250 | 206 | { |
paul@250 | 207 | _regs[Tcu_counter_base + _channel * Tcu_data_block_offset] = value & Data_mask; |
paul@250 | 208 | } |
paul@250 | 209 | |
paul@250 | 210 | uint8_t |
paul@250 | 211 | Tcu_channel::get_count_mode() |
paul@250 | 212 | { |
paul@250 | 213 | return 0; |
paul@250 | 214 | } |
paul@250 | 215 | |
paul@250 | 216 | void |
paul@250 | 217 | Tcu_channel::set_count_mode(uint8_t mode) |
paul@250 | 218 | { |
paul@250 | 219 | if (mode != 0) |
paul@250 | 220 | throw -L4_EINVAL; |
paul@250 | 221 | } |
paul@250 | 222 | |
paul@250 | 223 | uint32_t |
paul@250 | 224 | Tcu_channel::get_full_data_value() |
paul@250 | 225 | { |
paul@250 | 226 | return _regs[Tcu_full_data_value_base + _channel * Tcu_data_block_offset] & Data_mask; |
paul@250 | 227 | } |
paul@250 | 228 | |
paul@250 | 229 | void |
paul@250 | 230 | Tcu_channel::set_full_data_value(uint32_t value) |
paul@250 | 231 | { |
paul@250 | 232 | _regs[Tcu_full_data_value_base + _channel * Tcu_data_block_offset] = value & Data_mask; |
paul@250 | 233 | } |
paul@250 | 234 | |
paul@250 | 235 | uint32_t |
paul@250 | 236 | Tcu_channel::get_half_data_value() |
paul@250 | 237 | { |
paul@250 | 238 | return _regs[Tcu_half_data_value_base + _channel * Tcu_data_block_offset] & Data_mask; |
paul@250 | 239 | } |
paul@250 | 240 | |
paul@250 | 241 | void |
paul@250 | 242 | Tcu_channel::set_half_data_value(uint32_t value) |
paul@250 | 243 | { |
paul@250 | 244 | _regs[Tcu_half_data_value_base + _channel * Tcu_data_block_offset] = value & Data_mask; |
paul@250 | 245 | } |
paul@250 | 246 | |
paul@252 | 247 | bool |
paul@252 | 248 | Tcu_channel::get_full_data_mask() |
paul@252 | 249 | { |
paul@252 | 250 | return _regs[Tcu_mask_status] & (1UL << (_channel + Full_match_shift)); |
paul@252 | 251 | } |
paul@252 | 252 | |
paul@252 | 253 | void |
paul@252 | 254 | Tcu_channel::set_full_data_mask(bool masked) |
paul@252 | 255 | { |
paul@252 | 256 | _regs[masked ? Tcu_set_mask : Tcu_clear_mask] = (1UL << (_channel + Full_match_shift)); |
paul@252 | 257 | } |
paul@252 | 258 | |
paul@252 | 259 | bool |
paul@252 | 260 | Tcu_channel::get_half_data_mask() |
paul@252 | 261 | { |
paul@252 | 262 | return _regs[Tcu_mask_status] & (1UL << (_channel + Half_match_shift)); |
paul@252 | 263 | } |
paul@252 | 264 | |
paul@252 | 265 | void |
paul@252 | 266 | Tcu_channel::set_half_data_mask(bool masked) |
paul@252 | 267 | { |
paul@252 | 268 | _regs[masked ? Tcu_set_mask : Tcu_clear_mask] = (1UL << (_channel + Half_match_shift)); |
paul@252 | 269 | } |
paul@252 | 270 | |
paul@252 | 271 | // Wait indefinitely for an interrupt request, returning true if one was delivered. |
paul@252 | 272 | |
paul@252 | 273 | bool |
paul@252 | 274 | Tcu_channel::wait_for_irq() |
paul@268 | 275 | { |
paul@268 | 276 | if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) |
paul@268 | 277 | return false; |
paul@268 | 278 | |
paul@252 | 279 | bool irq = !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && have_interrupt(); |
paul@252 | 280 | |
paul@252 | 281 | if (irq) |
paul@252 | 282 | ack_irq(); |
paul@252 | 283 | |
paul@252 | 284 | return irq; |
paul@252 | 285 | } |
paul@252 | 286 | |
paul@252 | 287 | // Wait up to the given timeout (in microseconds) for an interrupt request, |
paul@252 | 288 | // returning true if one was delivered. |
paul@252 | 289 | |
paul@252 | 290 | bool |
paul@252 | 291 | Tcu_channel::wait_for_irq(unsigned int timeout) |
paul@252 | 292 | { |
paul@268 | 293 | if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) |
paul@268 | 294 | return false; |
paul@268 | 295 | |
paul@252 | 296 | bool irq = !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))) && have_interrupt(); |
paul@252 | 297 | |
paul@252 | 298 | if (irq) |
paul@252 | 299 | ack_irq(); |
paul@252 | 300 | |
paul@252 | 301 | return irq; |
paul@252 | 302 | } |
paul@252 | 303 | |
paul@252 | 304 | // Acknowledge an interrupt condition. |
paul@252 | 305 | |
paul@252 | 306 | void |
paul@252 | 307 | Tcu_channel::ack_irq() |
paul@252 | 308 | { |
paul@252 | 309 | _regs[Tcu_clear_flag] = 1UL << _channel; |
paul@252 | 310 | } |
paul@252 | 311 | |
paul@252 | 312 | // Return whether an interrupt is pending on the given channel. |
paul@252 | 313 | |
paul@252 | 314 | bool |
paul@252 | 315 | Tcu_channel::have_interrupt() |
paul@252 | 316 | { |
paul@252 | 317 | return _regs[Tcu_flag_status] & (1UL << _channel) ? true : false; |
paul@252 | 318 | } |
paul@252 | 319 | |
paul@250 | 320 | |
paul@250 | 321 | |
paul@250 | 322 | // Peripheral abstraction. |
paul@250 | 323 | |
paul@250 | 324 | Tcu_chip::Tcu_chip(l4_addr_t start, l4_addr_t end) |
paul@250 | 325 | : _start(start), _end(end) |
paul@250 | 326 | { |
paul@250 | 327 | } |
paul@250 | 328 | |
paul@250 | 329 | // Obtain a channel object. |
paul@250 | 330 | |
paul@250 | 331 | Tcu_channel * |
paul@252 | 332 | Tcu_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) |
paul@250 | 333 | { |
paul@250 | 334 | if (channel < num_channels()) |
paul@252 | 335 | return _get_channel(_start, channel, irq); |
paul@250 | 336 | else |
paul@250 | 337 | throw -L4_EINVAL; |
paul@250 | 338 | } |