paul@0 | 1 | /* |
paul@0 | 2 | * GPIO driver for Ingenic JZ4740. |
paul@0 | 3 | * (See below for additional copyright and licensing notices.) |
paul@0 | 4 | * |
paul@188 | 5 | * Copyright (C) 2017, 2018, 2023 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 6 | * |
paul@0 | 7 | * This program is free software; you can redistribute it and/or |
paul@0 | 8 | * modify it under the terms of the GNU General Public License as |
paul@0 | 9 | * published by the Free Software Foundation; either version 2 of |
paul@0 | 10 | * the License, or (at your option) any later version. |
paul@0 | 11 | * |
paul@0 | 12 | * This program is distributed in the hope that it will be useful, |
paul@0 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@0 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@0 | 15 | * GNU General Public License for more details. |
paul@0 | 16 | * |
paul@0 | 17 | * You should have received a copy of the GNU General Public License |
paul@0 | 18 | * along with this program; if not, write to the Free Software |
paul@0 | 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@0 | 20 | * Boston, MA 02110-1301, USA |
paul@0 | 21 | * |
paul@0 | 22 | * |
paul@0 | 23 | * Subject to other copyrights, being derived from the bcm2835.cc and |
paul@0 | 24 | * omap.cc GPIO driver implementations. |
paul@0 | 25 | * |
paul@0 | 26 | * This file is part of TUD:OS and distributed under the terms of the |
paul@0 | 27 | * GNU General Public License 2. |
paul@0 | 28 | * Please see the COPYING-GPL-2 file for details. |
paul@0 | 29 | */ |
paul@0 | 30 | |
paul@0 | 31 | #include <l4/sys/icu.h> |
paul@0 | 32 | #include <l4/util/util.h> |
paul@0 | 33 | #include <l4/devices/hw_mmio_register_block.h> |
paul@0 | 34 | |
paul@0 | 35 | #include "gpio-jz4740.h" |
paul@0 | 36 | |
paul@0 | 37 | // GPIO register offsets (x in A..D). |
paul@0 | 38 | |
paul@0 | 39 | enum Regs |
paul@0 | 40 | { |
paul@0 | 41 | Pin_level = 0x000, // PxPIN (read-only) |
paul@0 | 42 | Port_data = 0x010, // PxDAT (read-only) |
paul@0 | 43 | Port_data_set = 0x014, // PxDATS |
paul@0 | 44 | Port_data_clear = 0x018, // PxDATC |
paul@0 | 45 | Irq_mask = 0x020, // PxIM (read-only) |
paul@0 | 46 | Irq_mask_set = 0x024, // PxIMS |
paul@0 | 47 | Irq_mask_clear = 0x028, // PxIMC |
paul@0 | 48 | Pull_disable = 0x030, // PxPE (read-only) |
paul@0 | 49 | Pull_disable_set = 0x034, // PxPES |
paul@0 | 50 | Pull_disable_clear = 0x038, // PxPEC |
paul@0 | 51 | Port_function = 0x040, // PxFUN (read-only) |
paul@0 | 52 | Port_function_set = 0x044, // PxFUNS |
paul@0 | 53 | Port_function_clear = 0x048, // PxFUNC |
paul@0 | 54 | Port_select = 0x050, // PxSEL (read-only) |
paul@0 | 55 | Port_select_set = 0x054, // PxSELS |
paul@0 | 56 | Port_select_clear = 0x058, // PxSELC |
paul@0 | 57 | Port_dir = 0x060, // PxDIR (read-only) |
paul@0 | 58 | Port_dir_set = 0x064, // PxDIRS |
paul@0 | 59 | Port_dir_clear = 0x068, // PxDIRC |
paul@0 | 60 | Port_trigger = 0x070, // PxTRG (read-only) |
paul@0 | 61 | Port_trigger_set = 0x074, // PxTRGS |
paul@0 | 62 | Port_trigger_clear = 0x078, // PxTRGC |
paul@0 | 63 | Irq_flag = 0x080, // PxFLG (read-only) |
paul@0 | 64 | Irq_flag_clear = 0x084, // PxFLGC |
paul@0 | 65 | }; |
paul@0 | 66 | |
paul@0 | 67 | |
paul@0 | 68 | |
paul@0 | 69 | // IRQ control for each GPIO pin. |
paul@0 | 70 | |
paul@0 | 71 | Gpio_jz4740_irq_pin::Gpio_jz4740_irq_pin(unsigned pin, Hw::Register_block<32> const ®s) |
paul@0 | 72 | : _pin(pin), _regs(regs) |
paul@0 | 73 | {} |
paul@0 | 74 | |
paul@0 | 75 | void |
paul@0 | 76 | Gpio_jz4740_irq_pin::write_reg_pin(unsigned reg) |
paul@0 | 77 | { |
paul@0 | 78 | // Write the pin bit to the register, setting or clearing the pin |
paul@0 | 79 | // depending on the register chosen. |
paul@0 | 80 | |
paul@0 | 81 | _regs[reg] = _pin_bit(_pin); |
paul@0 | 82 | } |
paul@0 | 83 | |
paul@0 | 84 | void Gpio_jz4740_irq_pin::do_mask() |
paul@0 | 85 | { |
paul@0 | 86 | // Set the interrupt bit in the PxIM register. |
paul@0 | 87 | |
paul@0 | 88 | write_reg_pin(Irq_mask_set); |
paul@0 | 89 | } |
paul@0 | 90 | |
paul@0 | 91 | void Gpio_jz4740_irq_pin::do_unmask() |
paul@0 | 92 | { |
paul@0 | 93 | // Clear the interrupt bit in the PxIM register, first also clearing the |
paul@0 | 94 | // flag bit in the PxFLG register to allow interrupts to be delivered. |
paul@0 | 95 | |
paul@0 | 96 | write_reg_pin(Irq_flag_clear); |
paul@0 | 97 | write_reg_pin(Irq_mask_clear); |
paul@0 | 98 | } |
paul@0 | 99 | |
paul@0 | 100 | bool Gpio_jz4740_irq_pin::do_set_mode(unsigned mode) |
paul@0 | 101 | { |
paul@0 | 102 | // Standard comment found for this method: |
paul@0 | 103 | // this operation touches multiple mmio registers and is thus |
paul@0 | 104 | // not atomic, that's why we first mask the IRQ and if it was |
paul@0 | 105 | // enabled we unmask it after we have changed the mode |
paul@0 | 106 | |
paul@0 | 107 | if (enabled()) |
paul@0 | 108 | do_mask(); |
paul@0 | 109 | |
paul@0 | 110 | // Do the PxTRG, PxFUN, PxSEL and PxDIR configuration. |
paul@0 | 111 | |
paul@0 | 112 | switch(mode) |
paul@0 | 113 | { |
paul@0 | 114 | case L4_IRQ_F_LEVEL_HIGH: |
paul@0 | 115 | write_reg_pin(Port_trigger_clear); |
paul@0 | 116 | write_reg_pin(Port_function_clear); |
paul@0 | 117 | write_reg_pin(Port_select_set); |
paul@0 | 118 | write_reg_pin(Port_dir_set); |
paul@0 | 119 | break; |
paul@0 | 120 | case L4_IRQ_F_LEVEL_LOW: |
paul@0 | 121 | write_reg_pin(Port_trigger_clear); |
paul@0 | 122 | write_reg_pin(Port_function_clear); |
paul@0 | 123 | write_reg_pin(Port_select_set); |
paul@0 | 124 | write_reg_pin(Port_dir_clear); |
paul@0 | 125 | break; |
paul@0 | 126 | case L4_IRQ_F_POS_EDGE: |
paul@0 | 127 | write_reg_pin(Port_trigger_set); |
paul@0 | 128 | write_reg_pin(Port_function_clear); |
paul@0 | 129 | write_reg_pin(Port_select_set); |
paul@0 | 130 | write_reg_pin(Port_dir_set); |
paul@0 | 131 | break; |
paul@0 | 132 | case L4_IRQ_F_NEG_EDGE: |
paul@0 | 133 | write_reg_pin(Port_trigger_set); |
paul@0 | 134 | write_reg_pin(Port_function_clear); |
paul@0 | 135 | write_reg_pin(Port_select_set); |
paul@0 | 136 | write_reg_pin(Port_dir_clear); |
paul@0 | 137 | break; |
paul@0 | 138 | |
paul@0 | 139 | default: |
paul@0 | 140 | return false; |
paul@0 | 141 | } |
paul@0 | 142 | |
paul@0 | 143 | if (enabled()) |
paul@0 | 144 | do_unmask(); |
paul@0 | 145 | |
paul@0 | 146 | return true; |
paul@0 | 147 | } |
paul@0 | 148 | |
paul@0 | 149 | int Gpio_jz4740_irq_pin::clear() |
paul@0 | 150 | { |
paul@0 | 151 | // Obtain the flag status for the pin, clearing it if set. |
paul@0 | 152 | |
paul@0 | 153 | l4_uint32_t e = _regs[Irq_flag] & (1UL << _pin); |
paul@0 | 154 | if (e) |
paul@0 | 155 | _regs[Irq_flag_clear] = e; |
paul@0 | 156 | |
paul@0 | 157 | return (e >> _pin); |
paul@0 | 158 | } |
paul@0 | 159 | |
paul@0 | 160 | bool Gpio_jz4740_irq_pin::enabled() |
paul@0 | 161 | { |
paul@0 | 162 | return true; |
paul@0 | 163 | } |
paul@0 | 164 | |
paul@0 | 165 | |
paul@0 | 166 | |
paul@0 | 167 | // Initialise the GPIO controller. |
paul@0 | 168 | |
paul@0 | 169 | Gpio_jz4740_chip::Gpio_jz4740_chip(l4_addr_t start, l4_addr_t end, |
paul@0 | 170 | unsigned nr_pins) |
paul@0 | 171 | : _start(start), _end(end), |
paul@0 | 172 | _nr_pins(nr_pins) |
paul@0 | 173 | { |
paul@0 | 174 | _regs = new Hw::Mmio_register_block<32>(_start); |
paul@0 | 175 | } |
paul@0 | 176 | |
paul@0 | 177 | // Return the value of a pin. |
paul@0 | 178 | |
paul@0 | 179 | int |
paul@0 | 180 | Gpio_jz4740_chip::get(unsigned pin) |
paul@0 | 181 | { |
paul@0 | 182 | if (pin >= _nr_pins) |
paul@0 | 183 | throw -L4_EINVAL; |
paul@0 | 184 | |
paul@0 | 185 | l4_uint32_t val = _regs[Pin_level]; |
paul@0 | 186 | return (val >> _pin_shift(pin)) & 1; |
paul@0 | 187 | } |
paul@0 | 188 | |
paul@0 | 189 | // Return multiple pin values. |
paul@0 | 190 | |
paul@0 | 191 | unsigned |
paul@0 | 192 | Gpio_jz4740_chip::multi_get(unsigned offset) |
paul@0 | 193 | { |
paul@0 | 194 | _reg_offset_check(offset); |
paul@0 | 195 | return _regs[Pin_level]; |
paul@0 | 196 | } |
paul@0 | 197 | |
paul@0 | 198 | // Set the value of a pin. |
paul@0 | 199 | |
paul@0 | 200 | void |
paul@0 | 201 | Gpio_jz4740_chip::set(unsigned pin, int value) |
paul@0 | 202 | { |
paul@0 | 203 | if (pin >= _nr_pins) |
paul@0 | 204 | throw -L4_EINVAL; |
paul@0 | 205 | |
paul@0 | 206 | l4_uint32_t reg_set = value ? Port_data_set : Port_data_clear; |
paul@0 | 207 | _regs[reg_set] = _pin_bit(pin); |
paul@0 | 208 | } |
paul@0 | 209 | |
paul@0 | 210 | // Set multiple pin values. |
paul@0 | 211 | |
paul@0 | 212 | void |
paul@0 | 213 | Gpio_jz4740_chip::multi_set(Pin_slice const &mask, unsigned data) |
paul@0 | 214 | { |
paul@0 | 215 | _reg_offset_check(mask.offset); |
paul@0 | 216 | if (mask.mask & data) |
paul@0 | 217 | _regs[Port_data_set] = (mask.mask & data); |
paul@0 | 218 | if (mask.mask & ~data) |
paul@0 | 219 | _regs[Port_data_clear] = (mask.mask & ~data); |
paul@0 | 220 | } |
paul@0 | 221 | |
paul@0 | 222 | // Set a pin up with the given mode and value (if appropriate). |
paul@0 | 223 | |
paul@0 | 224 | void |
paul@0 | 225 | Gpio_jz4740_chip::setup(unsigned pin, unsigned mode, int value) |
paul@0 | 226 | { |
paul@0 | 227 | if (pin >= _nr_pins) |
paul@0 | 228 | throw -L4_EINVAL; |
paul@0 | 229 | |
paul@0 | 230 | config(pin, mode); |
paul@0 | 231 | |
paul@0 | 232 | if (mode == Output) |
paul@0 | 233 | set(pin, value); |
paul@0 | 234 | } |
paul@0 | 235 | |
paul@0 | 236 | // Configuration of a pin using the generic input/output/IRQ mode. |
paul@0 | 237 | |
paul@0 | 238 | void |
paul@0 | 239 | Gpio_jz4740_chip::config(unsigned pin, unsigned mode) |
paul@0 | 240 | { |
paul@0 | 241 | _config(_pin_bit(pin), mode); |
paul@0 | 242 | } |
paul@0 | 243 | |
paul@0 | 244 | void |
paul@0 | 245 | Gpio_jz4740_chip::_config(unsigned bitmap, unsigned mode) |
paul@0 | 246 | { |
paul@0 | 247 | switch (mode) |
paul@0 | 248 | { |
paul@0 | 249 | case Input: |
paul@0 | 250 | _regs[Port_function_clear] = bitmap; |
paul@0 | 251 | _regs[Port_select_clear] = bitmap; |
paul@0 | 252 | _regs[Port_dir_clear] = bitmap; |
paul@0 | 253 | break; |
paul@0 | 254 | case Output: |
paul@0 | 255 | _regs[Port_function_clear] = bitmap; |
paul@0 | 256 | _regs[Port_select_clear] = bitmap; |
paul@0 | 257 | _regs[Port_dir_set] = bitmap; |
paul@0 | 258 | break; |
paul@0 | 259 | case Irq: |
paul@0 | 260 | _regs[Port_function_clear] = bitmap; |
paul@0 | 261 | _regs[Port_select_set] = bitmap; |
paul@0 | 262 | // The direction depends on the actual trigger mode. |
paul@0 | 263 | break; |
paul@0 | 264 | default: |
paul@0 | 265 | break; |
paul@0 | 266 | } |
paul@0 | 267 | } |
paul@0 | 268 | |
paul@0 | 269 | // Pull-up configuration for a pin. |
paul@0 | 270 | |
paul@0 | 271 | void |
paul@0 | 272 | Gpio_jz4740_chip::config_pull(unsigned pin, unsigned mode) |
paul@0 | 273 | { |
paul@0 | 274 | if (pin >= _nr_pins) |
paul@0 | 275 | throw -L4_EINVAL; |
paul@0 | 276 | |
paul@0 | 277 | _config_pull(_pin_bit(pin), mode); |
paul@0 | 278 | } |
paul@0 | 279 | |
paul@0 | 280 | void |
paul@0 | 281 | Gpio_jz4740_chip::_config_pull(unsigned bitmap, unsigned mode) |
paul@0 | 282 | { |
paul@0 | 283 | switch (mode) |
paul@0 | 284 | { |
paul@0 | 285 | case Pull_none: |
paul@0 | 286 | _regs[Pull_disable_set] = bitmap; |
paul@0 | 287 | break; |
paul@0 | 288 | case Pull_up: |
paul@0 | 289 | _regs[Pull_disable_clear] = bitmap; |
paul@0 | 290 | break; |
paul@0 | 291 | default: |
paul@0 | 292 | // Invalid pull-up/down mode for pin. |
paul@0 | 293 | throw -L4_EINVAL; |
paul@0 | 294 | } |
paul@0 | 295 | } |
paul@0 | 296 | |
paul@0 | 297 | // Pin function configuration. |
paul@0 | 298 | |
paul@0 | 299 | void |
paul@0 | 300 | Gpio_jz4740_chip::config_pad(unsigned pin, unsigned func, unsigned value) |
paul@0 | 301 | { |
paul@0 | 302 | if (pin >= _nr_pins) |
paul@0 | 303 | throw -L4_EINVAL; |
paul@0 | 304 | |
paul@0 | 305 | _config_pad(_pin_bit(pin), func, value); |
paul@0 | 306 | } |
paul@0 | 307 | |
paul@0 | 308 | void |
paul@0 | 309 | Gpio_jz4740_chip::_config_pad(unsigned bitmap, unsigned func, unsigned value) |
paul@0 | 310 | { |
paul@0 | 311 | if (value > 1) |
paul@0 | 312 | throw -L4_EINVAL; |
paul@0 | 313 | |
paul@0 | 314 | switch (func) |
paul@0 | 315 | { |
paul@0 | 316 | case Hw::Gpio_chip::Function_gpio: |
paul@0 | 317 | _regs[Port_function_clear] = bitmap; |
paul@0 | 318 | break; |
paul@0 | 319 | |
paul@0 | 320 | // Support two different device functions. |
paul@0 | 321 | |
paul@0 | 322 | case Hw::Gpio_chip::Function_alt: |
paul@0 | 323 | _regs[Port_function_set] = bitmap; |
paul@0 | 324 | _regs[value ? Port_select_set : Port_select_clear] = bitmap; |
paul@0 | 325 | break; |
paul@0 | 326 | default: |
paul@0 | 327 | throw -L4_EINVAL; |
paul@0 | 328 | } |
paul@0 | 329 | } |
paul@0 | 330 | |
paul@0 | 331 | // Obtain a pin's configuration from a register in the supplied value. |
paul@0 | 332 | |
paul@0 | 333 | void |
paul@0 | 334 | Gpio_jz4740_chip::config_get(unsigned pin, unsigned reg, unsigned *value) |
paul@0 | 335 | { |
paul@0 | 336 | if (pin >= _nr_pins) |
paul@0 | 337 | throw -L4_EINVAL; |
paul@0 | 338 | |
paul@0 | 339 | *value = (_regs[reg] >> _pin_shift(pin)) & 1; |
paul@0 | 340 | } |
paul@0 | 341 | |
paul@188 | 342 | // Return function and function-specific configuration for a pin. |
paul@188 | 343 | |
paul@188 | 344 | void |
paul@188 | 345 | Gpio_jz4740_chip::config_pad_get(unsigned pin, unsigned *func, unsigned *value) |
paul@188 | 346 | { |
paul@188 | 347 | unsigned direction, function, select, trigger; |
paul@188 | 348 | |
paul@188 | 349 | config_get(pin, Port_function, &function); |
paul@188 | 350 | config_get(pin, Port_select, &select); |
paul@188 | 351 | config_get(pin, Port_dir, &direction); |
paul@188 | 352 | |
paul@188 | 353 | if (function) |
paul@188 | 354 | { |
paul@188 | 355 | *func = Hw::Gpio_chip::Function_alt; |
paul@188 | 356 | *value = select; |
paul@188 | 357 | return; |
paul@188 | 358 | } |
paul@188 | 359 | |
paul@188 | 360 | if (select) |
paul@188 | 361 | { |
paul@188 | 362 | config_get(pin, Port_trigger, &trigger); |
paul@188 | 363 | |
paul@188 | 364 | *func = Hw::Gpio_chip::Function_irq; |
paul@188 | 365 | *value = (trigger ? (direction ? L4_IRQ_F_POS_EDGE : L4_IRQ_F_NEG_EDGE) |
paul@188 | 366 | : (direction ? L4_IRQ_F_LEVEL_HIGH : L4_IRQ_F_LEVEL_LOW)); |
paul@188 | 367 | return; |
paul@188 | 368 | } |
paul@188 | 369 | |
paul@188 | 370 | *func = Hw::Gpio_chip::Function_gpio; |
paul@188 | 371 | *value = direction ? Input : Output; |
paul@188 | 372 | } |
paul@188 | 373 | |
paul@0 | 374 | // Obtain an IRQ abstraction for a pin. |
paul@0 | 375 | |
paul@0 | 376 | Hw::Gpio_irq_pin * |
paul@0 | 377 | Gpio_jz4740_chip::get_irq(unsigned pin) |
paul@0 | 378 | { |
paul@0 | 379 | if (pin >= _nr_pins) |
paul@0 | 380 | throw -L4_EINVAL; |
paul@0 | 381 | |
paul@0 | 382 | return new Gpio_jz4740_irq_pin(pin, _regs); |
paul@0 | 383 | } |
paul@0 | 384 | |
paul@0 | 385 | // Pull-up function configuration for multiple pins. |
paul@0 | 386 | |
paul@0 | 387 | void |
paul@0 | 388 | Gpio_jz4740_chip::multi_config_pull(Pin_slice const &mask, unsigned mode) |
paul@0 | 389 | { |
paul@0 | 390 | _config_pull(mask.mask << mask.offset, mode); |
paul@0 | 391 | } |
paul@0 | 392 | |
paul@0 | 393 | // Pin function configuration for multiple pins. |
paul@0 | 394 | |
paul@0 | 395 | void |
paul@0 | 396 | Gpio_jz4740_chip::multi_config_pad(Pin_slice const &mask, unsigned func, unsigned val) |
paul@0 | 397 | { |
paul@0 | 398 | _config_pad(mask.mask << mask.offset, func, val); |
paul@0 | 399 | } |
paul@0 | 400 | |
paul@0 | 401 | // Set up multiple pins with the given mode. |
paul@0 | 402 | |
paul@0 | 403 | void |
paul@0 | 404 | Gpio_jz4740_chip::multi_setup(Pin_slice const &mask, unsigned mode, unsigned outvalues) |
paul@0 | 405 | { |
paul@0 | 406 | _config(mask.mask << mask.offset, mode); |
paul@0 | 407 | |
paul@0 | 408 | if (mode == Output) |
paul@0 | 409 | multi_set(mask, outvalues); |
paul@0 | 410 | } |
paul@0 | 411 | |
paul@0 | 412 | |
paul@0 | 413 | |
paul@0 | 414 | // C language interface functions. |
paul@0 | 415 | |
paul@0 | 416 | void *jz4740_gpio_init(l4_addr_t start, l4_addr_t end, unsigned pins) |
paul@0 | 417 | { |
paul@0 | 418 | return (void *) new Gpio_jz4740_chip(start, end, pins); |
paul@0 | 419 | } |
paul@0 | 420 | |
paul@0 | 421 | void jz4740_gpio_setup(void *gpio, unsigned pin, unsigned mode, int value) |
paul@0 | 422 | { |
paul@0 | 423 | static_cast<Gpio_jz4740_chip *>(gpio)->setup(pin, mode, value); |
paul@0 | 424 | } |
paul@0 | 425 | |
paul@0 | 426 | void jz4740_gpio_config_pull(void *gpio, unsigned pin, unsigned mode) |
paul@0 | 427 | { |
paul@0 | 428 | static_cast<Gpio_jz4740_chip *>(gpio)->config_pull(pin, mode); |
paul@0 | 429 | } |
paul@0 | 430 | |
paul@0 | 431 | void jz4740_gpio_config_pad(void *gpio, unsigned pin, unsigned func, unsigned value) |
paul@0 | 432 | { |
paul@0 | 433 | static_cast<Gpio_jz4740_chip *>(gpio)->config_pad(pin, func, value); |
paul@0 | 434 | } |
paul@0 | 435 | |
paul@0 | 436 | void jz4740_gpio_config_get(void *gpio, unsigned pin, unsigned reg, unsigned *value) |
paul@0 | 437 | { |
paul@0 | 438 | static_cast<Gpio_jz4740_chip *>(gpio)->config_get(pin, reg, value); |
paul@0 | 439 | } |
paul@0 | 440 | |
paul@188 | 441 | void jz4740_gpio_config_pad_get(void *gpio, unsigned pin, unsigned *func, unsigned *value) |
paul@188 | 442 | { |
paul@188 | 443 | static_cast<Gpio_jz4740_chip *>(gpio)->config_pad_get(pin, func, value); |
paul@188 | 444 | } |
paul@188 | 445 | |
paul@0 | 446 | void jz4740_gpio_multi_setup(void *gpio, Pin_slice const *mask, unsigned mode, unsigned outvalues) |
paul@0 | 447 | { |
paul@0 | 448 | static_cast<Gpio_jz4740_chip *>(gpio)->multi_setup(*mask, mode, outvalues); |
paul@0 | 449 | } |
paul@0 | 450 | |
paul@0 | 451 | void jz4740_gpio_multi_config_pull(void *gpio, Pin_slice const *mask, unsigned mode) |
paul@0 | 452 | { |
paul@0 | 453 | static_cast<Gpio_jz4740_chip *>(gpio)->multi_config_pull(*mask, mode); |
paul@0 | 454 | } |
paul@0 | 455 | |
paul@0 | 456 | void jz4740_gpio_multi_config_pad(void *gpio, Pin_slice const *mask, unsigned func, unsigned value) |
paul@0 | 457 | { |
paul@0 | 458 | static_cast<Gpio_jz4740_chip *>(gpio)->multi_config_pad(*mask, func, value); |
paul@0 | 459 | } |
paul@0 | 460 | |
paul@0 | 461 | void jz4740_gpio_multi_set(void *gpio, Pin_slice const *mask, unsigned data) |
paul@0 | 462 | { |
paul@0 | 463 | static_cast<Gpio_jz4740_chip *>(gpio)->multi_set(*mask, data); |
paul@0 | 464 | } |
paul@0 | 465 | |
paul@0 | 466 | unsigned jz4740_gpio_multi_get(void *gpio, unsigned offset) |
paul@0 | 467 | { |
paul@0 | 468 | return static_cast<Gpio_jz4740_chip *>(gpio)->multi_get(offset); |
paul@0 | 469 | } |
paul@0 | 470 | |
paul@0 | 471 | int jz4740_gpio_get(void *gpio, unsigned pin) |
paul@0 | 472 | { |
paul@0 | 473 | return static_cast<Gpio_jz4740_chip *>(gpio)->get(pin); |
paul@0 | 474 | } |
paul@0 | 475 | |
paul@0 | 476 | void jz4740_gpio_set(void *gpio, unsigned pin, int value) |
paul@0 | 477 | { |
paul@0 | 478 | static_cast<Gpio_jz4740_chip *>(gpio)->set(pin, value); |
paul@0 | 479 | } |
paul@0 | 480 | |
paul@0 | 481 | void *jz4740_gpio_get_irq(void *gpio, unsigned pin) |
paul@0 | 482 | { |
paul@0 | 483 | return (void *) static_cast<Gpio_jz4740_chip *>(gpio)->get_irq(pin); |
paul@0 | 484 | } |
paul@0 | 485 | |
paul@0 | 486 | bool jz4740_gpio_irq_set_mode(void *gpio_irq, unsigned mode) |
paul@0 | 487 | { |
paul@0 | 488 | return static_cast<Hw::Gpio_irq_pin *>(gpio_irq)->do_set_mode(mode); |
paul@0 | 489 | } |