1.1 --- a/pkg/devices/lib/hdmi/include/hdmi-jz4780.h Sat May 23 22:34:17 2020 +0200
1.2 +++ b/pkg/devices/lib/hdmi/include/hdmi-jz4780.h Mon Jun 01 15:37:38 2020 +0200
1.3 @@ -3,6 +3,11 @@
1.4 *
1.5 * Copyright (C) 2020 Paul Boddie <paul@boddie.org.uk>
1.6 *
1.7 + * Some structures have been adopted from the Linux DRM bridge driver for
1.8 + * Synopsys DW-HDMI with the following attribution:
1.9 + *
1.10 + * Copyright (C) 2011 Freescale Semiconductor, Inc.
1.11 + *
1.12 * This program is free software; you can redistribute it and/or
1.13 * modify it under the terms of the GNU General Public License as
1.14 * published by the Free Software Foundation; either version 2 of
1.15 @@ -21,11 +26,60 @@
1.16
1.17 #pragma once
1.18
1.19 +#include <l4/devices/lcd-jz4740-panel.h>
1.20 #include <l4/sys/types.h>
1.21 #include <stdint.h>
1.22
1.23
1.24
1.25 +// PHY capability definition type.
1.26 +
1.27 +struct Phy_capabilities
1.28 +{
1.29 + uint8_t type;
1.30 + const char *name;
1.31 + int gen;
1.32 + int svsret;
1.33 + int configure;
1.34 +};
1.35 +
1.36 +
1.37 +
1.38 +// PHY configuration types.
1.39 +
1.40 +enum Phy_resolutions
1.41 +{
1.42 + Phy_resolution_8bpc = 0,
1.43 + Phy_resolution_10bpc = 1,
1.44 + Phy_resolution_12bpc = 2,
1.45 + Phy_resolution_count = 3,
1.46 +};
1.47 +
1.48 +struct Phy_mpll_config
1.49 +{
1.50 + unsigned long pixelclock; // frequency (Hz)
1.51 + struct {
1.52 + uint16_t cpce;
1.53 + uint16_t gmp;
1.54 + } res[Phy_resolution_count];
1.55 +};
1.56 +
1.57 +struct Phy_curr_ctrl
1.58 +{
1.59 + unsigned long pixelclock; // frequency (Hz)
1.60 + uint16_t curr[Phy_resolution_count];
1.61 +};
1.62 +
1.63 +struct Phy_config
1.64 +{
1.65 + unsigned long pixelclock; // frequency (Hz)
1.66 + uint16_t symbol; // clock symbol and transmitter control
1.67 + uint16_t term; // transmission termination value
1.68 + uint16_t vlevel; // voltage level control
1.69 +};
1.70 +
1.71 +
1.72 +
1.73 #ifdef __cplusplus
1.74
1.75 #include <l4/devices/hw_mmio_register_block.h>
1.76 @@ -42,34 +96,101 @@
1.77 // Identification.
1.78
1.79 uint16_t _version;
1.80 + uint8_t _phy_type;
1.81 + const struct Phy_capabilities *_phy_def;
1.82 +
1.83 + // Input/output properties.
1.84 +
1.85 + struct Jz4740_lcd_panel *_panel;
1.86 + unsigned long _pixelclock;
1.87
1.88 // Transfer properties.
1.89
1.90 bool _segment_read;
1.91 - uint8_t _device_register;
1.92 + uint8_t _device_register, _phy_device_register;
1.93 +
1.94 + // Convenience methods for register access.
1.95 +
1.96 + void reg_update(uint32_t reg, uint32_t bits, bool enable);
1.97 + void reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits);
1.98 + void reg_fill_field(uint32_t reg, uint32_t mask);
1.99
1.100 protected:
1.101 + unsigned long get_pixelclock();
1.102 +
1.103 void get_identification();
1.104
1.105 void irq_init();
1.106
1.107 - void i2c_init();
1.108 - long i2c_wait();
1.109 + void i2c_init(uint32_t reset, uint32_t divider, uint32_t config0,
1.110 + uint32_t config1, uint32_t status, uint32_t mask);
1.111
1.112 - void hotplug_init();
1.113 + long i2c_wait(uint32_t status);
1.114 +
1.115 + void phy_irq_init();
1.116
1.117 public:
1.118 - Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq);
1.119 + Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq,
1.120 + struct Jz4740_lcd_panel *panel);
1.121 +
1.122 + // Chipset querying.
1.123
1.124 void get_version(uint8_t *major, uint16_t *minor);
1.125 + void get_phy_capabilities(const struct Phy_capabilities **phy_def);
1.126 +
1.127 + // I2C operations.
1.128
1.129 int i2c_read(uint8_t *buf, unsigned int length);
1.130 +
1.131 void i2c_set_address(uint8_t address);
1.132 void i2c_set_segment(uint8_t segment);
1.133 void i2c_set_register(uint8_t device_register);
1.134
1.135 + int i2c_phy_write(uint8_t address, uint16_t value);
1.136 + int i2c_phy_write(uint16_t *buf, unsigned int length);
1.137 +
1.138 + void i2c_phy_set_address(uint8_t address);
1.139 + void i2c_phy_set_register(uint8_t device_register);
1.140 +
1.141 + // PHY configuration operations.
1.142 +
1.143 + void phy_enable_powerdown(bool enable);
1.144 + void phy_enable_tmds(bool enable);
1.145 + void phy_enable_svsret(bool enable);
1.146 + void phy_enable_gen2_powerdown(bool enable);
1.147 + void phy_enable_gen2_tx_power(bool enable);
1.148 + void phy_enable_interface(bool enable);
1.149 +
1.150 + // PHY operations.
1.151 +
1.152 + long phy_configure();
1.153 + long phy_configure_specific();
1.154 + long phy_init();
1.155 + void phy_power_off();
1.156 + void phy_power_on();
1.157 + void phy_reset();
1.158 +
1.159 + // Hotplug and signalling support.
1.160 +
1.161 bool connected();
1.162 long wait_for_connection();
1.163 + long wait_for_tx_phy_lock(int level);
1.164 + long wait_for_phy_irq(uint32_t int_status_flags, uint32_t status_flags,
1.165 + uint32_t polarity_flags);
1.166 +
1.167 + // Video output initialisation.
1.168 +
1.169 + void enable_overflow_irq(bool enable);
1.170 + void frame_init();
1.171 + void data_path_init();
1.172 + void packet_init();
1.173 + void csc_init();
1.174 + void sample_init();
1.175 + void hdcp_init();
1.176 +
1.177 + // Enable the video output.
1.178 +
1.179 + long enable(unsigned long pixelclock);
1.180 };
1.181
1.182 #endif /* __cplusplus */
1.183 @@ -80,10 +201,13 @@
1.184
1.185 EXTERN_C_BEGIN
1.186
1.187 -void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq);
1.188 +void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq,
1.189 + struct Jz4740_lcd_panel *panel);
1.190
1.191 void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor);
1.192
1.193 +void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def);
1.194 +
1.195 int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length);
1.196
1.197 void jz4780_hdmi_i2c_set_address(void *hdmi, uint8_t address);
1.198 @@ -92,8 +216,16 @@
1.199
1.200 void jz4780_hdmi_i2c_set_register(void *hdmi, uint8_t device_register);
1.201
1.202 +int jz4780_hdmi_phy_i2c_write(void *hdmi, uint16_t *buf, unsigned int length);
1.203 +
1.204 +void jz4780_hdmi_i2c_phy_set_address(void *hdmi, uint8_t address);
1.205 +
1.206 +void jz4780_hdmi_i2c_phy_set_register(void *hdmi, uint8_t device_register);
1.207 +
1.208 int jz4780_hdmi_connected(void *hdmi);
1.209
1.210 long jz4780_hdmi_wait_for_connection(void *hdmi);
1.211
1.212 +long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock);
1.213 +
1.214 EXTERN_C_END