1.1 --- a/pkg/devices/lib/dma/src/x1600.cc Wed Jun 05 13:51:55 2024 +0200
1.2 +++ b/pkg/devices/lib/dma/src/x1600.cc Thu Jun 06 23:57:07 2024 +0200
1.3 @@ -259,7 +259,10 @@
1.4 // Ensure an absence of address error and halt conditions globally and in this channel.
1.5
1.6 if (error() || halted())
1.7 - return 0;
1.8 + {
1.9 + printf("Cleared:%s%s\n", error() ? " error" : "", halted() ? " halted" : "");
1.10 + clear_errors();
1.11 + }
1.12
1.13 // Ensure a zero transfer count for this channel.
1.14
1.15 @@ -336,7 +339,8 @@
1.16
1.17 // Enable the channel with descriptor transfer configured if appropriate.
1.18
1.19 - _regs[Dma_control_status] = Dma_no_descriptor_transfer |
1.20 + _regs[Dma_control_status] = (desc_vaddr ? Dma_8word_descriptor :
1.21 + Dma_no_descriptor_transfer) |
1.22 Dma_channel_enable;
1.23
1.24 // Return the number of units to transfer.
1.25 @@ -409,6 +413,15 @@
1.26 _chip->ack_irq(_channel);
1.27 }
1.28
1.29 +// Clear error conditions.
1.30 +
1.31 +void
1.32 +Dma_x1600_channel::clear_errors()
1.33 +{
1.34 + _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_address_error | Dma_trans_halted);
1.35 + _chip->clear_errors();
1.36 +}
1.37 +
1.38 // Return whether a transfer has completed.
1.39
1.40 bool
1.41 @@ -492,6 +505,14 @@
1.42 _regs[Dma_irq_pending] = _regs[Dma_irq_pending] & ~(1UL << channel);
1.43 }
1.44
1.45 +// Clear error conditions.
1.46 +
1.47 +void
1.48 +Dma_x1600_chip::clear_errors()
1.49 +{
1.50 + _regs[Dma_control] = _regs[Dma_control] & ~(Dma_control_address_error | Dma_control_trans_halted);
1.51 +}
1.52 +
1.53 // Return whether an address error condition has arisen.
1.54
1.55 bool