1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Sat Sep 16 16:53:06 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Sat Sep 16 17:56:49 2023 +0200
1.3 @@ -256,37 +256,37 @@
1.4 Clock_gate_can0,
1.5 Clock_change_enable_can0,
1.6 Clock_busy_can0,
1.7 - Clock_divider_can0);
1.8 + Divider(Clock_divider_can0));
1.9
1.10 Clock clock_can1(Source(mux_bus, Clock_source_can1),
1.11 Clock_gate_can1,
1.12 Clock_change_enable_can1,
1.13 Clock_busy_can1,
1.14 - Clock_divider_can1);
1.15 + Divider(Clock_divider_can1));
1.16
1.17 Clock clock_cdbus(Source(mux_dev, Clock_source_cdbus),
1.18 Clock_gate_cdbus,
1.19 Clock_change_enable_cdbus,
1.20 Clock_busy_cdbus,
1.21 - Clock_divider_cdbus);
1.22 + Divider(Clock_divider_cdbus));
1.23
1.24 Clock clock_cim(Source(mux_dev, Clock_source_cim),
1.25 Clock_gate_cim,
1.26 Clock_change_enable_cim,
1.27 Clock_busy_cim,
1.28 - Clock_divider_cim);
1.29 + Divider(Clock_divider_cim));
1.30
1.31 Clock clock_cpu(Source(mux_core, Clock_source_cpu),
1.32 Field::undefined,
1.33 Clock_change_enable_cpu,
1.34 Clock_busy_cpu,
1.35 - Clock_divider_cpu);
1.36 + Divider(Clock_divider_cpu));
1.37
1.38 Clock clock_ddr(Source(mux_core, Clock_source_ddr),
1.39 Clock_gate_ddr,
1.40 Clock_change_enable_ddr,
1.41 Clock_busy_ddr,
1.42 - Clock_divider_ddr);
1.43 + Divider(Clock_divider_ddr));
1.44
1.45 Clock clock_dma(Source(mux_pclock), Clock_gate_dma);
1.46
1.47 @@ -298,13 +298,13 @@
1.48 Clock_gate_ahb0,
1.49 Clock_change_enable_ahb0,
1.50 Field::undefined,
1.51 - Clock_divider_hclock0);
1.52 + Divider(Clock_divider_hclock0));
1.53
1.54 Clock clock_hclock2(Source(mux_ahb2_apb),
1.55 Clock_gate_apb0,
1.56 Clock_change_enable_ahb2,
1.57 Field::undefined,
1.58 - Clock_divider_hclock2);
1.59 + Divider(Clock_divider_hclock2));
1.60
1.61 Clock clock_hdmi;
1.62
1.63 @@ -332,13 +332,13 @@
1.64 Clock_gate_lcd_pixel,
1.65 Clock_change_enable_lcd,
1.66 Clock_busy_lcd,
1.67 - Clock_divider_lcd);
1.68 + Divider(Clock_divider_lcd));
1.69
1.70 Clock clock_mac(Source(mux_dev, Clock_source_mac),
1.71 Clock_gate_gmac0,
1.72 Clock_change_enable_mac,
1.73 Clock_busy_mac,
1.74 - Clock_divider_mac);
1.75 + Divider(Clock_divider_mac));
1.76
1.77 Clock clock_main(Source(mux_core, Clock_source_main),
1.78 Clock_gate_main);
1.79 @@ -347,19 +347,19 @@
1.80 Clock_gate_msc0,
1.81 Clock_change_enable_msc0,
1.82 Clock_busy_msc0,
1.83 - Clock_divider_msc0);
1.84 + Divider(Clock_divider_msc0));
1.85
1.86 Clock clock_msc0(Source(mux_dev, Clock_source_msc0),
1.87 Clock_gate_msc0,
1.88 Clock_change_enable_msc0,
1.89 Clock_busy_msc0,
1.90 - Clock_divider_msc0);
1.91 + Divider(Clock_divider_msc0));
1.92
1.93 Clock clock_msc1(Source(mux_dev, Clock_source_msc1),
1.94 Clock_gate_msc1,
1.95 Clock_change_enable_msc1,
1.96 Clock_busy_msc1,
1.97 - Clock_divider_msc1);
1.98 + Divider(Clock_divider_msc1));
1.99
1.100 Clock clock_none;
1.101
1.102 @@ -367,34 +367,34 @@
1.103 Clock_gate_apb0,
1.104 Field::undefined,
1.105 Field::undefined,
1.106 - Clock_divider_pclock);
1.107 + Divider(Clock_divider_pclock));
1.108
1.109 Pll clock_pll_A(Source(mux_external),
1.110 Pll_enable_A, Pll_stable_A, Pll_bypass_A,
1.111 - Pll_multiplier_A, Pll_input_division_A,
1.112 - Pll_output_division0_A, Pll_output_division1_A);
1.113 + Divider_pll(Pll_multiplier_A, Pll_input_division_A,
1.114 + Pll_output_division0_A, Pll_output_division1_A));
1.115
1.116 Pll clock_pll_E(Source(mux_external),
1.117 Pll_enable_E, Pll_stable_E, Pll_bypass_E,
1.118 - Pll_multiplier_E, Pll_input_division_E,
1.119 - Pll_output_division0_E, Pll_output_division1_E);
1.120 + Divider_pll(Pll_multiplier_E, Pll_input_division_E,
1.121 + Pll_output_division0_E, Pll_output_division1_E));
1.122
1.123 Pll clock_pll_M(Source(mux_external),
1.124 Pll_enable_M, Pll_stable_M, Pll_bypass_M,
1.125 - Pll_multiplier_M, Pll_input_division_M,
1.126 - Pll_output_division0_M, Pll_output_division1_M);
1.127 + Divider_pll(Pll_multiplier_M, Pll_input_division_M,
1.128 + Pll_output_division0_M, Pll_output_division1_M));
1.129
1.130 Clock clock_pwm(Source(mux_dev, Clock_source_pwm),
1.131 Clock_gate_pwm,
1.132 Clock_change_enable_pwm,
1.133 Clock_busy_pwm,
1.134 - Clock_divider_pwm);
1.135 + Divider(Clock_divider_pwm));
1.136
1.137 Clock clock_pwm0(Source(mux_dev, Clock_source_pwm),
1.138 Clock_gate_pwm,
1.139 Clock_change_enable_pwm,
1.140 Clock_busy_pwm,
1.141 - Clock_divider_pwm);
1.142 + Divider(Clock_divider_pwm));
1.143
1.144 Clock clock_pwm1;
1.145
1.146 @@ -404,7 +404,7 @@
1.147 Clock_gate_sfc,
1.148 Clock_change_enable_sfc,
1.149 Clock_busy_sfc,
1.150 - Clock_divider_sfc);
1.151 + Divider(Clock_divider_sfc));
1.152
1.153 Clock clock_smb0;
1.154
1.155 @@ -420,7 +420,7 @@
1.156 Clock_gate_ssi0,
1.157 Clock_change_enable_ssi,
1.158 Clock_busy_ssi,
1.159 - Clock_divider_ssi);
1.160 + Divider(Clock_divider_ssi));
1.161
1.162 Clock clock_timer(Source(mux_pclock), Clock_gate_timer);
1.163