1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Thu Sep 14 00:13:02 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Thu Sep 14 01:09:02 2023 +0200
1.3 @@ -316,260 +316,292 @@
1.4 uint32_t divider_mask;
1.5 int num_inputs;
1.6 enum Clock_input_identifiers inputs[4];
1.7 + enum Clock_identifiers clock_input;
1.8 };
1.9
1.10 -#define Clock_undefined {Reg_undefined, Clock_source_undefined, \
1.11 - Reg_undefined, Clock_gate_undefined, \
1.12 - Reg_undefined, Clock_change_enable_undefined, \
1.13 - Reg_undefined, Clock_busy_undefined, \
1.14 - Reg_undefined, Clock_divider_undefined, 0, \
1.15 - 0, {}}
1.16 +#define Clock_desc_undefined {Reg_undefined, Clock_source_undefined, \
1.17 + Reg_undefined, Clock_gate_undefined, \
1.18 + Reg_undefined, Clock_change_enable_undefined, \
1.19 + Reg_undefined, Clock_busy_undefined, \
1.20 + Reg_undefined, Clock_divider_undefined, 0, \
1.21 + 0, {}, \
1.22 + Clock_undefined}
1.23
1.24 static struct Clock_desc clock_desc[Clock_identifier_count] = {
1.25
1.26 - /* Clock_aic_bitclk */ Clock_undefined,
1.27 + /* Clock_aic_bitclk */ Clock_desc_undefined,
1.28
1.29 - /* Clock_aic_pclk */ Clock_undefined,
1.30 + /* Clock_aic_pclk */ Clock_desc_undefined,
1.31
1.32 /* Clock_can0 */ {Can_divider0, Clock_source_can0,
1.33 Clock_gate1, Clock_gate_can0,
1.34 Can_divider0, Clock_change_enable_can0,
1.35 Can_divider0, Clock_busy_can0,
1.36 Can_divider0, Clock_divider_can0, 0xff,
1.37 - 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external}},
1.38 + 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external},
1.39 + Clock_undefined},
1.40
1.41 /* Clock_can1 */ {Can_divider1, Clock_source_can1,
1.42 Clock_gate1, Clock_gate_can1,
1.43 Can_divider1, Clock_change_enable_can1,
1.44 Can_divider1, Clock_busy_can1,
1.45 Can_divider1, Clock_divider_can1, 0xff,
1.46 - 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external}},
1.47 + 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external},
1.48 + Clock_undefined},
1.49
1.50 /* Clock_cdbus */ {Cdbus_divider, Clock_source_cdbus,
1.51 Clock_gate1, Clock_gate_cdbus,
1.52 Cdbus_divider, Clock_change_enable_cdbus,
1.53 Cdbus_divider, Clock_busy_cdbus,
1.54 Cdbus_divider, Clock_divider_cdbus, 0xff,
1.55 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.56 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.57 + Clock_undefined},
1.58
1.59 /* Clock_cim */ {Cim_divider, Clock_source_cim,
1.60 Clock_gate0, Clock_gate_cim,
1.61 Cim_divider, Clock_change_enable_cim,
1.62 Cim_divider, Clock_busy_cim,
1.63 Cim_divider, Clock_divider_cim, 0xff,
1.64 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.65 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.66 + Clock_undefined},
1.67
1.68 /* Clock_cpu */ {Clock_control, Clock_source_cpu,
1.69 Reg_undefined, Clock_gate_undefined,
1.70 Clock_control, Clock_change_enable_cpu,
1.71 Clock_status, Clock_busy_cpu,
1.72 Clock_control, Clock_divider_cpu, 0x0f,
1.73 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M}},
1.74 + 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M},
1.75 + Clock_undefined},
1.76
1.77 /* Clock_ddr */ {Ddr_divider, Clock_source_ddr,
1.78 Clock_gate0, Clock_gate_ddr,
1.79 Ddr_divider, Clock_change_enable_ddr,
1.80 Ddr_divider, Clock_busy_ddr,
1.81 Ddr_divider, Clock_divider_ddr, 0x0f,
1.82 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M}},
1.83 + 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M},
1.84 + Clock_undefined},
1.85
1.86 /* Clock_dma */ {Reg_undefined, Clock_source_undefined,
1.87 Clock_gate0, Clock_gate_dma,
1.88 Reg_undefined, Clock_change_enable_undefined,
1.89 Reg_undefined, Clock_busy_undefined,
1.90 Reg_undefined, Clock_divider_undefined, 0,
1.91 - 1, {Clock_input_ahb2_apb}},
1.92 + 0, {},
1.93 + Clock_pclock},
1.94
1.95 - /* Clock_emac */ Clock_undefined,
1.96 + /* Clock_emac */ Clock_desc_undefined,
1.97
1.98 /* Clock_hclock0 */ {Clock_control, Clock_source_hclock0,
1.99 Clock_gate0, Clock_gate_ahb0,
1.100 Clock_control, Clock_change_enable_ahb0,
1.101 Reg_undefined, Clock_busy_undefined,
1.102 Clock_control, Clock_divider_hclock0, 0x0f,
1.103 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M}},
1.104 + 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M},
1.105 + Clock_undefined},
1.106
1.107 /* Clock_hclock2 */ {Reg_undefined, Clock_source_undefined,
1.108 Clock_gate0, Clock_gate_apb0,
1.109 Clock_control, Clock_change_enable_ahb2,
1.110 Reg_undefined, Clock_busy_undefined,
1.111 Clock_control, Clock_divider_hclock2, 0x0f,
1.112 - 1, {Clock_input_ahb2_apb}},
1.113 + 1, {Clock_input_ahb2_apb},
1.114 + Clock_undefined},
1.115
1.116 - /* Clock_hdmi */ Clock_undefined,
1.117 + /* Clock_hdmi */ Clock_desc_undefined,
1.118
1.119 /* Clock_i2c */ {Reg_undefined, Clock_source_undefined,
1.120 Clock_gate0, Clock_gate_i2c0,
1.121 Reg_undefined, Clock_change_enable_undefined,
1.122 Reg_undefined, Clock_busy_undefined,
1.123 Reg_undefined, Clock_divider_undefined, 0,
1.124 - 1, {Clock_input_ahb2_apb}},
1.125 + 0, {},
1.126 + Clock_pclock},
1.127
1.128 /* Clock_i2c0 */ {Reg_undefined, Clock_source_undefined,
1.129 Clock_gate0, Clock_gate_i2c0,
1.130 Reg_undefined, Clock_change_enable_undefined,
1.131 Reg_undefined, Clock_busy_undefined,
1.132 Reg_undefined, Clock_divider_undefined, 0,
1.133 - 1, {Clock_input_ahb2_apb}},
1.134 + 0, {},
1.135 + Clock_pclock},
1.136
1.137 /* Clock_i2c1 */ {Reg_undefined, Clock_source_undefined,
1.138 Clock_gate0, Clock_gate_i2c1,
1.139 Reg_undefined, Clock_change_enable_undefined,
1.140 Reg_undefined, Clock_busy_undefined,
1.141 Reg_undefined, Clock_divider_undefined, 0,
1.142 - 1, {Clock_input_ahb2_apb}},
1.143 + 0, {},
1.144 + Clock_pclock},
1.145
1.146 - /* Clock_i2s */ Clock_undefined,
1.147 + /* Clock_i2s */ Clock_desc_undefined,
1.148
1.149 /* Clock_i2s0_rx */ {I2s_divider0, Clock_source_i2s,
1.150 Clock_gate1, Clock_gate_i2s0_rx,
1.151 I2s_divider0, Clock_change_enable_i2s,
1.152 Reg_undefined, Clock_busy_undefined,
1.153 Reg_undefined, Clock_divider_undefined, 0, // NOTE: To define.
1.154 - 2, {Clock_input_main, Clock_input_pll_E}},
1.155 + 2, {Clock_input_main, Clock_input_pll_E},
1.156 + Clock_undefined},
1.157
1.158 /* Clock_i2s0_tx */ {I2s_divider0, Clock_source_i2s,
1.159 Clock_gate1, Clock_gate_i2s0_tx,
1.160 I2s_divider0, Clock_change_enable_i2s,
1.161 Reg_undefined, Clock_busy_undefined,
1.162 Reg_undefined, Clock_divider_undefined, 0, // NOTE: To define.
1.163 - 2, {Clock_input_main, Clock_input_pll_E}},
1.164 + 2, {Clock_input_main, Clock_input_pll_E},
1.165 + Clock_undefined},
1.166
1.167 - /* Clock_kbc */ Clock_undefined,
1.168 + /* Clock_kbc */ Clock_desc_undefined,
1.169
1.170 - /* Clock_lcd */ Clock_undefined,
1.171 + /* Clock_lcd */ Clock_desc_undefined,
1.172
1.173 /* Clock_lcd_pixel */ {Lcd_divider, Clock_source_lcd,
1.174 Clock_gate0, Clock_gate_lcd_pixel,
1.175 Lcd_divider, Clock_change_enable_lcd,
1.176 Lcd_divider, Clock_busy_lcd,
1.177 Lcd_divider, Clock_divider_lcd, 0xff,
1.178 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.179 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.180 + Clock_undefined},
1.181
1.182 /* Clock_mac */ {Mac_divider, Clock_source_mac,
1.183 Clock_gate1, Clock_gate_gmac0,
1.184 Mac_divider, Clock_change_enable_mac,
1.185 Mac_divider, Clock_busy_mac,
1.186 Mac_divider, Clock_divider_mac, 0xff,
1.187 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.188 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.189 + Clock_undefined},
1.190
1.191 /* Clock_main */ {Reg_undefined, Clock_source_undefined,
1.192 Clock_control, Clock_gate_main,
1.193 Reg_undefined, Clock_change_enable_undefined,
1.194 Reg_undefined, Clock_busy_undefined,
1.195 Reg_undefined, Clock_divider_undefined, 0,
1.196 - 1, {Clock_input_main}},
1.197 + 1, {Clock_input_main},
1.198 + Clock_undefined},
1.199
1.200 /* Clock_msc */ {Msc_divider0, Clock_source_msc0,
1.201 Clock_gate0, Clock_gate_msc0,
1.202 Msc_divider0, Clock_change_enable_msc0,
1.203 Msc_divider0, Clock_busy_msc0,
1.204 Msc_divider0, Clock_divider_msc0, 0xff,
1.205 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.206 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.207 + Clock_undefined},
1.208
1.209 /* Clock_msc0 */ {Msc_divider0, Clock_source_msc0,
1.210 Clock_gate0, Clock_gate_msc0,
1.211 Msc_divider0, Clock_change_enable_msc0,
1.212 Msc_divider0, Clock_busy_msc0,
1.213 Msc_divider0, Clock_divider_msc0, 0xff,
1.214 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.215 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.216 + Clock_undefined},
1.217
1.218 /* Clock_msc1 */ {Msc_divider1, Clock_source_msc1,
1.219 Clock_gate0, Clock_gate_msc1,
1.220 Msc_divider1, Clock_change_enable_msc1,
1.221 Msc_divider1, Clock_busy_msc1,
1.222 Msc_divider1, Clock_divider_msc1, 0xff,
1.223 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.224 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.225 + Clock_undefined},
1.226
1.227 /* Clock_pclock */ {Reg_undefined, Clock_source_undefined,
1.228 Clock_gate0, Clock_gate_apb0,
1.229 Reg_undefined, Clock_change_enable_undefined,
1.230 Reg_undefined, Clock_busy_undefined,
1.231 Clock_control, Clock_divider_pclock, 0x0f,
1.232 - 1, {Clock_input_ahb2_apb}},
1.233 + 1, {Clock_input_ahb2_apb},
1.234 + Clock_undefined},
1.235
1.236 /* Clock_pwm */ {Pwm_divider, Clock_source_pwm,
1.237 Clock_gate1, Clock_gate_pwm,
1.238 Pwm_divider, Clock_change_enable_pwm,
1.239 Pwm_divider, Clock_busy_pwm,
1.240 Pwm_divider, Clock_divider_pwm, 0x0f,
1.241 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.242 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.243 + Clock_undefined},
1.244
1.245 /* Clock_pwm0 */ {Pwm_divider, Clock_source_pwm,
1.246 Clock_gate1, Clock_gate_pwm,
1.247 Pwm_divider, Clock_change_enable_pwm,
1.248 Pwm_divider, Clock_busy_pwm,
1.249 Pwm_divider, Clock_divider_pwm, 0x0f,
1.250 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.251 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.252 + Clock_undefined},
1.253
1.254 - /* Clock_pwm1 */ Clock_undefined,
1.255 + /* Clock_pwm1 */ Clock_desc_undefined,
1.256
1.257 - /* Clock_scc */ Clock_undefined,
1.258 + /* Clock_scc */ Clock_desc_undefined,
1.259
1.260 /* Clock_sfc */ {Sfc_divider, Clock_source_sfc,
1.261 Clock_gate0, Clock_gate_sfc,
1.262 Sfc_divider, Clock_change_enable_sfc,
1.263 Sfc_divider, Clock_busy_sfc,
1.264 Sfc_divider, Clock_divider_sfc, 0xff,
1.265 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.266 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.267 + Clock_undefined},
1.268
1.269 - /* Clock_smb0 */ Clock_undefined,
1.270 -
1.271 - /* Clock_smb1 */ Clock_undefined,
1.272 + /* Clock_smb0 */ Clock_desc_undefined,
1.273
1.274 - /* Clock_smb2 */ Clock_undefined,
1.275 + /* Clock_smb1 */ Clock_desc_undefined,
1.276 +
1.277 + /* Clock_smb2 */ Clock_desc_undefined,
1.278
1.279 - /* Clock_smb3 */ Clock_undefined,
1.280 + /* Clock_smb3 */ Clock_desc_undefined,
1.281
1.282 - /* Clock_smb4 */ Clock_undefined,
1.283 + /* Clock_smb4 */ Clock_desc_undefined,
1.284
1.285 /* Clock_ssi */ {Ssi_divider, Clock_source_ssi,
1.286 Clock_gate0, Clock_gate_ssi0,
1.287 Ssi_divider, Clock_change_enable_ssi,
1.288 Ssi_divider, Clock_busy_ssi,
1.289 Ssi_divider, Clock_divider_ssi, 0xff,
1.290 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E}},
1.291 + 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
1.292 + Clock_undefined},
1.293
1.294 /* Clock_timer */ {Reg_undefined, Clock_source_undefined,
1.295 Clock_gate0, Clock_gate_timer,
1.296 Reg_undefined, Clock_change_enable_undefined,
1.297 Reg_undefined, Clock_busy_undefined,
1.298 Reg_undefined, Clock_divider_undefined, 0,
1.299 - 1, {Clock_input_ahb2_apb}},
1.300 + 0, {},
1.301 + Clock_pclock},
1.302
1.303 /* Clock_uart0 */ {Reg_undefined, Clock_source_undefined,
1.304 Clock_gate0, Clock_gate_uart0,
1.305 Reg_undefined, Clock_change_enable_undefined,
1.306 Reg_undefined, Clock_busy_undefined,
1.307 Reg_undefined, Clock_divider_undefined, 0,
1.308 - 1, {Clock_input_ahb2_apb}},
1.309 + 0, {},
1.310 + Clock_pclock},
1.311
1.312 /* Clock_uart1 */ {Reg_undefined, Clock_source_undefined,
1.313 Clock_gate0, Clock_gate_uart1,
1.314 Reg_undefined, Clock_change_enable_undefined,
1.315 Reg_undefined, Clock_busy_undefined,
1.316 Reg_undefined, Clock_divider_undefined, 0,
1.317 - 1, {Clock_input_ahb2_apb}},
1.318 + 0, {},
1.319 + Clock_pclock},
1.320
1.321 /* Clock_uart2 */ {Reg_undefined, Clock_source_undefined,
1.322 Clock_gate0, Clock_gate_uart2,
1.323 Reg_undefined, Clock_change_enable_undefined,
1.324 Reg_undefined, Clock_busy_undefined,
1.325 Reg_undefined, Clock_divider_undefined, 0,
1.326 - 1, {Clock_input_ahb2_apb}},
1.327 + 0, {},
1.328 + Clock_pclock},
1.329
1.330 /* Clock_uart3 */ {Reg_undefined, Clock_source_undefined,
1.331 Clock_gate1, Clock_gate_uart3,
1.332 Reg_undefined, Clock_change_enable_undefined,
1.333 Reg_undefined, Clock_busy_undefined,
1.334 Reg_undefined, Clock_divider_undefined, 0,
1.335 - 1, {Clock_input_ahb2_apb}},
1.336 -
1.337 - /* Clock_udc */ Clock_undefined,
1.338 + 0, {},
1.339 + Clock_pclock},
1.340
1.341 - /* Clock_uhc */ Clock_undefined,
1.342 + /* Clock_udc */ Clock_desc_undefined,
1.343
1.344 - /* Clock_uprt */ Clock_undefined,
1.345 + /* Clock_uhc */ Clock_desc_undefined,
1.346 +
1.347 + /* Clock_uprt */ Clock_desc_undefined,
1.348 };
1.349
1.350
1.351 @@ -905,10 +937,18 @@
1.352 {
1.353 struct Clock_desc desc = clock_desc[clock];
1.354
1.355 - // Undefined clocks return zero.
1.356 + if (desc.num_inputs == 0)
1.357 + {
1.358 + // Clocks may reference other clocks.
1.359
1.360 - if (desc.num_inputs == 0)
1.361 - return 0;
1.362 + if (desc.clock_input != Clock_undefined)
1.363 + return get_frequency(desc.clock_input);
1.364 +
1.365 + // Undefined clocks return zero.
1.366 +
1.367 + else
1.368 + return 0;
1.369 + }
1.370
1.371 // Clocks with one source yield that input frequency.
1.372