1.1 --- a/pkg/landfall-examples/hw_info/jz4780.c Thu Nov 16 17:48:32 2023 +0100
1.2 +++ b/pkg/landfall-examples/hw_info/jz4780.c Thu Nov 16 22:03:51 2023 +0100
1.3 @@ -352,6 +352,16 @@
1.4 x1600_rtc_enable(rtc);
1.5 }
1.6
1.7 +void rtc_alarm_disable(void *rtc)
1.8 +{
1.9 + x1600_rtc_alarm_disable(rtc);
1.10 +}
1.11 +
1.12 +void rtc_alarm_enable(void *rtc)
1.13 +{
1.14 + x1600_rtc_alarm_enable(rtc);
1.15 +}
1.16 +
1.17 uint32_t rtc_get_seconds(void *rtc)
1.18 {
1.19 return x1600_rtc_get_seconds(rtc);
1.20 @@ -476,45 +486,48 @@
1.21 /* CPM definitions. */
1.22
1.23 struct clock_info clocks[] = {
1.24 - {"ext", Clock_external, "External"},
1.25 - {"plla", Clock_pll_A, "PLL A"},
1.26 - {"plle", Clock_pll_E, "PLL E"},
1.27 - {"pllm", Clock_pll_M, "PLL M"},
1.28 - {"pllv", Clock_pll_V, "PLL V"},
1.29 - {"main", Clock_main, "Main"},
1.30 - {"cpu", Clock_cpu, "CPU"},
1.31 - {"h2p", Clock_hclock2_pclock, "AHB2/APB"},
1.32 - {"ahb0", Clock_hclock0, "AHB0"},
1.33 - {"ahb2", Clock_hclock2, "AHB2"},
1.34 - {"apb", Clock_pclock, "APB"},
1.35 - {"dma", Clock_dma, "DMA"},
1.36 - {"hdmi", Clock_lcd, "HDMI"},
1.37 - {"lcd", Clock_lcd, "LCD"},
1.38 - {"lcd0", Clock_lcd_pixel0, "LCD0 pixel"},
1.39 - {"lcd1", Clock_lcd_pixel1, "LCD1 pixel"},
1.40 - {"msc", Clock_msc, "MSC"},
1.41 - {"msc0", Clock_msc0, "MSC0"},
1.42 - {"msc1", Clock_msc1, "MSC1"},
1.43 - {"msc2", Clock_msc1, "MSC2"},
1.44 - {"otg0", Clock_otg0, "USB OTG0"},
1.45 - {"otg1", Clock_otg1, "USB OTG1"},
1.46 - {"i2c0", Clock_i2c0, "I2C0"},
1.47 - {"i2c1", Clock_i2c1, "I2C1"},
1.48 - {"i2c2", Clock_i2c2, "I2C2"},
1.49 - {"i2c3", Clock_i2c3, "I2C3"},
1.50 - {"i2c4", Clock_i2c4, "I2C4"},
1.51 - {"i2s0", Clock_i2s0, "I2S0"},
1.52 - {"i2s1", Clock_i2s1, "I2S1"},
1.53 - {"pcm", Clock_pcm, "PCM"},
1.54 - {"ssi", Clock_ssi, "SSI"},
1.55 - {"ssi0", Clock_ssi0, "SSI0"},
1.56 - {"ssi1", Clock_ssi1, "SSI1"},
1.57 - {"uart0", Clock_uart0, "UART0"},
1.58 - {"uart1", Clock_uart1, "UART1"},
1.59 - {"uart2", Clock_uart2, "UART2"},
1.60 - {"uart3", Clock_uart3, "UART3"},
1.61 - {"uart4", Clock_uart4, "UART4"},
1.62 - {NULL, Clock_undefined, NULL},
1.63 + {"ext", Clock_external, "EXCLK"},
1.64 + {"ext_512", Clock_external_div_512, "EXCLK/512"},
1.65 + {"rtc_ext", Clock_rtc_external, "RTCLK"},
1.66 + {"plla", Clock_pll_A, "PLL A"},
1.67 + {"plle", Clock_pll_E, "PLL E"},
1.68 + {"pllm", Clock_pll_M, "PLL M"},
1.69 + {"pllv", Clock_pll_V, "PLL V"},
1.70 + {"main", Clock_main, "Main (SCLK_A)"},
1.71 + {"cpu", Clock_cpu, "CPU"},
1.72 + {"h2p", Clock_hclock2_pclock, "AHB2/APB"},
1.73 + {"ahb0", Clock_hclock0, "AHB0"},
1.74 + {"ahb2", Clock_hclock2, "AHB2"},
1.75 + {"apb", Clock_pclock, "APB"},
1.76 + {"dma", Clock_dma, "DMA"},
1.77 + {"hdmi", Clock_lcd, "HDMI"},
1.78 + {"lcd", Clock_lcd, "LCD"},
1.79 + {"lcd0", Clock_lcd_pixel0, "LCD0 pixel"},
1.80 + {"lcd1", Clock_lcd_pixel1, "LCD1 pixel"},
1.81 + {"msc", Clock_msc, "MSC"},
1.82 + {"msc0", Clock_msc0, "MSC0"},
1.83 + {"msc1", Clock_msc1, "MSC1"},
1.84 + {"msc2", Clock_msc1, "MSC2"},
1.85 + {"otg0", Clock_otg0, "USB OTG0"},
1.86 + {"otg1", Clock_otg1, "USB OTG1"},
1.87 + {"i2c0", Clock_i2c0, "I2C0"},
1.88 + {"i2c1", Clock_i2c1, "I2C1"},
1.89 + {"i2c2", Clock_i2c2, "I2C2"},
1.90 + {"i2c3", Clock_i2c3, "I2C3"},
1.91 + {"i2c4", Clock_i2c4, "I2C4"},
1.92 + {"i2s0", Clock_i2s0, "I2S0"},
1.93 + {"i2s1", Clock_i2s1, "I2S1"},
1.94 + {"pcm", Clock_pcm, "PCM"},
1.95 + {"rtc", Clock_rtc, "RTC"},
1.96 + {"ssi", Clock_ssi, "SSI"},
1.97 + {"ssi0", Clock_ssi0, "SSI0"},
1.98 + {"ssi1", Clock_ssi1, "SSI1"},
1.99 + {"uart0", Clock_uart0, "UART0"},
1.100 + {"uart1", Clock_uart1, "UART1"},
1.101 + {"uart2", Clock_uart2, "UART2"},
1.102 + {"uart3", Clock_uart3, "UART3"},
1.103 + {"uart4", Clock_uart4, "UART4"},
1.104 + {NULL, Clock_undefined, NULL},
1.105 };
1.106
1.107