1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/pkg/devices/lib/dma/include/dma-x1600.h Tue Oct 24 17:32:54 2023 +0200
1.3 @@ -0,0 +1,180 @@
1.4 +/*
1.5 + * DMA support for the X1600.
1.6 + *
1.7 + * Copyright (C) 2021, 2023 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software; you can redistribute it and/or
1.10 + * modify it under the terms of the GNU General Public License as
1.11 + * published by the Free Software Foundation; either version 2 of
1.12 + * the License, or (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program; if not, write to the Free Software
1.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.22 + * Boston, MA 02110-1301, USA
1.23 + */
1.24 +
1.25 +#pragma once
1.26 +
1.27 +#include <l4/sys/types.h>
1.28 +#include <stdint.h>
1.29 +
1.30 +
1.31 +
1.32 +/* Enumerated types for various transfer parameters. */
1.33 +
1.34 +enum Dma_x1600_request_type
1.35 +{
1.36 + Dma_request_auto = 8,
1.37 + Dma_request_can0_out = 10,
1.38 + Dma_request_can0_in = 11,
1.39 + Dma_request_can1_out = 10,
1.40 + Dma_request_can1_in = 11,
1.41 + Dma_request_uart3_out = 14,
1.42 + Dma_request_uart3_in = 15,
1.43 + Dma_request_uart2_out = 16,
1.44 + Dma_request_uart2_in = 17,
1.45 + Dma_request_uart1_out = 18,
1.46 + Dma_request_uart1_in = 19,
1.47 + Dma_request_uart0_out = 20,
1.48 + Dma_request_uart0_in = 21,
1.49 + Dma_request_ssi0_send_empty = 22,
1.50 + Dma_request_ssi0_recv_full = 23,
1.51 + Dma_request_i2c0_send_empty = 36,
1.52 + Dma_request_i2c0_recv_full = 37,
1.53 + Dma_request_i2c1_send_empty = 38,
1.54 + Dma_request_i2c1_recv_full = 39,
1.55 + Dma_request_ssi_slv_out = 42,
1.56 + Dma_request_ssi_slv_in = 43,
1.57 + Dma_request_msc0_send_empty = 52,
1.58 + Dma_request_msc0_recv_full = 53,
1.59 + Dma_request_msc1_send_empty = 54,
1.60 + Dma_request_msc1_recv_full = 55,
1.61 + Dma_request_sadc_in = 56,
1.62 + Dma_request_aic_loop_out = 61,
1.63 + Dma_request_aic_out = 62,
1.64 + Dma_request_aic_in = 63,
1.65 +};
1.66 +
1.67 +
1.68 +
1.69 +#ifdef __cplusplus
1.70 +
1.71 +#include <l4/devices/cpm-x1600.h>
1.72 +#include <l4/devices/hw_mmio_register_block.h>
1.73 +
1.74 +// Forward declaration.
1.75 +
1.76 +class Dma_x1600_chip;
1.77 +
1.78 +
1.79 +
1.80 +// DMA channel.
1.81 +
1.82 +class Dma_x1600_channel
1.83 +{
1.84 +private:
1.85 + Hw::Register_block<32> _regs;
1.86 + Dma_x1600_chip *_chip;
1.87 + uint8_t _channel;
1.88 + l4_cap_idx_t _irq = L4_INVALID_CAP;
1.89 +
1.90 +public:
1.91 + Dma_x1600_channel(Dma_x1600_chip *chip, uint8_t channel, l4_addr_t start, l4_cap_idx_t irq);
1.92 +
1.93 + unsigned int transfer(uint32_t source, uint32_t destination,
1.94 + unsigned int count,
1.95 + bool source_increment, bool destination_increment,
1.96 + uint8_t source_width, uint8_t destination_width,
1.97 + uint8_t transfer_unit_size,
1.98 + enum Dma_x1600_request_type type=Dma_request_auto);
1.99 +
1.100 + unsigned int wait();
1.101 +
1.102 +protected:
1.103 + // Transfer property configuration.
1.104 +
1.105 + uint32_t encode_req_detect_int_length(uint8_t units);
1.106 +
1.107 + uint32_t encode_source_port_width(uint8_t width);
1.108 +
1.109 + uint32_t encode_destination_port_width(uint8_t width);
1.110 +
1.111 + uint32_t encode_transfer_unit_size(uint8_t size);
1.112 +
1.113 + // Transaction control.
1.114 +
1.115 + void ack_irq();
1.116 +
1.117 + bool completed();
1.118 +
1.119 + bool error();
1.120 +
1.121 + bool halted();
1.122 +
1.123 + bool wait_for_irq();
1.124 +
1.125 + bool wait_for_irq(unsigned int timeout);
1.126 +};
1.127 +
1.128 +// DMA device control.
1.129 +
1.130 +class Dma_x1600_chip
1.131 +{
1.132 +private:
1.133 + Hw::Register_block<32> _regs;
1.134 + l4_addr_t _start, _end;
1.135 + Cpm_x1600_chip *_cpm;
1.136 +
1.137 +public:
1.138 + Dma_x1600_chip(l4_addr_t start, l4_addr_t end, Cpm_x1600_chip *cpm);
1.139 +
1.140 + void disable();
1.141 +
1.142 + void enable();
1.143 +
1.144 + Dma_x1600_channel *get_channel(uint8_t channel, l4_cap_idx_t irq);
1.145 +
1.146 + // Transaction control.
1.147 +
1.148 + void ack_irq(uint8_t channel);
1.149 +
1.150 + bool error();
1.151 +
1.152 + bool halted();
1.153 +
1.154 + bool have_interrupt(uint8_t channel);
1.155 +};
1.156 +
1.157 +#endif /* __cplusplus */
1.158 +
1.159 +
1.160 +
1.161 +/* C language interface. */
1.162 +
1.163 +EXTERN_C_BEGIN
1.164 +
1.165 +void *x1600_dma_init(l4_addr_t start, l4_addr_t end, void *cpm);
1.166 +
1.167 +void x1600_dma_disable(void *dma_chip);
1.168 +
1.169 +void x1600_dma_enable(void *dma_chip);
1.170 +
1.171 +void *x1600_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq);
1.172 +
1.173 +unsigned int x1600_dma_transfer(void *dma_channel,
1.174 + uint32_t source, uint32_t destination,
1.175 + unsigned int count,
1.176 + int source_increment, int destination_increment,
1.177 + uint8_t source_width, uint8_t destination_width,
1.178 + uint8_t transfer_unit_size,
1.179 + enum Dma_x1600_request_type type);
1.180 +
1.181 +unsigned int x1600_dma_wait(void *dma_channel);
1.182 +
1.183 +EXTERN_C_END