1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Fri Sep 15 17:55:43 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Fri Sep 15 19:29:34 2023 +0200
1.3 @@ -38,21 +38,21 @@
1.4 Clock_gate1 = 0x028, // CLKGR1
1.5 Sleep_control = 0x024, // OPCR (oscillator and power control)
1.6 Clock_status = 0x0d4, // CPCSR
1.7 - Ddr_divider = 0x02c, // DDRCDR
1.8 - Mac_divider = 0x054, // MACCDR
1.9 - I2s_divider0 = 0x060, // I2SCDR
1.10 - I2s_divider1 = 0x070, // I2S1CDR
1.11 - Lcd_divider = 0x064, // LPCDR
1.12 - Msc_divider0 = 0x068, // MSC0CDR
1.13 - Msc_divider1 = 0x0a4, // MSC1CDR
1.14 - Sfc_divider = 0x074, // SFCCDR
1.15 - Ssi_divider = 0x05c, // SSICDR
1.16 - Cim_divider = 0x078, // CIMCDR
1.17 - Pwm_divider = 0x06c, // PWMCDR
1.18 - Can_divider0 = 0x0a0, // CAN0CDR
1.19 - Can_divider1 = 0x0a8, // CAN1CDR
1.20 - Cdbus_divider = 0x0ac, // CDBUSCDR
1.21 - Macphy0_divider = 0x0e4, // MPHY0C
1.22 + Divider_ddr = 0x02c, // DDRCDR
1.23 + Divider_mac = 0x054, // MACCDR
1.24 + Divider0_i2s0 = 0x060, // I2SCDR
1.25 + Divider1_i2s0 = 0x070, // I2S1CDR
1.26 + Divider_lcd = 0x064, // LPCDR
1.27 + Divider_msc0 = 0x068, // MSC0CDR
1.28 + Divider_msc1 = 0x0a4, // MSC1CDR
1.29 + Divider_sfc = 0x074, // SFCCDR
1.30 + Divider_ssi = 0x05c, // SSICDR
1.31 + Divider_cim = 0x078, // CIMCDR
1.32 + Divider_pwm = 0x06c, // PWMCDR
1.33 + Divider_can0 = 0x0a0, // CAN0CDR
1.34 + Divider_can1 = 0x0a8, // CAN1CDR
1.35 + Divider_cdbus = 0x0ac, // CDBUSCDR
1.36 + Divider_macphy0 = 0x0e4, // MPHY0C
1.37 Cpm_interrupt = 0x0b0, // CPM_INTR
1.38 Cpm_interrupt_en = 0x0b4, // CPM_INTRE
1.39 Cpm_swi = 0x0bc, // CPM_SFTINT
1.40 @@ -72,32 +72,6 @@
1.41 Pll_fraction_E = 0x08c, // CPEPACR
1.42 };
1.43
1.44 -enum Clock_source_bits : unsigned
1.45 -{
1.46 - // Clock_control
1.47 -
1.48 - Clock_source_main = 30, // SEL_SRC (output to SCLK_A)
1.49 - Clock_source_cpu = 28, // SEL_CPLL (output to CCLK)
1.50 - Clock_source_hclock0 = 26, // SEL_H0PLL (output to AHB0)
1.51 - Clock_source_hclock2 = 24, // SEL_H2PLL (output to AHB2)
1.52 -
1.53 - // Divider registers
1.54 -
1.55 - Clock_source_can0 = 30, // CA0CS
1.56 - Clock_source_can1 = 30, // CA1CS
1.57 - Clock_source_cdbus = 30, // CDCS
1.58 - Clock_source_cim = 30, // CIMPCS
1.59 - Clock_source_ddr = 30, // DCS
1.60 - Clock_source_i2s = 31, // I2PCS
1.61 - Clock_source_lcd = 30, // LPCS
1.62 - Clock_source_mac = 30, // MACPCS
1.63 - Clock_source_msc0 = 30, // MPCS
1.64 - Clock_source_msc1 = 30, // MPCS
1.65 - Clock_source_pwm = 30, // PWMPCS
1.66 - Clock_source_sfc = 30, // SFCS
1.67 - Clock_source_ssi = 30, // SPCS
1.68 -};
1.69 -
1.70 enum Clock_source_values : unsigned
1.71 {
1.72 Source_mME_main = 0,
1.73 @@ -109,115 +83,6 @@
1.74 Source_mask = 0x3,
1.75 };
1.76
1.77 -enum Clock_gate_bits : unsigned
1.78 -{
1.79 - // Clock_control
1.80 -
1.81 - Clock_gate_main = 23, // GATE_SCLKA
1.82 -
1.83 - // Clock_gate0
1.84 -
1.85 - Clock_gate_ddr = 31, // DDR
1.86 - Clock_gate_ahb0 = 29, // AHB0
1.87 - Clock_gate_apb0 = 28, // APB0
1.88 - Clock_gate_rtc = 27, // RTC
1.89 - Clock_gate_aes = 24, // AES
1.90 - Clock_gate_lcd_pixel = 23, // LCD
1.91 - Clock_gate_cim = 22, // CIM
1.92 - Clock_gate_dma = 21, // PDMA
1.93 - Clock_gate_ost = 20, // OST
1.94 - Clock_gate_ssi0 = 19, // SSI0
1.95 - Clock_gate_timer = 18, // TCU
1.96 - Clock_gate_dtrng = 17, // DTRNG
1.97 - Clock_gate_uart2 = 16, // UART2
1.98 - Clock_gate_uart1 = 15, // UART1
1.99 - Clock_gate_uart0 = 14, // UART0
1.100 - Clock_gate_sadc = 13, // SADC
1.101 - Clock_gate_audio = 11, // AUDIO
1.102 - Clock_gate_ssi_slv = 10, // SSI_SLV
1.103 - Clock_gate_i2c1 = 8, // I2C1
1.104 - Clock_gate_i2c0 = 7, // I2C0
1.105 - Clock_gate_msc1 = 5, // MSC1
1.106 - Clock_gate_msc0 = 4, // MSC0
1.107 - Clock_gate_otg = 3, // OTG
1.108 - Clock_gate_sfc = 2, // SFC
1.109 - Clock_gate_efuse = 1, // EFUSE
1.110 - Clock_gate_nemc = 0, // NEMC
1.111 -
1.112 - // Clock_gate1
1.113 -
1.114 - Clock_gate_arb = 30, // ARB
1.115 - Clock_gate_mipi_csi = 28, // MIPI_CSI
1.116 - Clock_gate_intc = 26, // INTC
1.117 - Clock_gate_gmac0 = 23, // GMAC0
1.118 - Clock_gate_uart3 = 16, // UART3
1.119 - Clock_gate_i2s0_tx = 9, // I2S0_dev_tclk
1.120 - Clock_gate_i2s0_rx = 8, // I2S0_dev_rclk
1.121 - Clock_gate_hash = 6, // HASH
1.122 - Clock_gate_pwm = 5, // PWM
1.123 - Clock_gate_cdbus = 2, // CDBUS
1.124 - Clock_gate_can1 = 1, // CAN1
1.125 - Clock_gate_can0 = 0, // CAN0
1.126 -};
1.127 -
1.128 -enum Clock_change_enable_bits : unsigned
1.129 -{
1.130 - Clock_change_enable_cpu = 22,
1.131 - Clock_change_enable_ahb0 = 21,
1.132 - Clock_change_enable_ahb2 = 20,
1.133 - Clock_change_enable_ddr = 29,
1.134 - Clock_change_enable_mac = 29,
1.135 - Clock_change_enable_i2s = 29,
1.136 - Clock_change_enable_lcd = 29,
1.137 - Clock_change_enable_msc0 = 29,
1.138 - Clock_change_enable_msc1 = 29,
1.139 - Clock_change_enable_sfc = 29,
1.140 - Clock_change_enable_ssi = 29,
1.141 - Clock_change_enable_cim = 29,
1.142 - Clock_change_enable_pwm = 29,
1.143 - Clock_change_enable_can0 = 29,
1.144 - Clock_change_enable_can1 = 29,
1.145 - Clock_change_enable_cdbus = 29,
1.146 -};
1.147 -
1.148 -enum Clock_busy_bits : unsigned
1.149 -{
1.150 - Clock_busy_cpu = 0,
1.151 - Clock_busy_ddr = 28,
1.152 - Clock_busy_mac = 28,
1.153 - Clock_busy_lcd = 28,
1.154 - Clock_busy_msc0 = 28,
1.155 - Clock_busy_msc1 = 28,
1.156 - Clock_busy_sfc = 28,
1.157 - Clock_busy_ssi = 28,
1.158 - Clock_busy_cim = 28,
1.159 - Clock_busy_pwm = 28,
1.160 - Clock_busy_can0 = 28,
1.161 - Clock_busy_can1 = 28,
1.162 - Clock_busy_cdbus = 28,
1.163 -};
1.164 -
1.165 -enum Clock_divider_bits : unsigned
1.166 -{
1.167 - Clock_divider_can0 = 0, // CAN0CDR
1.168 - Clock_divider_can1 = 0, // CAN1CDR
1.169 - Clock_divider_cdbus = 0, // CDBUSCDR
1.170 - Clock_divider_cim = 0, // CIMCDR
1.171 - Clock_divider_cpu = 0, // CDIV
1.172 - Clock_divider_ddr = 0, // DDRCDR
1.173 - Clock_divider_hclock0 = 8, // H0DIV (fast AHB peripherals)
1.174 - Clock_divider_hclock2 = 12, // H2DIV (fast AHB peripherals)
1.175 - Clock_divider_l2cache = 4, // L2CDIV
1.176 - Clock_divider_lcd = 0, // LPCDR
1.177 - Clock_divider_mac = 0, // MACCDR
1.178 - Clock_divider_msc0 = 0, // MSC0CDR
1.179 - Clock_divider_msc1 = 0, // MSC1CDR
1.180 - Clock_divider_pclock = 16, // PDIV (slow APB peripherals)
1.181 - Clock_divider_pwm = 0, // PWMCDR
1.182 - Clock_divider_sfc = 0, // SFCCDR
1.183 - Clock_divider_ssi = 0, // SSICDR
1.184 -};
1.185 -
1.186 enum Pll_bits : unsigned
1.187 {
1.188 // Pll_control_A, Pll_control_M, Pll_control_E
1.189 @@ -406,158 +271,269 @@
1.190
1.191
1.192
1.193 +// Register field definitions.
1.194 +
1.195 +Field Clock_source_main (Clock_control, 3, 30); // SEL_SRC (output to SCLK_A)
1.196 +Field Clock_source_cpu (Clock_control, 3, 28); // SEL_CPLL (output to CCLK)
1.197 +Field Clock_source_hclock0 (Clock_control, 3, 26); // SEL_H0PLL (output to AHB0)
1.198 +Field Clock_source_hclock2 (Clock_control, 3, 24); // SEL_H2PLL (output to AHB2)
1.199 +Field Clock_source_can0 (Divider_can0, 3, 30); // CA0CS
1.200 +Field Clock_source_can1 (Divider_can1, 3, 30); // CA1CS
1.201 +Field Clock_source_cdbus (Divider_cdbus, 3, 30); // CDCS
1.202 +Field Clock_source_cim (Divider_cim, 3, 30); // CIMPCS
1.203 +Field Clock_source_ddr (Divider_ddr, 3, 30); // DCS
1.204 +Field Clock_source_i2s (Divider0_i2s0, 1, 31); // I2PCS
1.205 +Field Clock_source_lcd (Divider_lcd, 3, 30); // LPCS
1.206 +Field Clock_source_mac (Divider_mac, 3, 30); // MACPCS
1.207 +Field Clock_source_msc0 (Divider_msc0, 3, 30); // MPCS
1.208 +Field Clock_source_msc1 (Divider_msc1, 3, 30); // MPCS
1.209 +Field Clock_source_pwm (Divider_pwm, 3, 30); // PWMPCS
1.210 +Field Clock_source_sfc (Divider_sfc, 3, 30); // SFCS
1.211 +Field Clock_source_ssi (Divider_ssi, 3, 30); // SPCS
1.212 +
1.213 +Field Clock_busy_cpu (Clock_status, 1, 0);
1.214 +Field Clock_busy_ddr (Divider_ddr, 1, 28);
1.215 +Field Clock_busy_mac (Divider_mac, 1, 28);
1.216 +Field Clock_busy_lcd (Divider_lcd, 1, 28);
1.217 +Field Clock_busy_msc0 (Divider_msc0, 1, 28);
1.218 +Field Clock_busy_msc1 (Divider_msc1, 1, 28);
1.219 +Field Clock_busy_sfc (Divider_sfc, 1, 28);
1.220 +Field Clock_busy_ssi (Divider_ssi, 1, 28);
1.221 +Field Clock_busy_cim (Divider_cim, 1, 28);
1.222 +Field Clock_busy_pwm (Divider_pwm, 1, 28);
1.223 +Field Clock_busy_can0 (Divider_can0, 1, 28);
1.224 +Field Clock_busy_can1 (Divider_can1, 1, 28);
1.225 +Field Clock_busy_cdbus (Divider_cdbus, 1, 28);
1.226 +
1.227 +Field Clock_change_enable_cpu (Clock_control, 1, 22);
1.228 +Field Clock_change_enable_ahb0 (Clock_control, 1, 21);
1.229 +Field Clock_change_enable_ahb2 (Clock_control, 1, 20);
1.230 +Field Clock_change_enable_ddr (Divider_ddr, 1, 29);
1.231 +Field Clock_change_enable_mac (Divider_mac, 1, 29);
1.232 +Field Clock_change_enable_i2s (Divider0_i2s0, 1, 29);
1.233 +Field Clock_change_enable_lcd (Divider_lcd, 1, 29);
1.234 +Field Clock_change_enable_msc0 (Divider_msc0, 1, 29);
1.235 +Field Clock_change_enable_msc1 (Divider_msc1, 1, 29);
1.236 +Field Clock_change_enable_sfc (Divider_sfc, 1, 29);
1.237 +Field Clock_change_enable_ssi (Divider_ssi, 1, 29);
1.238 +Field Clock_change_enable_cim (Divider_cim, 1, 29);
1.239 +Field Clock_change_enable_pwm (Divider_pwm, 1, 29);
1.240 +Field Clock_change_enable_can0 (Divider_can0, 1, 29);
1.241 +Field Clock_change_enable_can1 (Divider_can1, 1, 29);
1.242 +Field Clock_change_enable_cdbus (Divider_cdbus, 1, 29);
1.243 +
1.244 +Field Clock_divider_can0 (Divider_can0, 0xff, 0); // CAN0CDR
1.245 +Field Clock_divider_can1 (Divider_can1, 0xff, 0); // CAN1CDR
1.246 +Field Clock_divider_cdbus (Divider_cdbus, 0xff, 0); // CDBUSCDR
1.247 +Field Clock_divider_cim (Divider_cim, 0xff, 0); // CIMCDR
1.248 +Field Clock_divider_cpu (Clock_control, 0x0f, 0); // CDIV
1.249 +Field Clock_divider_ddr (Divider_ddr, 0x0f, 0); // DDRCDR
1.250 +Field Clock_divider_hclock0 (Clock_control, 0x0f, 8); // H0DIV (fast AHB peripherals)
1.251 +Field Clock_divider_hclock2 (Clock_control, 0x0f, 12); // H2DIV (fast AHB peripherals)
1.252 +Field Clock_divider_l2cache (Clock_control, 0x0f, 4); // L2CDIV
1.253 +Field Clock_divider_lcd (Divider_lcd, 0xff, 0); // LPCDR
1.254 +Field Clock_divider_mac (Divider_mac, 0xff, 0); // MACCDR
1.255 +Field Clock_divider_msc0 (Divider_msc0, 0xff, 0); // MSC0CDR
1.256 +Field Clock_divider_msc1 (Divider_msc1, 0xff, 0); // MSC1CDR
1.257 +Field Clock_divider_pclock (Clock_control, 0x0f, 16); // PDIV (slow APB peripherals)
1.258 +Field Clock_divider_pwm (Divider_pwm, 0x0f, 0); // PWMCDR
1.259 +Field Clock_divider_sfc (Divider_sfc, 0xff, 0); // SFCCDR
1.260 +Field Clock_divider_ssi (Divider_ssi, 0xff, 0); // SSICDR
1.261 +
1.262 +Field Clock_gate_main (Clock_control, 1, 23); // GATE_SCLKA
1.263 +Field Clock_gate_ddr (Clock_gate0, 1, 31); // DDR
1.264 +Field Clock_gate_ahb0 (Clock_gate0, 1, 29); // AHB0
1.265 +Field Clock_gate_apb0 (Clock_gate0, 1, 28); // APB0
1.266 +Field Clock_gate_rtc (Clock_gate0, 1, 27); // RTC
1.267 +Field Clock_gate_aes (Clock_gate0, 1, 24); // AES
1.268 +Field Clock_gate_lcd_pixel (Clock_gate0, 1, 23); // LCD
1.269 +Field Clock_gate_cim (Clock_gate0, 1, 22); // CIM
1.270 +Field Clock_gate_dma (Clock_gate0, 1, 21); // PDMA
1.271 +Field Clock_gate_ost (Clock_gate0, 1, 20); // OST
1.272 +Field Clock_gate_ssi0 (Clock_gate0, 1, 19); // SSI0
1.273 +Field Clock_gate_timer (Clock_gate0, 1, 18); // TCU
1.274 +Field Clock_gate_dtrng (Clock_gate0, 1, 17); // DTRNG
1.275 +Field Clock_gate_uart2 (Clock_gate0, 1, 16); // UART2
1.276 +Field Clock_gate_uart1 (Clock_gate0, 1, 15); // UART1
1.277 +Field Clock_gate_uart0 (Clock_gate0, 1, 14); // UART0
1.278 +Field Clock_gate_sadc (Clock_gate0, 1, 13); // SADC
1.279 +Field Clock_gate_audio (Clock_gate0, 1, 11); // AUDIO
1.280 +Field Clock_gate_ssi_slv (Clock_gate0, 1, 10); // SSI_SLV
1.281 +Field Clock_gate_i2c1 (Clock_gate0, 1, 8); // I2C1
1.282 +Field Clock_gate_i2c0 (Clock_gate0, 1, 7); // I2C0
1.283 +Field Clock_gate_msc1 (Clock_gate0, 1, 5); // MSC1
1.284 +Field Clock_gate_msc0 (Clock_gate0, 1, 4); // MSC0
1.285 +Field Clock_gate_otg (Clock_gate0, 1, 3); // OTG
1.286 +Field Clock_gate_sfc (Clock_gate0, 1, 2); // SFC
1.287 +Field Clock_gate_efuse (Clock_gate0, 1, 1); // EFUSE
1.288 +Field Clock_gate_nemc (Clock_gate0, 1, 0); // NEMC
1.289 +Field Clock_gate_arb (Clock_gate1, 1, 30); // ARB
1.290 +Field Clock_gate_mipi_csi (Clock_gate1, 1, 28); // MIPI_CSI
1.291 +Field Clock_gate_intc (Clock_gate1, 1, 26); // INTC
1.292 +Field Clock_gate_gmac0 (Clock_gate1, 1, 23); // GMAC0
1.293 +Field Clock_gate_uart3 (Clock_gate1, 1, 16); // UART3
1.294 +Field Clock_gate_i2s0_tx (Clock_gate1, 1, 9); // I2S0_dev_tclk
1.295 +Field Clock_gate_i2s0_rx (Clock_gate1, 1, 8); // I2S0_dev_rclk
1.296 +Field Clock_gate_hash (Clock_gate1, 1, 6); // HASH
1.297 +Field Clock_gate_pwm (Clock_gate1, 1, 5); // PWM
1.298 +Field Clock_gate_cdbus (Clock_gate1, 1, 2); // CDBUS
1.299 +Field Clock_gate_can1 (Clock_gate1, 1, 1); // CAN1
1.300 +Field Clock_gate_can0 (Clock_gate1, 1, 0); // CAN0
1.301 +
1.302 +
1.303 +
1.304 // Clock instances.
1.305
1.306 #define Clock_inputs(...) ((enum Clock_identifiers []) {__VA_ARGS__})
1.307
1.308 Clock clock_ahb2_apb(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M),
1.309 - Field(Clock_control, 3, Clock_source_hclock2));
1.310 + Clock_source_hclock2);
1.311
1.312 Clock clock_aic_bitclk;
1.313
1.314 Clock clock_aic_pclk;
1.315
1.316 Clock clock_can0(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external),
1.317 - Field(Can_divider0, 3, Clock_source_can0),
1.318 - Field(Clock_gate1, 1, Clock_gate_can0),
1.319 - Field(Can_divider0, 1, Clock_change_enable_can0),
1.320 - Field(Can_divider0, 1, Clock_busy_can0),
1.321 - Field(Can_divider0, 0xff, Clock_divider_can0));
1.322 + Clock_source_can0,
1.323 + Clock_gate_can0,
1.324 + Clock_change_enable_can0,
1.325 + Clock_busy_can0,
1.326 + Clock_divider_can0);
1.327
1.328 Clock clock_can1(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external),
1.329 - Field(Can_divider1, 3, Clock_source_can1),
1.330 - Field(Clock_gate1, 1, Clock_gate_can1),
1.331 - Field(Can_divider1, 1, Clock_change_enable_can1),
1.332 - Field(Can_divider1, 1, Clock_busy_can1),
1.333 - Field(Can_divider1, 0xff, Clock_divider_can1));
1.334 + Clock_source_can1,
1.335 + Clock_gate_can1,
1.336 + Clock_change_enable_can1,
1.337 + Clock_busy_can1,
1.338 + Clock_divider_can1);
1.339
1.340 Clock clock_cdbus(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.341 - Field(Cdbus_divider, 3, Clock_source_cdbus),
1.342 - Field(Clock_gate1, 1, Clock_gate_cdbus),
1.343 - Field(Cdbus_divider, 1, Clock_change_enable_cdbus),
1.344 - Field(Cdbus_divider, 1, Clock_busy_cdbus),
1.345 - Field(Cdbus_divider, 0xff, Clock_divider_cdbus));
1.346 + Clock_source_cdbus,
1.347 + Clock_gate_cdbus,
1.348 + Clock_change_enable_cdbus,
1.349 + Clock_busy_cdbus,
1.350 + Clock_divider_cdbus);
1.351
1.352 Clock clock_cim(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.353 - Field(Cim_divider, 3, Clock_source_cim),
1.354 - Field(Clock_gate0, 1, Clock_gate_cim),
1.355 - Field(Cim_divider, 1, Clock_change_enable_cim),
1.356 - Field(Cim_divider, 1, Clock_busy_cim),
1.357 - Field(Cim_divider, 0xff, Clock_divider_cim));
1.358 + Clock_source_cim,
1.359 + Clock_gate_cim,
1.360 + Clock_change_enable_cim,
1.361 + Clock_busy_cim,
1.362 + Clock_divider_cim);
1.363
1.364 Clock clock_cpu(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M),
1.365 - Field(Clock_control, 3, Clock_source_cpu),
1.366 + Clock_source_cpu,
1.367 Gate_undefined,
1.368 - Field(Clock_control, 1, Clock_change_enable_cpu),
1.369 - Field(Clock_status, 1, Clock_busy_cpu),
1.370 - Field(Clock_control, 0x0f, Clock_divider_cpu));
1.371 + Clock_change_enable_cpu,
1.372 + Clock_busy_cpu,
1.373 + Clock_divider_cpu);
1.374
1.375 Clock clock_ddr(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M),
1.376 - Field(Ddr_divider, 3, Clock_source_ddr),
1.377 - Field(Clock_gate0, 1, Clock_gate_ddr),
1.378 - Field(Ddr_divider, 1, Clock_change_enable_ddr),
1.379 - Field(Ddr_divider, 1, Clock_busy_ddr),
1.380 - Field(Ddr_divider, 0x0f, Clock_divider_ddr));
1.381 + Clock_source_ddr,
1.382 + Clock_gate_ddr,
1.383 + Clock_change_enable_ddr,
1.384 + Clock_busy_ddr,
1.385 + Clock_divider_ddr);
1.386
1.387 Clock clock_dma(1, Clock_inputs(Clock_pclock),
1.388 Source_undefined,
1.389 - Field(Clock_gate0, 1, Clock_gate_dma));
1.390 + Clock_gate_dma);
1.391
1.392 Clock clock_emac;
1.393
1.394 Clock clock_external;
1.395
1.396 Clock clock_hclock0(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M),
1.397 - Field(Clock_control, 3, Clock_source_hclock0),
1.398 - Field(Clock_gate0, 1, Clock_gate_ahb0),
1.399 - Field(Clock_control, 1, Clock_change_enable_ahb0),
1.400 + Clock_source_hclock0,
1.401 + Clock_gate_ahb0,
1.402 + Clock_change_enable_ahb0,
1.403 Busy_undefined,
1.404 - Field(Clock_control, 0x0f, Clock_divider_hclock0));
1.405 + Clock_divider_hclock0);
1.406
1.407 Clock clock_hclock2(1, Clock_inputs(Clock_ahb2_apb),
1.408 Source_undefined,
1.409 - Field(Clock_gate0, 1, Clock_gate_apb0),
1.410 - Field(Clock_control, 1, Clock_change_enable_ahb2),
1.411 + Clock_gate_apb0,
1.412 + Clock_change_enable_ahb2,
1.413 Busy_undefined,
1.414 - Field(Clock_control, 0x0f, Clock_divider_hclock2));
1.415 + Clock_divider_hclock2);
1.416
1.417 Clock clock_hdmi;
1.418
1.419 Clock clock_i2c(1, Clock_inputs(Clock_pclock),
1.420 Source_undefined,
1.421 - Field(Clock_gate0, 1, Clock_gate_i2c0));
1.422 + Clock_gate_i2c0);
1.423
1.424 Clock clock_i2c0(1, Clock_inputs(Clock_pclock),
1.425 Source_undefined,
1.426 - Field(Clock_gate0, 1, Clock_gate_i2c0));
1.427 + Clock_gate_i2c0);
1.428
1.429 Clock clock_i2c1(1, Clock_inputs(Clock_pclock),
1.430 Source_undefined,
1.431 - Field(Clock_gate0, 1, Clock_gate_i2c1));
1.432 + Clock_gate_i2c1);
1.433
1.434 Clock clock_i2s;
1.435
1.436 Clock clock_i2s0_rx(2, Clock_inputs(Clock_main, Clock_pll_E),
1.437 - Field(I2s_divider0, 1, Clock_source_i2s),
1.438 - Field(Clock_gate1, 1, Clock_gate_i2s0_rx),
1.439 - Field(I2s_divider0, 1, Clock_change_enable_i2s));
1.440 + Clock_source_i2s,
1.441 + Clock_gate_i2s0_rx,
1.442 + Clock_change_enable_i2s);
1.443
1.444 Clock clock_i2s0_tx(2, Clock_inputs(Clock_main, Clock_pll_E),
1.445 - Field(I2s_divider0, 1, Clock_source_i2s),
1.446 - Field(Clock_gate1, 1, Clock_gate_i2s0_tx),
1.447 - Field(I2s_divider0, 1, Clock_change_enable_i2s));
1.448 + Clock_source_i2s,
1.449 + Clock_gate_i2s0_tx,
1.450 + Clock_change_enable_i2s);
1.451
1.452 Clock clock_kbc;
1.453
1.454 Clock clock_lcd;
1.455
1.456 Clock clock_lcd_pixel(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.457 - Field(Lcd_divider, 3, Clock_source_lcd),
1.458 - Field(Clock_gate0, 1, Clock_gate_lcd_pixel),
1.459 - Field(Lcd_divider, 1, Clock_change_enable_lcd),
1.460 - Field(Lcd_divider, 1, Clock_busy_lcd),
1.461 - Field(Lcd_divider, 0xff, Clock_divider_lcd));
1.462 + Clock_source_lcd,
1.463 + Clock_gate_lcd_pixel,
1.464 + Clock_change_enable_lcd,
1.465 + Clock_busy_lcd,
1.466 + Clock_divider_lcd);
1.467
1.468 Clock clock_mac(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.469 - Field(Mac_divider, 3, Clock_source_mac),
1.470 - Field(Clock_gate1, 1, Clock_gate_gmac0),
1.471 - Field(Mac_divider, 1, Clock_change_enable_mac),
1.472 - Field(Mac_divider, 1, Clock_busy_mac),
1.473 - Field(Mac_divider, 0xff, Clock_divider_mac));
1.474 + Clock_source_mac,
1.475 + Clock_gate_gmac0,
1.476 + Clock_change_enable_mac,
1.477 + Clock_busy_mac,
1.478 + Clock_divider_mac);
1.479
1.480 Clock clock_main(3, Clock_inputs(Clock_none, Clock_external, Clock_pll_A),
1.481 - Field(Clock_control, 3, Clock_source_main),
1.482 - Field(Clock_control, 1, Clock_gate_main));
1.483 + Clock_source_main,
1.484 + Clock_gate_main);
1.485
1.486 Clock clock_msc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.487 - Field(Msc_divider0, 3, Clock_source_msc0),
1.488 - Field(Clock_gate0, 1, Clock_gate_msc0),
1.489 - Field(Msc_divider0, 1, Clock_change_enable_msc0),
1.490 - Field(Msc_divider0, 1, Clock_busy_msc0),
1.491 - Field(Msc_divider0, 0xff, Clock_divider_msc0));
1.492 + Clock_source_msc0,
1.493 + Clock_gate_msc0,
1.494 + Clock_change_enable_msc0,
1.495 + Clock_busy_msc0,
1.496 + Clock_divider_msc0);
1.497
1.498 Clock clock_msc0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.499 - Field(Msc_divider0, 3, Clock_source_msc0),
1.500 - Field(Clock_gate0, 1, Clock_gate_msc0),
1.501 - Field(Msc_divider0, 1, Clock_change_enable_msc0),
1.502 - Field(Msc_divider0, 1, Clock_busy_msc0),
1.503 - Field(Msc_divider0, 0xff, Clock_divider_msc0));
1.504 + Clock_source_msc0,
1.505 + Clock_gate_msc0,
1.506 + Clock_change_enable_msc0,
1.507 + Clock_busy_msc0,
1.508 + Clock_divider_msc0);
1.509
1.510 Clock clock_msc1(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.511 - Field(Msc_divider1, 3, Clock_source_msc1),
1.512 - Field(Clock_gate0, 1, Clock_gate_msc1),
1.513 - Field(Msc_divider1, 1, Clock_change_enable_msc1),
1.514 - Field(Msc_divider1, 1, Clock_busy_msc1),
1.515 - Field(Msc_divider1, 0xff, Clock_divider_msc1));
1.516 + Clock_source_msc1,
1.517 + Clock_gate_msc1,
1.518 + Clock_change_enable_msc1,
1.519 + Clock_busy_msc1,
1.520 + Clock_divider_msc1);
1.521
1.522 Clock clock_none;
1.523
1.524 Clock clock_pclock(1, Clock_inputs(Clock_ahb2_apb),
1.525 Source_undefined,
1.526 - Field(Clock_gate0, 1, Clock_gate_apb0),
1.527 + Clock_gate_apb0,
1.528 Change_enable_undefined,
1.529 Busy_undefined,
1.530 - Field(Clock_control, 0x0f, Clock_divider_pclock));
1.531 + Clock_divider_pclock);
1.532
1.533 Pll clock_pll_A(1, Clock_inputs(Clock_external),
1.534 Pll_control_A, Pll_bypass_A);
1.535 @@ -569,29 +545,29 @@
1.536 Pll_control_M, Pll_bypass_M);
1.537
1.538 Clock clock_pwm(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.539 - Field(Pwm_divider, 3, Clock_source_pwm),
1.540 - Field(Clock_gate1, 1, Clock_gate_pwm),
1.541 - Field(Pwm_divider, 1, Clock_change_enable_pwm),
1.542 - Field(Pwm_divider, 1, Clock_busy_pwm),
1.543 - Field(Pwm_divider, 0x0f, Clock_divider_pwm));
1.544 + Clock_source_pwm,
1.545 + Clock_gate_pwm,
1.546 + Clock_change_enable_pwm,
1.547 + Clock_busy_pwm,
1.548 + Clock_divider_pwm);
1.549
1.550 Clock clock_pwm0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.551 - Field(Pwm_divider, 3, Clock_source_pwm),
1.552 - Field(Clock_gate1, 1, Clock_gate_pwm),
1.553 - Field(Pwm_divider, 1, Clock_change_enable_pwm),
1.554 - Field(Pwm_divider, 1, Clock_busy_pwm),
1.555 - Field(Pwm_divider, 0x0f, Clock_divider_pwm));
1.556 + Clock_source_pwm,
1.557 + Clock_gate_pwm,
1.558 + Clock_change_enable_pwm,
1.559 + Clock_busy_pwm,
1.560 + Clock_divider_pwm);
1.561
1.562 Clock clock_pwm1;
1.563
1.564 Clock clock_scc;
1.565
1.566 Clock clock_sfc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.567 - Field(Sfc_divider, 3, Clock_source_sfc),
1.568 - Field(Clock_gate0, 1, Clock_gate_sfc),
1.569 - Field(Sfc_divider, 1, Clock_change_enable_sfc),
1.570 - Field(Sfc_divider, 1, Clock_busy_sfc),
1.571 - Field(Sfc_divider, 0xff, Clock_divider_sfc));
1.572 + Clock_source_sfc,
1.573 + Clock_gate_sfc,
1.574 + Clock_change_enable_sfc,
1.575 + Clock_busy_sfc,
1.576 + Clock_divider_sfc);
1.577
1.578 Clock clock_smb0;
1.579
1.580 @@ -604,31 +580,31 @@
1.581 Clock clock_smb4;
1.582
1.583 Clock clock_ssi(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.584 - Field(Ssi_divider, 3, Clock_source_ssi),
1.585 - Field(Clock_gate0, 1, Clock_gate_ssi0),
1.586 - Field(Ssi_divider, 1, Clock_change_enable_ssi),
1.587 - Field(Ssi_divider, 1, Clock_busy_ssi),
1.588 - Field(Ssi_divider, 0xff, Clock_divider_ssi));
1.589 + Clock_source_ssi,
1.590 + Clock_gate_ssi0,
1.591 + Clock_change_enable_ssi,
1.592 + Clock_busy_ssi,
1.593 + Clock_divider_ssi);
1.594
1.595 Clock clock_timer(1, Clock_inputs(Clock_pclock),
1.596 Source_undefined,
1.597 - Field(Clock_gate0, 1, Clock_gate_timer));
1.598 + Clock_gate_timer);
1.599
1.600 Clock clock_uart0(1, Clock_inputs(Clock_external),
1.601 Source_undefined,
1.602 - Field(Clock_gate0, 1, Clock_gate_uart0));
1.603 + Clock_gate_uart0);
1.604
1.605 Clock clock_uart1(1, Clock_inputs(Clock_external),
1.606 Source_undefined,
1.607 - Field(Clock_gate0, 1, Clock_gate_uart1));
1.608 + Clock_gate_uart1);
1.609
1.610 Clock clock_uart2(1, Clock_inputs(Clock_external),
1.611 Source_undefined,
1.612 - Field(Clock_gate0, 1, Clock_gate_uart2));
1.613 + Clock_gate_uart2);
1.614
1.615 Clock clock_uart3(1, Clock_inputs(Clock_external),
1.616 Source_undefined,
1.617 - Field(Clock_gate1, 1, Clock_gate_uart3));
1.618 + Clock_gate_uart3);
1.619
1.620 Clock clock_udc;
1.621