1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Fri Sep 15 00:31:43 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Fri Sep 15 17:55:43 2023 +0200
1.3 @@ -70,10 +70,6 @@
1.4 Pll_fraction_A = 0x084, // CPAPACR
1.5 Pll_fraction_M = 0x088, // CPMPACR
1.6 Pll_fraction_E = 0x08c, // CPEPACR
1.7 -
1.8 - // Special value
1.9 -
1.10 - Reg_undefined = 0xfff,
1.11 };
1.12
1.13 enum Clock_source_bits : unsigned
1.14 @@ -100,10 +96,6 @@
1.15 Clock_source_pwm = 30, // PWMPCS
1.16 Clock_source_sfc = 30, // SFCS
1.17 Clock_source_ssi = 30, // SPCS
1.18 -
1.19 - // Special value
1.20 -
1.21 - Clock_source_undefined = 32,
1.22 };
1.23
1.24 enum Clock_source_values : unsigned
1.25 @@ -166,10 +158,6 @@
1.26 Clock_gate_cdbus = 2, // CDBUS
1.27 Clock_gate_can1 = 1, // CAN1
1.28 Clock_gate_can0 = 0, // CAN0
1.29 -
1.30 - // Special value
1.31 -
1.32 - Clock_gate_undefined = 32,
1.33 };
1.34
1.35 enum Clock_change_enable_bits : unsigned
1.36 @@ -190,10 +178,6 @@
1.37 Clock_change_enable_can0 = 29,
1.38 Clock_change_enable_can1 = 29,
1.39 Clock_change_enable_cdbus = 29,
1.40 -
1.41 - // Special value
1.42 -
1.43 - Clock_change_enable_undefined = 32,
1.44 };
1.45
1.46 enum Clock_busy_bits : unsigned
1.47 @@ -211,10 +195,6 @@
1.48 Clock_busy_can0 = 28,
1.49 Clock_busy_can1 = 28,
1.50 Clock_busy_cdbus = 28,
1.51 -
1.52 - // Special value
1.53 -
1.54 - Clock_busy_undefined = 32,
1.55 };
1.56
1.57 enum Clock_divider_bits : unsigned
1.58 @@ -236,10 +216,6 @@
1.59 Clock_divider_pwm = 0, // PWMCDR
1.60 Clock_divider_sfc = 0, // SFCCDR
1.61 Clock_divider_ssi = 0, // SSICDR
1.62 -
1.63 - // Special value
1.64 -
1.65 - Clock_divider_undefined = 32,
1.66 };
1.67
1.68 enum Pll_bits : unsigned
1.69 @@ -263,6 +239,37 @@
1.70
1.71
1.72
1.73 +// Register field abstraction.
1.74 +
1.75 +class Field
1.76 +{
1.77 + uint32_t reg;
1.78 + uint32_t mask;
1.79 + uint8_t bit;
1.80 + bool defined;
1.81 +
1.82 +public:
1.83 + explicit Field()
1.84 + : defined(false)
1.85 + {
1.86 + }
1.87 +
1.88 + explicit Field(uint32_t reg, uint32_t mask, uint32_t bit)
1.89 + : reg(reg), mask(mask), bit(bit), defined(true)
1.90 + {
1.91 + }
1.92 +
1.93 + uint32_t get_field(Cpm_regs ®s);
1.94 + void set_field(Cpm_regs ®s, uint32_t value);
1.95 + bool is_defined() { return defined; }
1.96 +};
1.97 +
1.98 +// Undefined fields.
1.99 +
1.100 +Field Source_undefined, Gate_undefined, Change_enable_undefined, Busy_undefined, Divider_undefined;
1.101 +
1.102 +
1.103 +
1.104 // Common clock abstraction.
1.105
1.106 class Clock_base
1.107 @@ -273,16 +280,13 @@
1.108
1.109 int num_inputs;
1.110 enum Clock_identifiers *inputs;
1.111 - uint32_t source_reg;
1.112 - enum Clock_source_bits source_bit;
1.113 + Field _source;
1.114
1.115 public:
1.116 explicit Clock_base(int num_inputs = 0,
1.117 enum Clock_identifiers inputs[] = NULL,
1.118 - uint32_t source_reg = Reg_undefined,
1.119 - enum Clock_source_bits source_bit = Clock_source_undefined)
1.120 - : num_inputs(num_inputs), inputs(inputs),
1.121 - source_reg(source_reg), source_bit(source_bit)
1.122 + Field source = Source_undefined)
1.123 + : num_inputs(num_inputs), inputs(inputs), _source(source)
1.124 {
1.125 }
1.126
1.127 @@ -364,15 +368,7 @@
1.128
1.129 class Clock : public Clock_base
1.130 {
1.131 - uint32_t gate_reg;
1.132 - enum Clock_gate_bits gate_bit;
1.133 - uint32_t change_enable_reg;
1.134 - enum Clock_change_enable_bits change_enable_bit;
1.135 - uint32_t busy_reg;
1.136 - enum Clock_busy_bits busy_bit;
1.137 - uint32_t divider_reg;
1.138 - enum Clock_divider_bits divider_bit;
1.139 - uint32_t divider_mask;
1.140 + Field _gate, _change_enable, _busy, _divider;
1.141
1.142 // Clock control.
1.143
1.144 @@ -381,24 +377,14 @@
1.145 void wait_busy(Cpm_regs ®s);
1.146
1.147 public:
1.148 - explicit Clock(int num_inputs = 0,
1.149 - enum Clock_identifiers inputs[] = NULL,
1.150 - uint32_t source_reg = Reg_undefined,
1.151 - enum Clock_source_bits source_bit = Clock_source_undefined,
1.152 - uint32_t gate_reg = Reg_undefined,
1.153 - enum Clock_gate_bits gate_bit = Clock_gate_undefined,
1.154 - uint32_t change_enable_reg = Reg_undefined,
1.155 - enum Clock_change_enable_bits change_enable_bit = Clock_change_enable_undefined,
1.156 - uint32_t busy_reg = Reg_undefined,
1.157 - enum Clock_busy_bits busy_bit = Clock_busy_undefined,
1.158 - uint32_t divider_reg = Reg_undefined,
1.159 - enum Clock_divider_bits divider_bit = Clock_divider_undefined,
1.160 - uint32_t divider_mask = 0)
1.161 - : Clock_base(num_inputs, inputs, source_reg, source_bit),
1.162 - gate_reg(gate_reg), gate_bit(gate_bit),
1.163 - change_enable_reg(change_enable_reg), change_enable_bit(change_enable_bit),
1.164 - busy_reg(busy_reg), busy_bit(busy_bit),
1.165 - divider_reg(divider_reg), divider_bit(divider_bit), divider_mask(divider_mask)
1.166 + explicit Clock(int num_inputs = 0, enum Clock_identifiers inputs[] = NULL,
1.167 + Field source = Source_undefined,
1.168 + Field gate = Gate_undefined,
1.169 + Field change_enable = Change_enable_undefined,
1.170 + Field busy = Busy_undefined,
1.171 + Field divider = Divider_undefined)
1.172 + : Clock_base(num_inputs, inputs, source),
1.173 + _gate(gate), _change_enable(change_enable), _busy(busy), _divider(divider)
1.174 {
1.175 }
1.176
1.177 @@ -425,153 +411,153 @@
1.178 #define Clock_inputs(...) ((enum Clock_identifiers []) {__VA_ARGS__})
1.179
1.180 Clock clock_ahb2_apb(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M),
1.181 - Clock_control, Clock_source_hclock2);
1.182 + Field(Clock_control, 3, Clock_source_hclock2));
1.183
1.184 Clock clock_aic_bitclk;
1.185
1.186 Clock clock_aic_pclk;
1.187
1.188 Clock clock_can0(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external),
1.189 - Can_divider0, Clock_source_can0,
1.190 - Clock_gate1, Clock_gate_can0,
1.191 - Can_divider0, Clock_change_enable_can0,
1.192 - Can_divider0, Clock_busy_can0,
1.193 - Can_divider0, Clock_divider_can0, 0xff);
1.194 + Field(Can_divider0, 3, Clock_source_can0),
1.195 + Field(Clock_gate1, 1, Clock_gate_can0),
1.196 + Field(Can_divider0, 1, Clock_change_enable_can0),
1.197 + Field(Can_divider0, 1, Clock_busy_can0),
1.198 + Field(Can_divider0, 0xff, Clock_divider_can0));
1.199
1.200 Clock clock_can1(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external),
1.201 - Can_divider1, Clock_source_can1,
1.202 - Clock_gate1, Clock_gate_can1,
1.203 - Can_divider1, Clock_change_enable_can1,
1.204 - Can_divider1, Clock_busy_can1,
1.205 - Can_divider1, Clock_divider_can1, 0xff);
1.206 + Field(Can_divider1, 3, Clock_source_can1),
1.207 + Field(Clock_gate1, 1, Clock_gate_can1),
1.208 + Field(Can_divider1, 1, Clock_change_enable_can1),
1.209 + Field(Can_divider1, 1, Clock_busy_can1),
1.210 + Field(Can_divider1, 0xff, Clock_divider_can1));
1.211
1.212 Clock clock_cdbus(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.213 - Cdbus_divider, Clock_source_cdbus,
1.214 - Clock_gate1, Clock_gate_cdbus,
1.215 - Cdbus_divider, Clock_change_enable_cdbus,
1.216 - Cdbus_divider, Clock_busy_cdbus,
1.217 - Cdbus_divider, Clock_divider_cdbus, 0xff);
1.218 + Field(Cdbus_divider, 3, Clock_source_cdbus),
1.219 + Field(Clock_gate1, 1, Clock_gate_cdbus),
1.220 + Field(Cdbus_divider, 1, Clock_change_enable_cdbus),
1.221 + Field(Cdbus_divider, 1, Clock_busy_cdbus),
1.222 + Field(Cdbus_divider, 0xff, Clock_divider_cdbus));
1.223
1.224 Clock clock_cim(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.225 - Cim_divider, Clock_source_cim,
1.226 - Clock_gate0, Clock_gate_cim,
1.227 - Cim_divider, Clock_change_enable_cim,
1.228 - Cim_divider, Clock_busy_cim,
1.229 - Cim_divider, Clock_divider_cim, 0xff);
1.230 + Field(Cim_divider, 3, Clock_source_cim),
1.231 + Field(Clock_gate0, 1, Clock_gate_cim),
1.232 + Field(Cim_divider, 1, Clock_change_enable_cim),
1.233 + Field(Cim_divider, 1, Clock_busy_cim),
1.234 + Field(Cim_divider, 0xff, Clock_divider_cim));
1.235
1.236 Clock clock_cpu(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M),
1.237 - Clock_control, Clock_source_cpu,
1.238 - Reg_undefined, Clock_gate_undefined,
1.239 - Clock_control, Clock_change_enable_cpu,
1.240 - Clock_status, Clock_busy_cpu,
1.241 - Clock_control, Clock_divider_cpu, 0x0f);
1.242 + Field(Clock_control, 3, Clock_source_cpu),
1.243 + Gate_undefined,
1.244 + Field(Clock_control, 1, Clock_change_enable_cpu),
1.245 + Field(Clock_status, 1, Clock_busy_cpu),
1.246 + Field(Clock_control, 0x0f, Clock_divider_cpu));
1.247
1.248 Clock clock_ddr(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M),
1.249 - Ddr_divider, Clock_source_ddr,
1.250 - Clock_gate0, Clock_gate_ddr,
1.251 - Ddr_divider, Clock_change_enable_ddr,
1.252 - Ddr_divider, Clock_busy_ddr,
1.253 - Ddr_divider, Clock_divider_ddr, 0x0f);
1.254 + Field(Ddr_divider, 3, Clock_source_ddr),
1.255 + Field(Clock_gate0, 1, Clock_gate_ddr),
1.256 + Field(Ddr_divider, 1, Clock_change_enable_ddr),
1.257 + Field(Ddr_divider, 1, Clock_busy_ddr),
1.258 + Field(Ddr_divider, 0x0f, Clock_divider_ddr));
1.259
1.260 Clock clock_dma(1, Clock_inputs(Clock_pclock),
1.261 - Reg_undefined, Clock_source_undefined,
1.262 - Clock_gate0, Clock_gate_dma);
1.263 + Source_undefined,
1.264 + Field(Clock_gate0, 1, Clock_gate_dma));
1.265
1.266 Clock clock_emac;
1.267
1.268 Clock clock_external;
1.269
1.270 Clock clock_hclock0(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M),
1.271 - Clock_control, Clock_source_hclock0,
1.272 - Clock_gate0, Clock_gate_ahb0,
1.273 - Clock_control, Clock_change_enable_ahb0,
1.274 - Reg_undefined, Clock_busy_undefined,
1.275 - Clock_control, Clock_divider_hclock0, 0x0f);
1.276 + Field(Clock_control, 3, Clock_source_hclock0),
1.277 + Field(Clock_gate0, 1, Clock_gate_ahb0),
1.278 + Field(Clock_control, 1, Clock_change_enable_ahb0),
1.279 + Busy_undefined,
1.280 + Field(Clock_control, 0x0f, Clock_divider_hclock0));
1.281
1.282 Clock clock_hclock2(1, Clock_inputs(Clock_ahb2_apb),
1.283 - Reg_undefined, Clock_source_undefined,
1.284 - Clock_gate0, Clock_gate_apb0,
1.285 - Clock_control, Clock_change_enable_ahb2,
1.286 - Reg_undefined, Clock_busy_undefined,
1.287 - Clock_control, Clock_divider_hclock2, 0x0f);
1.288 + Source_undefined,
1.289 + Field(Clock_gate0, 1, Clock_gate_apb0),
1.290 + Field(Clock_control, 1, Clock_change_enable_ahb2),
1.291 + Busy_undefined,
1.292 + Field(Clock_control, 0x0f, Clock_divider_hclock2));
1.293
1.294 Clock clock_hdmi;
1.295
1.296 Clock clock_i2c(1, Clock_inputs(Clock_pclock),
1.297 - Reg_undefined, Clock_source_undefined,
1.298 - Clock_gate0, Clock_gate_i2c0);
1.299 + Source_undefined,
1.300 + Field(Clock_gate0, 1, Clock_gate_i2c0));
1.301
1.302 Clock clock_i2c0(1, Clock_inputs(Clock_pclock),
1.303 - Reg_undefined, Clock_source_undefined,
1.304 - Clock_gate0, Clock_gate_i2c0);
1.305 + Source_undefined,
1.306 + Field(Clock_gate0, 1, Clock_gate_i2c0));
1.307
1.308 Clock clock_i2c1(1, Clock_inputs(Clock_pclock),
1.309 - Reg_undefined, Clock_source_undefined,
1.310 - Clock_gate0, Clock_gate_i2c1);
1.311 + Source_undefined,
1.312 + Field(Clock_gate0, 1, Clock_gate_i2c1));
1.313
1.314 Clock clock_i2s;
1.315
1.316 Clock clock_i2s0_rx(2, Clock_inputs(Clock_main, Clock_pll_E),
1.317 - I2s_divider0, Clock_source_i2s,
1.318 - Clock_gate1, Clock_gate_i2s0_rx,
1.319 - I2s_divider0, Clock_change_enable_i2s);
1.320 + Field(I2s_divider0, 1, Clock_source_i2s),
1.321 + Field(Clock_gate1, 1, Clock_gate_i2s0_rx),
1.322 + Field(I2s_divider0, 1, Clock_change_enable_i2s));
1.323
1.324 Clock clock_i2s0_tx(2, Clock_inputs(Clock_main, Clock_pll_E),
1.325 - I2s_divider0, Clock_source_i2s,
1.326 - Clock_gate1, Clock_gate_i2s0_tx,
1.327 - I2s_divider0, Clock_change_enable_i2s);
1.328 + Field(I2s_divider0, 1, Clock_source_i2s),
1.329 + Field(Clock_gate1, 1, Clock_gate_i2s0_tx),
1.330 + Field(I2s_divider0, 1, Clock_change_enable_i2s));
1.331
1.332 Clock clock_kbc;
1.333
1.334 Clock clock_lcd;
1.335
1.336 Clock clock_lcd_pixel(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.337 - Lcd_divider, Clock_source_lcd,
1.338 - Clock_gate0, Clock_gate_lcd_pixel,
1.339 - Lcd_divider, Clock_change_enable_lcd,
1.340 - Lcd_divider, Clock_busy_lcd,
1.341 - Lcd_divider, Clock_divider_lcd, 0xff);
1.342 + Field(Lcd_divider, 3, Clock_source_lcd),
1.343 + Field(Clock_gate0, 1, Clock_gate_lcd_pixel),
1.344 + Field(Lcd_divider, 1, Clock_change_enable_lcd),
1.345 + Field(Lcd_divider, 1, Clock_busy_lcd),
1.346 + Field(Lcd_divider, 0xff, Clock_divider_lcd));
1.347
1.348 Clock clock_mac(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.349 - Mac_divider, Clock_source_mac,
1.350 - Clock_gate1, Clock_gate_gmac0,
1.351 - Mac_divider, Clock_change_enable_mac,
1.352 - Mac_divider, Clock_busy_mac,
1.353 - Mac_divider, Clock_divider_mac, 0xff);
1.354 + Field(Mac_divider, 3, Clock_source_mac),
1.355 + Field(Clock_gate1, 1, Clock_gate_gmac0),
1.356 + Field(Mac_divider, 1, Clock_change_enable_mac),
1.357 + Field(Mac_divider, 1, Clock_busy_mac),
1.358 + Field(Mac_divider, 0xff, Clock_divider_mac));
1.359
1.360 Clock clock_main(3, Clock_inputs(Clock_none, Clock_external, Clock_pll_A),
1.361 - Clock_control, Clock_source_main,
1.362 - Clock_control, Clock_gate_main);
1.363 + Field(Clock_control, 3, Clock_source_main),
1.364 + Field(Clock_control, 1, Clock_gate_main));
1.365
1.366 Clock clock_msc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.367 - Msc_divider0, Clock_source_msc0,
1.368 - Clock_gate0, Clock_gate_msc0,
1.369 - Msc_divider0, Clock_change_enable_msc0,
1.370 - Msc_divider0, Clock_busy_msc0,
1.371 - Msc_divider0, Clock_divider_msc0, 0xff);
1.372 + Field(Msc_divider0, 3, Clock_source_msc0),
1.373 + Field(Clock_gate0, 1, Clock_gate_msc0),
1.374 + Field(Msc_divider0, 1, Clock_change_enable_msc0),
1.375 + Field(Msc_divider0, 1, Clock_busy_msc0),
1.376 + Field(Msc_divider0, 0xff, Clock_divider_msc0));
1.377
1.378 Clock clock_msc0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.379 - Msc_divider0, Clock_source_msc0,
1.380 - Clock_gate0, Clock_gate_msc0,
1.381 - Msc_divider0, Clock_change_enable_msc0,
1.382 - Msc_divider0, Clock_busy_msc0,
1.383 - Msc_divider0, Clock_divider_msc0, 0xff);
1.384 + Field(Msc_divider0, 3, Clock_source_msc0),
1.385 + Field(Clock_gate0, 1, Clock_gate_msc0),
1.386 + Field(Msc_divider0, 1, Clock_change_enable_msc0),
1.387 + Field(Msc_divider0, 1, Clock_busy_msc0),
1.388 + Field(Msc_divider0, 0xff, Clock_divider_msc0));
1.389
1.390 Clock clock_msc1(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.391 - Msc_divider1, Clock_source_msc1,
1.392 - Clock_gate0, Clock_gate_msc1,
1.393 - Msc_divider1, Clock_change_enable_msc1,
1.394 - Msc_divider1, Clock_busy_msc1,
1.395 - Msc_divider1, Clock_divider_msc1, 0xff);
1.396 + Field(Msc_divider1, 3, Clock_source_msc1),
1.397 + Field(Clock_gate0, 1, Clock_gate_msc1),
1.398 + Field(Msc_divider1, 1, Clock_change_enable_msc1),
1.399 + Field(Msc_divider1, 1, Clock_busy_msc1),
1.400 + Field(Msc_divider1, 0xff, Clock_divider_msc1));
1.401
1.402 Clock clock_none;
1.403
1.404 Clock clock_pclock(1, Clock_inputs(Clock_ahb2_apb),
1.405 - Reg_undefined, Clock_source_undefined,
1.406 - Clock_gate0, Clock_gate_apb0,
1.407 - Reg_undefined, Clock_change_enable_undefined,
1.408 - Reg_undefined, Clock_busy_undefined,
1.409 - Clock_control, Clock_divider_pclock, 0x0f);
1.410 + Source_undefined,
1.411 + Field(Clock_gate0, 1, Clock_gate_apb0),
1.412 + Change_enable_undefined,
1.413 + Busy_undefined,
1.414 + Field(Clock_control, 0x0f, Clock_divider_pclock));
1.415
1.416 Pll clock_pll_A(1, Clock_inputs(Clock_external),
1.417 Pll_control_A, Pll_bypass_A);
1.418 @@ -583,29 +569,29 @@
1.419 Pll_control_M, Pll_bypass_M);
1.420
1.421 Clock clock_pwm(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.422 - Pwm_divider, Clock_source_pwm,
1.423 - Clock_gate1, Clock_gate_pwm,
1.424 - Pwm_divider, Clock_change_enable_pwm,
1.425 - Pwm_divider, Clock_busy_pwm,
1.426 - Pwm_divider, Clock_divider_pwm, 0x0f);
1.427 + Field(Pwm_divider, 3, Clock_source_pwm),
1.428 + Field(Clock_gate1, 1, Clock_gate_pwm),
1.429 + Field(Pwm_divider, 1, Clock_change_enable_pwm),
1.430 + Field(Pwm_divider, 1, Clock_busy_pwm),
1.431 + Field(Pwm_divider, 0x0f, Clock_divider_pwm));
1.432
1.433 Clock clock_pwm0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.434 - Pwm_divider, Clock_source_pwm,
1.435 - Clock_gate1, Clock_gate_pwm,
1.436 - Pwm_divider, Clock_change_enable_pwm,
1.437 - Pwm_divider, Clock_busy_pwm,
1.438 - Pwm_divider, Clock_divider_pwm, 0x0f);
1.439 + Field(Pwm_divider, 3, Clock_source_pwm),
1.440 + Field(Clock_gate1, 1, Clock_gate_pwm),
1.441 + Field(Pwm_divider, 1, Clock_change_enable_pwm),
1.442 + Field(Pwm_divider, 1, Clock_busy_pwm),
1.443 + Field(Pwm_divider, 0x0f, Clock_divider_pwm));
1.444
1.445 Clock clock_pwm1;
1.446
1.447 Clock clock_scc;
1.448
1.449 Clock clock_sfc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.450 - Sfc_divider, Clock_source_sfc,
1.451 - Clock_gate0, Clock_gate_sfc,
1.452 - Sfc_divider, Clock_change_enable_sfc,
1.453 - Sfc_divider, Clock_busy_sfc,
1.454 - Sfc_divider, Clock_divider_sfc, 0xff);
1.455 + Field(Sfc_divider, 3, Clock_source_sfc),
1.456 + Field(Clock_gate0, 1, Clock_gate_sfc),
1.457 + Field(Sfc_divider, 1, Clock_change_enable_sfc),
1.458 + Field(Sfc_divider, 1, Clock_busy_sfc),
1.459 + Field(Sfc_divider, 0xff, Clock_divider_sfc));
1.460
1.461 Clock clock_smb0;
1.462
1.463 @@ -618,31 +604,31 @@
1.464 Clock clock_smb4;
1.465
1.466 Clock clock_ssi(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E),
1.467 - Ssi_divider, Clock_source_ssi,
1.468 - Clock_gate0, Clock_gate_ssi0,
1.469 - Ssi_divider, Clock_change_enable_ssi,
1.470 - Ssi_divider, Clock_busy_ssi,
1.471 - Ssi_divider, Clock_divider_ssi, 0xff);
1.472 + Field(Ssi_divider, 3, Clock_source_ssi),
1.473 + Field(Clock_gate0, 1, Clock_gate_ssi0),
1.474 + Field(Ssi_divider, 1, Clock_change_enable_ssi),
1.475 + Field(Ssi_divider, 1, Clock_busy_ssi),
1.476 + Field(Ssi_divider, 0xff, Clock_divider_ssi));
1.477
1.478 Clock clock_timer(1, Clock_inputs(Clock_pclock),
1.479 - Reg_undefined, Clock_source_undefined,
1.480 - Clock_gate0, Clock_gate_timer);
1.481 + Source_undefined,
1.482 + Field(Clock_gate0, 1, Clock_gate_timer));
1.483
1.484 Clock clock_uart0(1, Clock_inputs(Clock_external),
1.485 - Reg_undefined, Clock_source_undefined,
1.486 - Clock_gate0, Clock_gate_uart0);
1.487 + Source_undefined,
1.488 + Field(Clock_gate0, 1, Clock_gate_uart0));
1.489
1.490 Clock clock_uart1(1, Clock_inputs(Clock_external),
1.491 - Reg_undefined, Clock_source_undefined,
1.492 - Clock_gate0, Clock_gate_uart1);
1.493 + Source_undefined,
1.494 + Field(Clock_gate0, 1, Clock_gate_uart1));
1.495
1.496 Clock clock_uart2(1, Clock_inputs(Clock_external),
1.497 - Reg_undefined, Clock_source_undefined,
1.498 - Clock_gate0, Clock_gate_uart2);
1.499 + Source_undefined,
1.500 + Field(Clock_gate0, 1, Clock_gate_uart2));
1.501
1.502 Clock clock_uart3(1, Clock_inputs(Clock_external),
1.503 - Reg_undefined, Clock_source_undefined,
1.504 - Clock_gate1, Clock_gate_uart3);
1.505 + Source_undefined,
1.506 + Field(Clock_gate1, 1, Clock_gate_uart3));
1.507
1.508 Clock clock_udc;
1.509
1.510 @@ -736,6 +722,26 @@
1.511
1.512
1.513
1.514 +// Field methods.
1.515 +
1.516 +uint32_t
1.517 +Field::get_field(Cpm_regs ®s)
1.518 +{
1.519 + if (defined)
1.520 + return regs.get_field(reg, mask, bit);
1.521 + else
1.522 + return 0;
1.523 +}
1.524 +
1.525 +void
1.526 +Field::set_field(Cpm_regs ®s, uint32_t value)
1.527 +{
1.528 + if (defined)
1.529 + regs.set_field(reg, mask, bit, value);
1.530 +}
1.531 +
1.532 +
1.533 +
1.534 // Clock control.
1.535
1.536 int
1.537 @@ -778,8 +784,8 @@
1.538 uint8_t
1.539 Clock_base::get_source(Cpm_regs ®s)
1.540 {
1.541 - if (source_bit != Clock_source_undefined)
1.542 - return regs.get_field(source_reg, Source_mask, source_bit);
1.543 + if (_source.is_defined())
1.544 + return _source.get_field(regs);
1.545 else
1.546 return 0;
1.547 }
1.548 @@ -787,10 +793,10 @@
1.549 void
1.550 Clock_base::set_source(Cpm_regs ®s, uint8_t source)
1.551 {
1.552 - if (source_bit == Clock_source_undefined)
1.553 + if (_source.is_defined())
1.554 return;
1.555
1.556 - regs.set_field(source_reg, Source_mask, source_bit, source);
1.557 + _source.set_field(regs, source);
1.558 }
1.559
1.560 // Clock source frequencies.
1.561 @@ -959,22 +965,22 @@
1.562 void
1.563 Clock::change_disable(Cpm_regs ®s)
1.564 {
1.565 - if (change_enable_bit != Clock_change_enable_undefined)
1.566 - regs.set_field(change_enable_reg, 1, change_enable_bit, 0);
1.567 + if (_change_enable.is_defined())
1.568 + _change_enable.set_field(regs, 0);
1.569 }
1.570
1.571 void
1.572 Clock::change_enable(Cpm_regs ®s)
1.573 {
1.574 - if (change_enable_bit != Clock_change_enable_undefined)
1.575 - regs.set_field(change_enable_reg, 1, change_enable_bit, 1);
1.576 + if (_change_enable.is_defined())
1.577 + _change_enable.set_field(regs, 1);
1.578 }
1.579
1.580 int
1.581 Clock::have_clock(Cpm_regs ®s)
1.582 {
1.583 - if (gate_bit != Clock_gate_undefined)
1.584 - return !regs.get_field(gate_reg, 1, gate_bit);
1.585 + if (_gate.is_defined())
1.586 + return !_gate.get_field(regs);
1.587 else
1.588 return true;
1.589 }
1.590 @@ -982,22 +988,22 @@
1.591 void
1.592 Clock::start_clock(Cpm_regs ®s)
1.593 {
1.594 - if (gate_bit != Clock_gate_undefined)
1.595 - regs.set_field(gate_reg, 1, gate_bit, 0);
1.596 + if (_gate.is_defined())
1.597 + _gate.set_field(regs, 0);
1.598 }
1.599
1.600 void
1.601 Clock::stop_clock(Cpm_regs ®s)
1.602 {
1.603 - if (gate_bit != Clock_gate_undefined)
1.604 - regs.set_field(gate_reg, 1, gate_bit, 1);
1.605 + if (_gate.is_defined())
1.606 + _gate.set_field(regs, 1);
1.607 }
1.608
1.609 void
1.610 Clock::wait_busy(Cpm_regs ®s)
1.611 {
1.612 - if (busy_bit != Clock_busy_undefined)
1.613 - while (regs.get_field(busy_reg, 1, busy_bit));
1.614 + if (_busy.is_defined())
1.615 + while (_busy.get_field(regs));
1.616 }
1.617
1.618
1.619 @@ -1007,8 +1013,8 @@
1.620 uint32_t
1.621 Clock::get_divider(Cpm_regs ®s)
1.622 {
1.623 - if (divider_bit != Clock_divider_undefined)
1.624 - return regs.get_field(divider_reg, divider_mask, divider_bit) + 1;
1.625 + if (_divider.is_defined())
1.626 + return _divider.get_field(regs) + 1;
1.627 else
1.628 return 1;
1.629 }
1.630 @@ -1016,11 +1022,11 @@
1.631 void
1.632 Clock::set_divider(Cpm_regs ®s, uint32_t division)
1.633 {
1.634 - if (divider_bit == Clock_divider_undefined)
1.635 + if (_divider.is_defined())
1.636 return;
1.637
1.638 change_enable(regs);
1.639 - regs.set_field(divider_reg, divider_mask, divider_bit, division - 1);
1.640 + _divider.set_field(regs, division - 1);
1.641 wait_busy(regs);
1.642 change_disable(regs);
1.643 }