1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Mon Sep 18 16:40:15 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Wed Sep 20 00:37:57 2023 +0200
1.3 @@ -98,7 +98,7 @@
1.4 Clock_source_cdbus (Divider_cdbus, 3, 30), // CDCS
1.5 Clock_source_cim (Divider_cim, 3, 30), // CIMPCS
1.6 Clock_source_ddr (Divider_ddr, 3, 30), // DCS
1.7 - Clock_source_i2s (Divider0_i2s0, 1, 31), // I2PCS
1.8 + Clock_source_i2s (Divider0_i2s0, 1, 30), // I2PCS
1.9 Clock_source_lcd (Divider_lcd, 3, 30), // LPCS
1.10 Clock_source_mac (Divider_mac, 3, 30), // MACPCS
1.11 Clock_source_msc0 (Divider_msc0, 3, 30), // MPCS
1.12 @@ -126,7 +126,7 @@
1.13 Clock_change_enable_ahb2 (Clock_control, 1, 20),
1.14 Clock_change_enable_ddr (Divider_ddr, 1, 29),
1.15 Clock_change_enable_mac (Divider_mac, 1, 29),
1.16 - Clock_change_enable_i2s (Divider0_i2s0, 1, 29),
1.17 + // Clock_change_enable_i2s (Divider0_i2s0, 1, 29), // CE_I2S may not be change enable
1.18 Clock_change_enable_lcd (Divider_lcd, 1, 29),
1.19 Clock_change_enable_msc0 (Divider_msc0, 1, 29),
1.20 Clock_change_enable_msc1 (Divider_msc1, 1, 29),
1.21 @@ -162,6 +162,11 @@
1.22 Clock_divider_sfc (Divider_sfc, 0xff, 0), // SFCCDR
1.23 Clock_divider_ssi (Divider_ssi, 0xff, 0), // SSICDR
1.24
1.25 + Clock_divider_i2s0_n_auto (Divider1_i2s0, 1, 31), // I2S_NEN
1.26 + Clock_divider_i2s0_d_auto (Divider1_i2s0, 1, 30), // I2S_DEN
1.27 + Clock_divider_i2s1_n_auto (Divider1_i2s1, 1, 31), // I2S_NEN
1.28 + Clock_divider_i2s1_d_auto (Divider1_i2s1, 1, 30), // I2S_DEN
1.29 +
1.30 Clock_gate_main (Clock_control, 1, 23), // GATE_SCLKA
1.31 Clock_gate_ddr (Clock_gate0, 1, 31), // DDR
1.32 Clock_gate_ahb0 (Clock_gate0, 1, 29), // AHB0
1.33 @@ -237,8 +242,9 @@
1.34 #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__})
1.35
1.36 static Mux mux_external (Clock_external),
1.37 + mux_hclock0 (Clock_hclock0),
1.38 + mux_hclock2 (Clock_hclock2),
1.39 mux_pclock (Clock_pclock),
1.40 - mux_ahb2_apb (Clock_ahb2_apb),
1.41 mux_core (3, Clocks(Clock_none, Clock_main, Clock_pll_M)),
1.42 mux_bus (4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external)),
1.43 mux_dev (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)),
1.44 @@ -255,9 +261,7 @@
1.45 // Note the use of extra parentheses due to the annoying C++ "most vexing parse"
1.46 // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse
1.47
1.48 -static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)),
1.49 -
1.50 - clock_dma((Source(mux_pclock)), (Control(Clock_gate_dma))),
1.51 +static Clock clock_dma((Source(mux_hclock2)), (Control(Clock_gate_dma))),
1.52
1.53 clock_i2c((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
1.54
1.55 @@ -267,6 +271,10 @@
1.56
1.57 clock_main(Source(mux_core, Clock_source_main), Control(Clock_gate_main)),
1.58
1.59 + clock_mipi_csi((Source(mux_hclock0)), Control(Clock_gate_mipi_csi)),
1.60 +
1.61 + clock_otg((Source(mux_hclock2)), (Control(Clock_gate_otg))),
1.62 +
1.63 clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))),
1.64
1.65 clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))),
1.66 @@ -306,7 +314,7 @@
1.67 Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
1.68 Divider(Clock_divider_hclock0)),
1.69
1.70 - clock_hclock2(Source(mux_ahb2_apb),
1.71 + clock_hclock2(Source(mux_core, Clock_source_hclock2),
1.72 Control(Clock_gate_apb0, Clock_change_enable_ahb2),
1.73 Divider(Clock_divider_hclock2)),
1.74
1.75 @@ -330,9 +338,9 @@
1.76 Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
1.77 Divider(Clock_divider_msc1)),
1.78
1.79 - clock_pclock((Source(mux_ahb2_apb)),
1.80 - (Control(Clock_gate_apb0)),
1.81 - (Divider(Clock_divider_pclock))),
1.82 + clock_pclock(Source(mux_core, Clock_source_hclock2),
1.83 + Control(Clock_gate_apb0, Clock_change_enable_ahb2),
1.84 + Divider(Clock_divider_pclock)),
1.85
1.86 clock_pwm(Source(mux_dev, Clock_source_pwm),
1.87 Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.88 @@ -352,14 +360,16 @@
1.89
1.90 static Clock_divided_i2s
1.91 clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
1.92 - Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s),
1.93 + Control(Clock_gate_i2s0_rx),
1.94 Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
1.95 - Clock_divider_i2s0_d)),
1.96 + Clock_divider_i2s0_d, Clock_divider_i2s0_n_auto,
1.97 + Clock_divider_i2s0_d_auto)),
1.98
1.99 clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s),
1.100 - Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s),
1.101 + Control(Clock_gate_i2s0_tx),
1.102 Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
1.103 - Clock_divider_i2s1_d));
1.104 + Clock_divider_i2s1_d, Clock_divider_i2s1_n_auto,
1.105 + Clock_divider_i2s1_d_auto));
1.106
1.107 static Pll clock_pll_A(Source(mux_external),
1.108 Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
1.109 @@ -381,7 +391,6 @@
1.110 // Clock register.
1.111
1.112 static Clock_base *clocks[Clock_identifier_count] = {
1.113 - &clock_ahb2_apb,
1.114 &clock_none, // Clock_aic_bitclk
1.115 &clock_none, // Clock_aic_pclk
1.116 &clock_can0,
1.117 @@ -407,10 +416,12 @@
1.118 &clock_lcd_pixel,
1.119 &clock_mac,
1.120 &clock_main,
1.121 + &clock_mipi_csi,
1.122 &clock_msc,
1.123 &clock_msc0,
1.124 &clock_msc1,
1.125 &clock_none,
1.126 + &clock_otg,
1.127 &clock_pclock,
1.128 &clock_pll_A,
1.129 &clock_pll_E,
1.130 @@ -485,13 +496,15 @@
1.131 return 0;
1.132 }
1.133
1.134 -void
1.135 -Cpm_x1600_chip::set_parameters(enum Clock_identifiers clock, uint32_t parameters[])
1.136 +int
1.137 +Cpm_x1600_chip::set_parameters(enum Clock_identifiers clock, int num_parameters, uint32_t parameters[])
1.138 {
1.139 Clock_divided_base *clk = dynamic_cast<Clock_divided_base *>(clocks[clock]);
1.140
1.141 if (clk != NULL)
1.142 - clk->set_parameters(_cpm_regs, parameters);
1.143 + return clk->set_parameters(_cpm_regs, num_parameters, parameters);
1.144 + else
1.145 + return 0;
1.146 }
1.147
1.148 uint8_t
1.149 @@ -505,6 +518,26 @@
1.150 return 0;
1.151 }
1.152
1.153 +enum Clock_identifiers
1.154 +Cpm_x1600_chip::get_source_clock(enum Clock_identifiers clock)
1.155 +{
1.156 + Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]);
1.157 +
1.158 + if (clk != NULL)
1.159 + return clk->get_source_clock(_cpm_regs);
1.160 + else
1.161 + return Clock_undefined;
1.162 +}
1.163 +
1.164 +void
1.165 +Cpm_x1600_chip::set_source_clock(enum Clock_identifiers clock, enum Clock_identifiers source)
1.166 +{
1.167 + Clock_active *clk = dynamic_cast<Clock_active *>(clocks[clock]);
1.168 +
1.169 + if (clk != NULL)
1.170 + clk->set_source_clock(_cpm_regs, source);
1.171 +}
1.172 +
1.173 void
1.174 Cpm_x1600_chip::set_source(enum Clock_identifiers clock, uint8_t source)
1.175 {
1.176 @@ -553,7 +586,7 @@
1.177
1.178 lcd->set_source(_cpm_regs, Source_mME_pll_M);
1.179 pll->start_clock(_cpm_regs);
1.180 - lcd->set_parameters(_cpm_regs, parameters);
1.181 + lcd->set_parameters(_cpm_regs, 1, parameters);
1.182 }
1.183 break;
1.184 }
1.185 @@ -606,10 +639,10 @@
1.186 return static_cast<Cpm_x1600_chip *>(cpm)->get_parameters(clock, parameters);
1.187 }
1.188
1.189 -void
1.190 -x1600_cpm_set_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[])
1.191 +int
1.192 +x1600_cpm_set_parameters(void *cpm, enum Clock_identifiers clock, int num_parameters, uint32_t parameters[])
1.193 {
1.194 - return static_cast<Cpm_x1600_chip *>(cpm)->set_parameters(clock, parameters);
1.195 + return static_cast<Cpm_x1600_chip *>(cpm)->set_parameters(clock, num_parameters, parameters);
1.196 }
1.197
1.198 uint8_t
1.199 @@ -624,6 +657,18 @@
1.200 static_cast<Cpm_x1600_chip *>(cpm)->set_source(clock, source);
1.201 }
1.202
1.203 +enum Clock_identifiers
1.204 +x1600_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock)
1.205 +{
1.206 + return static_cast<Cpm_x1600_chip *>(cpm)->get_source_clock(clock);
1.207 +}
1.208 +
1.209 +void
1.210 +x1600_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source)
1.211 +{
1.212 + static_cast<Cpm_x1600_chip *>(cpm)->set_source_clock(clock, source);
1.213 +}
1.214 +
1.215 uint32_t
1.216 x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock)
1.217 {