1.1 --- a/pkg/devices/lib/dma/src/jz4730.cc Wed Apr 24 00:47:34 2024 +0200
1.2 +++ b/pkg/devices/lib/dma/src/jz4730.cc Sat Apr 27 23:46:28 2024 +0200
1.3 @@ -19,6 +19,7 @@
1.4 * Boston, MA 02110-1301, USA
1.5 */
1.6
1.7 +#include <l4/devices/cpm-jz4730.h>
1.8 #include <l4/devices/dma-jz4730.h>
1.9 #include <l4/devices/hw_mmio_register_block.h>
1.10
1.11 @@ -134,7 +135,7 @@
1.12
1.13 // Initialise a channel.
1.14
1.15 -Dma_jz4730_channel::Dma_jz4730_channel(Dma_jz4730_chip *chip, uint8_t channel,
1.16 +Dma_jz4730_channel::Dma_jz4730_channel(Dma_chip *chip, uint8_t channel,
1.17 l4_addr_t start, l4_cap_idx_t irq)
1.18 : _chip(chip), _channel(channel), _irq(irq)
1.19 {
1.20 @@ -239,8 +240,14 @@
1.21 bool source_increment, bool destination_increment,
1.22 uint8_t source_width, uint8_t destination_width,
1.23 uint8_t transfer_unit_size,
1.24 - enum Dma_jz4730_request_type type)
1.25 + int type,
1.26 + l4_addr_t desc_vaddr,
1.27 + l4re_dma_space_dma_addr_t desc_paddr)
1.28 {
1.29 + // Descriptor-based transfers are not supported.
1.30 +
1.31 + (void) desc_vaddr; (void) desc_paddr;
1.32 +
1.33 // Ensure an absence of address error and halt conditions globally and in this channel.
1.34
1.35 if (error() || halted())
1.36 @@ -281,7 +288,7 @@
1.37 * transfer mode (currently left as single)
1.38 */
1.39
1.40 - _regs[Dma_control_status] = encode_external_transfer(type) |
1.41 + _regs[Dma_control_status] = encode_external_transfer((enum Dma_jz4730_request_type) type) |
1.42 (source_increment ? Dma_source_address_incr : Dma_source_address_no_incr) |
1.43 (destination_increment ? Dma_dest_address_incr : Dma_dest_address_no_incr) |
1.44 encode_source_port_width(source_width) |
1.45 @@ -393,7 +400,7 @@
1.46 // Initialise the I2C controller.
1.47
1.48 Dma_jz4730_chip::Dma_jz4730_chip(l4_addr_t start, l4_addr_t end,
1.49 - Cpm_jz4730_chip *cpm)
1.50 + Cpm_chip *cpm)
1.51 : _start(start), _end(end), _cpm(cpm)
1.52 {
1.53 _regs = new Hw::Mmio_register_block<32>(start);
1.54 @@ -426,7 +433,7 @@
1.55
1.56 // Obtain a channel object.
1.57
1.58 -Dma_jz4730_channel *
1.59 +Dma_channel *
1.60 Dma_jz4730_chip::get_channel(uint8_t channel, l4_cap_idx_t irq)
1.61 {
1.62 if (channel < 6)
1.63 @@ -443,28 +450,33 @@
1.64 return _regs[Dma_irq_pending] & (1 << (Dma_irq_pending_ch0 - channel)) ? true : false;
1.65 }
1.66
1.67 +Dma_chip *jz4730_dma_chip(l4_addr_t start, l4_addr_t end, Cpm_chip *cpm)
1.68 +{
1.69 + return new Dma_jz4730_chip(start, end, cpm);
1.70 +}
1.71 +
1.72
1.73
1.74 // C language interface functions.
1.75
1.76 void *jz4730_dma_init(l4_addr_t start, l4_addr_t end, void *cpm)
1.77 {
1.78 - return (void *) new Dma_jz4730_chip(start, end, static_cast<Cpm_jz4730_chip *>(cpm));
1.79 + return (void *) jz4730_dma_chip(start, end, static_cast<Cpm_chip *>(cpm));
1.80 }
1.81
1.82 void jz4730_dma_disable(void *dma_chip)
1.83 {
1.84 - static_cast<Dma_jz4730_chip *>(dma_chip)->disable();
1.85 + static_cast<Dma_chip *>(dma_chip)->disable();
1.86 }
1.87
1.88 void jz4730_dma_enable(void *dma_chip)
1.89 {
1.90 - static_cast<Dma_jz4730_chip *>(dma_chip)->enable();
1.91 + static_cast<Dma_chip *>(dma_chip)->enable();
1.92 }
1.93
1.94 void *jz4730_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq)
1.95 {
1.96 - return static_cast<Dma_jz4730_chip *>(dma)->get_channel(channel, irq);
1.97 + return static_cast<Dma_chip *>(dma)->get_channel(channel, irq);
1.98 }
1.99
1.100 void jz4730_dma_set_output_polarity(void *dma_channel, enum Dma_jz4730_ext_level polarity)