1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/pkg/devices/lib/i2c/src/x1600.cc Tue Sep 26 21:27:50 2023 +0200
1.3 @@ -0,0 +1,803 @@
1.4 +/*
1.5 + * I2C support for the X1600.
1.6 + *
1.7 + * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software; you can redistribute it and/or
1.10 + * modify it under the terms of the GNU General Public License as
1.11 + * published by the Free Software Foundation; either version 2 of
1.12 + * the License, or (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program; if not, write to the Free Software
1.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.22 + * Boston, MA 02110-1301, USA
1.23 + */
1.24 +
1.25 +#include <l4/devices/i2c-x1600.h>
1.26 +#include <l4/devices/hw_mmio_register_block.h>
1.27 +
1.28 +#include <l4/sys/icu.h>
1.29 +#include <l4/util/util.h>
1.30 +#include <sys/time.h>
1.31 +
1.32 +#include <stdio.h>
1.33 +
1.34 +/* NOTE: This peripheral is very similar to the JZ4780 with the registers
1.35 + renamed to I2C from I2C, with a few high speed registers added, and
1.36 + with I2C_SDAHD appearing at a different location. */
1.37 +
1.38 +enum Regs
1.39 +{
1.40 + I2c_control = 0x000, // I2C_CON
1.41 + I2c_target_address = 0x004, // I2C_TAR
1.42 + I2c_slave_address = 0x008, // I2C_SAR
1.43 + I2c_master_code = 0x00c, // I2C_HS_MADDR
1.44 + I2c_data_command = 0x010, // I2C_DC
1.45 + Std_high_count = 0x014, // I2C_SHCNT
1.46 + Std_low_count = 0x018, // I2C_SLCNT
1.47 + Fast_high_count = 0x01c, // I2C_FHCNT
1.48 + Fast_low_count = 0x020, // I2C_FLCNT
1.49 + High_high_count = 0x024, // I2C_HHCNT
1.50 + High_low_count = 0x028, // I2C_HLCNT
1.51 + Int_status = 0x02c, // I2C_INTST (read-only)
1.52 + Int_mask = 0x030, // I2C_INTM
1.53 + Int_raw_status = 0x034, // I2C_RINTST (read-only)
1.54 + Rx_fifo_thold = 0x038, // I2C_RXTL
1.55 + Tx_fifo_thold = 0x03c, // I2C_TXTL
1.56 + Int_combined_clear = 0x040, // I2C_CINT (read-only)
1.57 + Int_rx_uf_clear = 0x044, // I2C_CRXUF (read-only)
1.58 + Int_rx_of_clear = 0x048, // I2C_CRXOF (read-only)
1.59 + Int_tx_of_clear = 0x04c, // I2C_CTXOF (read-only)
1.60 + Int_rd_req_clear = 0x050, // I2C_CRXREQ (read-only)
1.61 + Int_tx_abort_clear = 0x054, // I2C_CTXABT (read-only)
1.62 + Int_rx_done_clear = 0x058, // I2C_CRXDN (read-only)
1.63 + Int_activity_clear = 0x05c, // I2C_CACT (read-only)
1.64 + Int_stop_clear = 0x060, // I2C_CSTP (read-only)
1.65 + Int_start_clear = 0x064, // I2C_CSTT (read-only)
1.66 + Int_call_clear = 0x068, // I2C_CGC (read-only)
1.67 + I2c_enable = 0x06c, // I2C_ENB
1.68 + I2c_status = 0x070, // I2C_ST (read-only)
1.69 + Tx_fifo_count = 0x074, // I2C_TXFLR (read-only)
1.70 + Rx_fifo_count = 0x078, // I2C_RXFLR (read-only)
1.71 + I2c_sda_hold_time = 0x07c, // I2C_SDAHD
1.72 + Trans_abort_status = 0x080, // I2C_ABTSRC (read-only)
1.73 + Slv_data_nack = 0x084, // I2CSDNACK
1.74 + I2c_dma_ctrl = 0x088, // I2C_DMACR
1.75 + I2c_trans_data_lvl = 0x08c, // I2C_DMATDLR
1.76 + I2c_recv_data_lvl = 0x090, // I2C_DMARDLR
1.77 + I2c_sda_setup_time = 0x094, // I2C_SDASU
1.78 + I2c_ack_call = 0x098, // I2C_ACKGC
1.79 + I2c_enable_status = 0x09c, // I2C_ENBST (read-only)
1.80 + I2c_spike_suppress = 0x0a0, // I2C_FSPKLEN
1.81 +
1.82 + I2c_block_offset = 0x1000
1.83 +};
1.84 +
1.85 +enum I2c_control_bits : unsigned
1.86 +{
1.87 + I2c_disable_slave = 0x40, // SLVDIS (slave disabled)
1.88 + I2c_enable_restart = 0x20, // RESTART
1.89 + I2c_master_10bit = 0x10, // MATP (read-only)
1.90 + I2c_slave_10bit = 0x08, // SATP
1.91 + I2c_speed_mode_mask = 0x06, // SPEED
1.92 + I2c_enable_master = 0x01, // MD (master enabled)
1.93 + I2c_speed_bit = 1, // SPD
1.94 +};
1.95 +
1.96 +enum I2c_speed_mode_values : unsigned
1.97 +{
1.98 + I2c_speed_standard = 1,
1.99 + I2c_speed_fast = 2,
1.100 + I2c_speed_high = 3,
1.101 +};
1.102 +
1.103 +enum I2c_enable_bits : unsigned
1.104 +{
1.105 + I2c_enable_enabled = 0x01, // I2CEN
1.106 +};
1.107 +
1.108 +enum I2c_status_bits : unsigned
1.109 +{
1.110 + I2c_status_master_act = 0x20, // MSTACT (master active)
1.111 + I2c_status_rx_nempty = 0x08, // RFNE (read queue not empty)
1.112 + I2c_status_tx_empty = 0x04, // TFE (write queue empty)
1.113 + I2c_status_tx_nfull = 0x02, // TFNF (write queue not full)
1.114 + I2c_status_active = 0x01, // ACT (device active as master or slave)
1.115 +};
1.116 +
1.117 +enum I2c_target_bits : unsigned
1.118 +{
1.119 + I2c_target_master_10bit = 0x1000,
1.120 + I2c_target_special = 0x0800, // SPECIAL: perform general call or start byte
1.121 + I2c_target_start_byte = 0x0400, // Special: start byte (1) or general call (0)
1.122 + I2c_target_10bits = 0x3ff, // Mask for 10-bit address
1.123 + I2c_target_7bits = 0x7f, // Mask for 7-bit address
1.124 +};
1.125 +
1.126 +enum I2c_hold_control_bits : unsigned
1.127 +{
1.128 + /* The hold enable flag has been removed since the JZ4780 and the hold time
1.129 + field widened. */
1.130 +
1.131 + I2c_hold_mask = 0xffff,
1.132 +};
1.133 +
1.134 +enum I2c_setup_control_bits : unsigned
1.135 +{
1.136 + I2c_setup_mask = 0x0ff, // SDASU
1.137 +};
1.138 +
1.139 +enum I2c_command_bits : unsigned
1.140 +{
1.141 + I2c_command_restart = 0x400, // RESTART: explicit restart before next byte
1.142 + I2c_command_stop = 0x200, // STOP: explicit stop after next byte
1.143 + I2c_command_no_stop = 0x000,
1.144 + I2c_command_read = 0x100, // CMD
1.145 + I2c_command_write = 0x000, // CMD
1.146 +};
1.147 +
1.148 +enum I2c_fifo_bits : unsigned
1.149 +{
1.150 + I2c_fifo_limit = 64, // RXTL, TXTL (256 noted in field description)
1.151 +};
1.152 +
1.153 +enum Int_bits : unsigned
1.154 +{
1.155 + Int_call = 0x800, // IGC (general call received)
1.156 + Int_start = 0x400, // ISTT (start/restart condition occurred)
1.157 + Int_stop = 0x200, // ISTP (stop condition occurred)
1.158 + Int_activity = 0x100, // IACT (bus activity interrupt)
1.159 + Int_rx_done = 0x080, // RXDN (read from master device done)
1.160 + Int_tx_abort = 0x040, // TXABT (transmit abort)
1.161 + Int_rd_req = 0x020, // RDREQ (read request from master device)
1.162 + Int_tx_empty = 0x010, // TXEMP (threshold reached or passed)
1.163 + Int_tx_of = 0x008, // TXOF (overflow when writing to queue)
1.164 + Int_rx_full = 0x004, // RXFL (threshold reached or exceeded)
1.165 + Int_rx_of = 0x002, // RXOF (overflow from device)
1.166 + Int_rx_uf = 0x001, // RXUF (underflow when reading from queue)
1.167 +};
1.168 +
1.169 +
1.170 +
1.171 +// Initialise a channel.
1.172 +
1.173 +I2c_x1600_channel::I2c_x1600_channel(l4_addr_t start,
1.174 + Cpm_x1600_chip *cpm,
1.175 + uint32_t frequency)
1.176 +: _cpm(cpm), _frequency(frequency)
1.177 +{
1.178 + _regs = new Hw::Mmio_register_block<32>(start);
1.179 +}
1.180 +
1.181 +// Enable the channel.
1.182 +
1.183 +void
1.184 +I2c_x1600_channel::enable()
1.185 +{
1.186 + _regs[I2c_enable] = I2c_enable_enabled;
1.187 + while (!(_regs[I2c_enable_status] & I2c_enable_enabled));
1.188 +}
1.189 +
1.190 +// Disable the channel.
1.191 +
1.192 +void
1.193 +I2c_x1600_channel::disable()
1.194 +{
1.195 + _regs[I2c_enable] = 0;
1.196 + while (_regs[I2c_enable_status] & I2c_enable_enabled);
1.197 +}
1.198 +
1.199 +// Return the configured frequency.
1.200 +
1.201 +uint32_t
1.202 +I2c_x1600_channel::get_frequency()
1.203 +{
1.204 + return _frequency;
1.205 +}
1.206 +
1.207 +// Set the frequency-related peripheral parameters.
1.208 +
1.209 +void
1.210 +I2c_x1600_channel::set_frequency()
1.211 +{
1.212 + // The APB clock (PCLK) is used to drive I2C transfers. Its value must be
1.213 + // obtained from the CPM unit. It is known as I2C_DEV_CLK here and is scaled
1.214 + // to kHz in order to keep the numbers easily representable, as is the bus
1.215 + // frequency.
1.216 +
1.217 + uint32_t i2c_dev_clk = _cpm->get_frequency(Clock_pclock) / 1000;
1.218 +
1.219 + // Note that this is not I2C_DEV_CLK but the actual I2C bus frequency.
1.220 +
1.221 + uint32_t i2c_clk = _frequency / 1000;
1.222 +
1.223 + // Select the appropriate speed.
1.224 +
1.225 + unsigned int speed = (i2c_clk <= 100) ? I2c_speed_standard
1.226 + : (i2c_clk <= 400 ? I2c_speed_fast
1.227 + : I2c_speed_high);
1.228 +
1.229 + _regs[I2c_control] = _regs[I2c_control] | (speed << I2c_speed_bit) |
1.230 + I2c_disable_slave |
1.231 + I2c_enable_restart |
1.232 + I2c_enable_master;
1.233 +
1.234 + // According to the programming manual, if the PCLK period is T{I2C_DEV_CLK}
1.235 + // then the I2C clock period is...
1.236 +
1.237 + // T{SCL} = T{SCL_high} + T{SCL_low}
1.238 +
1.239 + // Where...
1.240 +
1.241 + // T{SCL_low} = T{I2C_DEV_CLK} * (#cycles for low signal)
1.242 + // T{SCL_high} = T{I2C_DEV_CLK} * (#cycles for high signal)
1.243 +
1.244 + // Since, with minimum periods being defined...
1.245 +
1.246 + // T{SCL} >= T{min_SCL}
1.247 + // T{SCL_low} >= T{min_SCL_low}
1.248 + // T{SCL_high} >= T{min_SCL_high}
1.249 + // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high}
1.250 +
1.251 + // Then the following applies...
1.252 +
1.253 + // T{I2C_DEV_CLK} * (#cycles for low signal)) >= T{min_SCL_low}
1.254 + // T{I2C_DEV_CLK} * (#cycles for high signal) >= T{min_SCL_high}
1.255 +
1.256 + // To work with different clock speeds while maintaining the low-to-high
1.257 + // ratios:
1.258 +
1.259 + // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL}
1.260 + // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high}))
1.261 +
1.262 + // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL}
1.263 + // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high}))
1.264 +
1.265 + // Constraints are given with respect to the high and low count registers.
1.266 +
1.267 + // #cycles for high signal = I2CxHCNT + 8
1.268 + // #cycles for low signal = I2CxLCNT + 1
1.269 +
1.270 + // From earlier, this yields...
1.271 +
1.272 + // T{I2C_DEV_CLK} * (I2CxLCNT + 1) >= T{min_SCL_low}
1.273 + // T{I2C_DEV_CLK} * (I2CxHCNT + 8) >= T{min_SCL_high}
1.274 +
1.275 + // Rearranging...
1.276 +
1.277 + // I2CxLCNT >= (T{min_SCL_low} / T{I2C_DEV_CLK}) - 1
1.278 + // >= T{min_SCL_low} * I2C_DEV_CLK - 1
1.279 +
1.280 + // I2CxHCNT >= (T{min_SCL_high} / T{I2C_DEV_CLK}) - 8
1.281 + // >= T{min_SCL_high} * I2C_DEV_CLK - 8
1.282 +
1.283 + // Introducing the definitions for the high and low periods...
1.284 +
1.285 + // I2CxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 1
1.286 + // >= (T{min_SCL_low} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 1
1.287 +
1.288 + // I2CxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 8
1.289 + // >= (T{min_SCL_high} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 8
1.290 +
1.291 + uint32_t high_reg, low_reg;
1.292 + uint32_t high_count, low_count;
1.293 + int32_t hold_count;
1.294 + uint32_t setup_count;
1.295 +
1.296 + // Level hold times:
1.297 +
1.298 + // Standard Fast High
1.299 + // SCL low 4.7us 1.3us 0.5us
1.300 + // SCL high 4.0us 0.6us 0.26us +
1.301 + // SCL period 8.7us 1.9us 0.76us =
1.302 +
1.303 + // See: UM10204 "I2C-bus specification and user manual"
1.304 + // Table 10: t{LOW} and t{HIGH}
1.305 +
1.306 + if (i2c_clk <= 100) // 100 kHz
1.307 + {
1.308 + low_count = (i2c_dev_clk * 47) / (i2c_clk * 87) - 1;
1.309 + high_count = (i2c_dev_clk * 40) / (i2c_clk * 87) - 8;
1.310 + low_reg = Std_low_count;
1.311 + high_reg = Std_high_count;
1.312 + }
1.313 + else if (i2c_clk <= 400) // 400 kHz
1.314 + {
1.315 + low_count = (i2c_dev_clk * 13) / (i2c_clk * 19) - 1;
1.316 + high_count = (i2c_dev_clk * 6) / (i2c_clk * 19) - 8;
1.317 + low_reg = Fast_low_count;
1.318 + high_reg = Fast_high_count;
1.319 + }
1.320 + else // > 400 kHz
1.321 + {
1.322 + // Note how the frequencies are scaled to accommodate the extra precision
1.323 + // required.
1.324 +
1.325 + low_count = (i2c_dev_clk / 10 * 50) / (i2c_clk / 10 * 76) - 1;
1.326 + high_count = (i2c_dev_clk / 10 * 26) / (i2c_clk / 10 * 76) - 8;
1.327 + low_reg = High_low_count;
1.328 + high_reg = High_high_count;
1.329 + }
1.330 +
1.331 + // Minimum counts are 8 and 6 for low and high respectively.
1.332 +
1.333 + _regs[low_reg] = low_count < 8 ? 8 : low_count;
1.334 + _regs[high_reg] = high_count < 6 ? 6 : high_count;
1.335 +
1.336 + //printf("low_count: %d\n", low_count);
1.337 + //printf("high_count: %d\n", high_count);
1.338 +
1.339 + // Data hold and setup times:
1.340 +
1.341 + // Standard Fast High
1.342 + // t{HD;DAT} 300ns 300ns 300ns
1.343 + // t{SU;DAT} 250ns 100ns 50ns
1.344 +
1.345 + // See: UM10204 "I2C-bus specification and user manual"
1.346 + // Table 10: t{HD;DAT} and t{SU;DAT}, also note [3]
1.347 +
1.348 + // T{delay} = (I2CSDAHD + 2) * T{I2C_DEV_CLK}
1.349 + // I2CSDAHD = T{delay} / T{I2C_DEV_CLK} - 2
1.350 + // I2CSDAHD = I2C_DEV_CLK * T{delay} - 2
1.351 +
1.352 + // Since the device clock is in kHz (scaled down by 1000) and the times are
1.353 + // given in ns (scaled up by 1000000000), a division of 1000000 is introduced.
1.354 +
1.355 + hold_count = (i2c_dev_clk * 300) / 1000000 - 1;
1.356 +
1.357 + _regs[I2c_sda_hold_time] = (_regs[I2c_sda_hold_time] & ~I2c_hold_mask) |
1.358 + (hold_count < 0 ? 0
1.359 + : (hold_count < (int) I2c_hold_mask ? (uint32_t) hold_count
1.360 + : I2c_hold_mask));
1.361 +
1.362 + //printf("i2c_dev_clk: %d\n", i2c_dev_clk);
1.363 + //printf("SDA hold: %x\n", hold_count);
1.364 +
1.365 + // I2C_SDASU is apparently not used in master mode.
1.366 +
1.367 + // T{delay} = (I2CSDASU - 1) * T{I2C_DEV_CLK}
1.368 + // I2CSDASU = T{delay} / T{I2C_DEV_CLK} + 1
1.369 + // I2CSDASU = I2C_DEV_CLK * T{delay} + 1
1.370 +
1.371 + if (i2c_clk <= 100)
1.372 + setup_count = (i2c_dev_clk * 250) / 1000000 + 1;
1.373 + else if (i2c_clk <= 400)
1.374 + setup_count = (i2c_dev_clk * 100) / 1000000 + 1;
1.375 + else
1.376 + setup_count = (i2c_dev_clk * 50) / 1000000 + 1;
1.377 +
1.378 + _regs[I2c_sda_setup_time] = (_regs[I2c_sda_setup_time] & ~I2c_setup_mask) |
1.379 + (setup_count < I2c_setup_mask ? setup_count : I2c_setup_mask);
1.380 +}
1.381 +
1.382 +// Set the target address and enable transfer.
1.383 +// NOTE: Only supporting 7-bit addresses currently.
1.384 +
1.385 +void
1.386 +I2c_x1600_channel::set_target(uint8_t address)
1.387 +{
1.388 + //printf("set_target: %x\n", address);
1.389 + disable();
1.390 + set_frequency();
1.391 + _regs[I2c_target_address] = address & I2c_target_7bits;
1.392 + enable();
1.393 + init_parameters();
1.394 + //printf("I2c_enable_status: %x\n", (uint32_t) _regs[I2c_enable_status]);
1.395 + //printf("I2c_status: %x\n", (uint32_t) _regs[I2c_status]);
1.396 + //printf("Int_mask: %x\n", (uint32_t) _regs[Int_mask]);
1.397 + //printf("Int_status: %x\n", (uint32_t) _regs[Int_status]);
1.398 + printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]);
1.399 +}
1.400 +
1.401 +
1.402 +
1.403 +// Reset interrupt flags upon certain conditions.
1.404 +
1.405 +void
1.406 +I2c_x1600_channel::reset_flags()
1.407 +{
1.408 + volatile uint32_t r;
1.409 +
1.410 + _regs[Int_mask] = 0;
1.411 +
1.412 + // Read from the register to clear interrupts.
1.413 +
1.414 + r = _regs[Int_combined_clear];
1.415 + (void) r;
1.416 +}
1.417 +
1.418 +// Initialise interrupt flags and queue thresholds for reading and writing.
1.419 +
1.420 +void
1.421 +I2c_x1600_channel::init_parameters()
1.422 +{
1.423 + // Handle read queue conditions for data, write queue conditions for commands.
1.424 +
1.425 + reset_flags();
1.426 +
1.427 + _regs[Tx_fifo_thold] = 0; // write when 0 in queue
1.428 +}
1.429 +
1.430 +
1.431 +
1.432 +// Return whether the device is active.
1.433 +
1.434 +int
1.435 +I2c_x1600_channel::active()
1.436 +{
1.437 + return _regs[I2c_status] & I2c_status_master_act;
1.438 +}
1.439 +
1.440 +// Return whether data is available to receive.
1.441 +
1.442 +int
1.443 +I2c_x1600_channel::have_input()
1.444 +{
1.445 + return _regs[I2c_status] & I2c_status_rx_nempty;
1.446 +}
1.447 +
1.448 +// Return whether data is queued for sending.
1.449 +
1.450 +int
1.451 +I2c_x1600_channel::have_output()
1.452 +{
1.453 + return !(_regs[I2c_status] & I2c_status_tx_empty);
1.454 +}
1.455 +
1.456 +// Return whether data can be queued for sending.
1.457 +
1.458 +int
1.459 +I2c_x1600_channel::can_send()
1.460 +{
1.461 + return _regs[I2c_status] & I2c_status_tx_nfull;
1.462 +}
1.463 +
1.464 +// Return whether a receive operation has failed.
1.465 +
1.466 +int
1.467 +I2c_x1600_channel::read_failed()
1.468 +{
1.469 + return _regs[Int_status] & Int_rx_of;
1.470 +}
1.471 +
1.472 +// Return whether a send operation has failed.
1.473 +
1.474 +int
1.475 +I2c_x1600_channel::write_failed()
1.476 +{
1.477 + return _regs[Int_status] & Int_tx_abort;
1.478 +}
1.479 +
1.480 +int
1.481 +I2c_x1600_channel::read_done()
1.482 +{
1.483 + return _pos == _total;
1.484 +}
1.485 +
1.486 +int
1.487 +I2c_x1600_channel::write_done()
1.488 +{
1.489 + return _reqpos == _total;
1.490 +}
1.491 +
1.492 +unsigned
1.493 +I2c_x1600_channel::have_read()
1.494 +{
1.495 + return _pos;
1.496 +}
1.497 +
1.498 +unsigned
1.499 +I2c_x1600_channel::have_written()
1.500 +{
1.501 + return _reqpos;
1.502 +}
1.503 +
1.504 +int
1.505 +I2c_x1600_channel::failed()
1.506 +{
1.507 + return _fail;
1.508 +}
1.509 +
1.510 +
1.511 +
1.512 +// Send read commands for empty queue entries.
1.513 +
1.514 +void
1.515 +I2c_x1600_channel::queue_reads()
1.516 +{
1.517 + unsigned int remaining = _total - _reqpos;
1.518 + unsigned int queued = _reqpos - _pos;
1.519 + unsigned int can_queue = I2c_fifo_limit - queued;
1.520 +
1.521 + // Keep the number of reads in progress below the length of the read queue.
1.522 +
1.523 + if (!can_queue)
1.524 + return;
1.525 +
1.526 + // At most, only queue as many reads as are remaining.
1.527 +
1.528 + if (remaining < can_queue)
1.529 + can_queue = remaining;
1.530 +
1.531 + // Queue read requests for any remaining queue entries.
1.532 +
1.533 + while (can_queue && can_send())
1.534 + {
1.535 + uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop;
1.536 + printf("Queue read %d/%d %s\n", _reqpos, _total - 1, stop ? "stop" : "continue");
1.537 +
1.538 + _regs[I2c_data_command] = I2c_command_read | stop;
1.539 + _reqpos++;
1.540 + can_queue--;
1.541 + }
1.542 +
1.543 + // Update the threshold to be notified of any reduced remaining amount.
1.544 +
1.545 + set_read_threshold();
1.546 +}
1.547 +
1.548 +// Send write commands for empty queue entries.
1.549 +
1.550 +void
1.551 +I2c_x1600_channel::queue_writes()
1.552 +{
1.553 + unsigned int remaining = _total - _reqpos;
1.554 + unsigned int can_queue = I2c_fifo_limit;
1.555 +
1.556 + if (remaining < can_queue)
1.557 + can_queue = remaining;
1.558 +
1.559 + printf("queue_writes: %d %s\n", can_queue, can_send() ? "can send" : "cannot send");
1.560 +
1.561 + // Queue write requests for any remaining queue entries.
1.562 +
1.563 + while (can_queue && can_send())
1.564 + {
1.565 + uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop;
1.566 + printf("Queue write %d/%d %s\n", _reqpos, _total - 1, stop ? "stop" : "continue");
1.567 +
1.568 + _regs[I2c_data_command] = I2c_command_write | _buf[_reqpos] | stop;
1.569 + _reqpos++;
1.570 + can_queue--;
1.571 + }
1.572 +
1.573 + printf("Tx_fifo_count = %d\n", (uint32_t) _regs[Tx_fifo_count]);
1.574 +}
1.575 +
1.576 +// Store read command results from the queue.
1.577 +
1.578 +void
1.579 +I2c_x1600_channel::store_reads()
1.580 +{
1.581 + printf("store_reads: %s\n", have_input() ? "input" : "no input");
1.582 +
1.583 + // Read any input and store it in the buffer.
1.584 +
1.585 + while (have_input() && (_pos < _reqpos))
1.586 + {
1.587 + _buf[_pos] = _regs[I2c_data_command] & 0xff;
1.588 + _pos++;
1.589 + }
1.590 +}
1.591 +
1.592 +void
1.593 +I2c_x1600_channel::set_read_threshold()
1.594 +{
1.595 + unsigned int queued = _reqpos - _pos;
1.596 +
1.597 + if (!queued)
1.598 + return;
1.599 +
1.600 + // Read all expected.
1.601 +
1.602 + _regs[Rx_fifo_thold] = queued - 1;
1.603 + printf("Rx_fifo_thold = %d\n", (uint32_t) _regs[Rx_fifo_thold]);
1.604 +}
1.605 +
1.606 +// Read from the target device.
1.607 +
1.608 +void
1.609 +I2c_x1600_channel::start_read(uint8_t buf[], unsigned int total, int stop)
1.610 +{
1.611 + _buf = buf;
1.612 + _total = total;
1.613 + _pos = 0;
1.614 + _reqpos = 0;
1.615 + _fail = 0;
1.616 + _stop = stop;
1.617 +
1.618 + printf("start_read: %d\n", total);
1.619 +
1.620 + _regs[Int_mask] = Int_rx_full | // read condition (reading needed)
1.621 + Int_rx_of | // abort condition
1.622 + Int_tx_abort; // abort condition
1.623 +
1.624 + // Perform initial read requests.
1.625 +
1.626 + read();
1.627 +}
1.628 +
1.629 +void
1.630 +I2c_x1600_channel::read()
1.631 +{
1.632 + printf("Rx_fifo_count = %d\n", (uint32_t) _regs[Rx_fifo_count]);
1.633 + printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]);
1.634 + printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]);
1.635 +
1.636 + if (read_failed() || write_failed())
1.637 + {
1.638 + _fail = 1;
1.639 + _regs[Int_mask] = 0;
1.640 + return;
1.641 + }
1.642 +
1.643 + if (_regs[Int_status] & Int_rx_full)
1.644 + store_reads();
1.645 +
1.646 + // Always attempt to queue more read requests.
1.647 +
1.648 + queue_reads();
1.649 +}
1.650 +
1.651 +// Write to the target device.
1.652 +
1.653 +void
1.654 +I2c_x1600_channel::start_write(uint8_t buf[], unsigned int total, int stop)
1.655 +{
1.656 + _buf = buf;
1.657 + _total = total;
1.658 + _reqpos = 0;
1.659 + _fail = 0;
1.660 + _stop = stop;
1.661 +
1.662 + printf("start_write: %d\n", total);
1.663 +
1.664 + // Enable interrupts for further writes.
1.665 +
1.666 + _regs[Int_mask] = Int_tx_empty | // write condition (writing needed)
1.667 + Int_tx_abort; // abort condition
1.668 +
1.669 + // Perform initial writes.
1.670 +
1.671 + write();
1.672 +}
1.673 +
1.674 +void
1.675 +I2c_x1600_channel::write()
1.676 +{
1.677 + printf("Tx_fifo_count = %d\n", (uint32_t) _regs[Tx_fifo_count]);
1.678 + printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]);
1.679 + printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]);
1.680 +
1.681 + if (write_failed())
1.682 + {
1.683 + _fail = 1;
1.684 + _regs[Int_mask] = 0;
1.685 + return;
1.686 + }
1.687 +
1.688 + if (_regs[Int_status] & Int_tx_empty)
1.689 + queue_writes();
1.690 +}
1.691 +
1.692 +// Explicitly stop communication.
1.693 +
1.694 +void
1.695 +I2c_x1600_channel::stop()
1.696 +{
1.697 +}
1.698 +
1.699 +
1.700 +
1.701 +// Initialise the I2C controller.
1.702 +
1.703 +I2c_x1600_chip::I2c_x1600_chip(l4_addr_t start, l4_addr_t end,
1.704 + Cpm_x1600_chip *cpm,
1.705 + uint32_t frequency)
1.706 +: _start(start), _end(end), _cpm(cpm), _frequency(frequency)
1.707 +{
1.708 +}
1.709 +
1.710 +// Obtain a channel object.
1.711 +
1.712 +I2c_x1600_channel *
1.713 +I2c_x1600_chip::get_channel(uint8_t channel)
1.714 +{
1.715 + l4_addr_t block = _start + channel * I2c_block_offset;
1.716 + enum Clock_identifiers bits[] = {Clock_i2c0, Clock_i2c1};
1.717 +
1.718 + if (channel < 2)
1.719 + {
1.720 + _cpm->start_clock(bits[channel]);
1.721 + return new I2c_x1600_channel(block, _cpm, _frequency);
1.722 + }
1.723 + else
1.724 + throw -L4_EINVAL;
1.725 +}
1.726 +
1.727 +
1.728 +
1.729 +// C language interface functions.
1.730 +
1.731 +void *x1600_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency)
1.732 +{
1.733 + return (void *) new I2c_x1600_chip(start, end, static_cast<Cpm_x1600_chip *>(cpm), frequency);
1.734 +}
1.735 +
1.736 +void x1600_i2c_disable(void *i2c_channel)
1.737 +{
1.738 + static_cast<I2c_x1600_channel *>(i2c_channel)->disable();
1.739 +}
1.740 +
1.741 +void *x1600_i2c_get_channel(void *i2c, uint8_t channel)
1.742 +{
1.743 + return static_cast<I2c_x1600_chip *>(i2c)->get_channel(channel);
1.744 +}
1.745 +
1.746 +uint32_t x1600_i2c_get_frequency(void *i2c_channel)
1.747 +{
1.748 + return static_cast<I2c_x1600_channel *>(i2c_channel)->get_frequency();
1.749 +}
1.750 +
1.751 +void x1600_i2c_set_target(void *i2c_channel, uint8_t addr)
1.752 +{
1.753 + static_cast<I2c_x1600_channel *>(i2c_channel)->set_target(addr);
1.754 +}
1.755 +
1.756 +void x1600_i2c_start_read(void *i2c_channel, uint8_t buf[], unsigned int total,
1.757 + int stop)
1.758 +{
1.759 + static_cast<I2c_x1600_channel *>(i2c_channel)->start_read(buf, total, stop);
1.760 +}
1.761 +
1.762 +void x1600_i2c_read(void *i2c_channel)
1.763 +{
1.764 + static_cast<I2c_x1600_channel *>(i2c_channel)->read();
1.765 +}
1.766 +
1.767 +void x1600_i2c_start_write(void *i2c_channel, uint8_t buf[], unsigned int total,
1.768 + int stop)
1.769 +{
1.770 + static_cast<I2c_x1600_channel *>(i2c_channel)->start_write(buf, total, stop);
1.771 +}
1.772 +
1.773 +void x1600_i2c_write(void *i2c_channel)
1.774 +{
1.775 + static_cast<I2c_x1600_channel *>(i2c_channel)->write();
1.776 +}
1.777 +
1.778 +int x1600_i2c_read_done(void *i2c_channel)
1.779 +{
1.780 + return static_cast<I2c_x1600_channel *>(i2c_channel)->read_done();
1.781 +}
1.782 +
1.783 +int x1600_i2c_write_done(void *i2c_channel)
1.784 +{
1.785 + return static_cast<I2c_x1600_channel *>(i2c_channel)->write_done();
1.786 +}
1.787 +
1.788 +unsigned int x1600_i2c_have_read(void *i2c_channel)
1.789 +{
1.790 + return static_cast<I2c_x1600_channel *>(i2c_channel)->have_read();
1.791 +}
1.792 +
1.793 +unsigned int x1600_i2c_have_written(void *i2c_channel)
1.794 +{
1.795 + return static_cast<I2c_x1600_channel *>(i2c_channel)->have_written();
1.796 +}
1.797 +
1.798 +int x1600_i2c_failed(void *i2c_channel)
1.799 +{
1.800 + return static_cast<I2c_x1600_channel *>(i2c_channel)->failed();
1.801 +}
1.802 +
1.803 +void x1600_i2c_stop(void *i2c_channel)
1.804 +{
1.805 + static_cast<I2c_x1600_channel *>(i2c_channel)->stop();
1.806 +}