1 /* 2 * I2C support for the JZ4780 and X1600. 3 * 4 * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-common.h> 23 24 #include <l4/sys/icu.h> 25 #include <l4/util/util.h> 26 #include <sys/time.h> 27 28 /* NOTE: The X1600 is very similar to the JZ4780 with the registers 29 renamed to I2C from SMB, with a few high speed registers, the 30 I2C_RINTST, I2C_TXFLR and I2C_RXFLR registers, and a few other 31 registers added, with I2C_SDAHD appearing at a different location. */ 32 33 enum Regs 34 { 35 I2c_control = 0x000, // I2C_CON 36 I2c_target_address = 0x004, // I2C_TAR 37 I2c_slave_address = 0x008, // I2C_SAR 38 I2c_master_code = 0x00c, // I2C_HS_MADDR 39 I2c_data_command = 0x010, // I2C_DC 40 Std_high_count = 0x014, // I2C_SHCNT 41 Std_low_count = 0x018, // I2C_SLCNT 42 Fast_high_count = 0x01c, // I2C_FHCNT 43 Fast_low_count = 0x020, // I2C_FLCNT 44 Int_status = 0x02c, // I2C_INTST (read-only) 45 Int_mask = 0x030, // I2C_INTM 46 Rx_fifo_thold = 0x038, // I2C_RXTL 47 Tx_fifo_thold = 0x03c, // I2C_TXTL 48 Int_combined_clear = 0x040, // I2C_CINT (read-only) 49 Int_rx_uf_clear = 0x044, // I2C_CRXUF (read-only) 50 Int_rx_of_clear = 0x048, // I2C_CRXOF (read-only) 51 Int_tx_of_clear = 0x04c, // I2C_CTXOF (read-only) 52 Int_rd_req_clear = 0x050, // I2C_CRXREQ (read-only) 53 Int_tx_abort_clear = 0x054, // I2C_CTXABT (read-only) 54 Int_rx_done_clear = 0x058, // I2C_CRXDN (read-only) 55 Int_activity_clear = 0x05c, // I2C_CACT (read-only) 56 Int_stop_clear = 0x060, // I2C_CSTP (read-only) 57 Int_start_clear = 0x064, // I2C_CSTT (read-only) 58 Int_call_clear = 0x068, // I2C_CGC (read-only) 59 I2c_enable = 0x06c, // I2C_ENB 60 I2c_status = 0x070, // I2C_ST (read-only) 61 I2c_sda_hold_time = 0x07c, // I2C_SDAHD 62 Trans_abort_status = 0x080, // I2C_ABTSRC (read-only) 63 I2c_dma_ctrl = 0x088, // I2C_DMACR 64 I2c_trans_data_lvl = 0x08c, // I2C_DMATDLR 65 I2c_recv_data_lvl = 0x090, // I2C_DMARDLR 66 I2c_sda_setup_time = 0x094, // I2C_SDASU 67 I2c_ack_call = 0x098, // I2C_ACKGC 68 I2c_enable_status = 0x09c, // I2C_ENBST (read-only) 69 70 // X1600 only... 71 72 High_high_count = 0x024, // I2C_HHCNT 73 High_low_count = 0x028, // I2C_HLCNT 74 Int_raw_status = 0x034, // I2C_RINTST (read-only) 75 Tx_fifo_count = 0x074, // I2C_TXFLR (read-only) 76 Rx_fifo_count = 0x078, // I2C_RXFLR (read-only) 77 Slv_data_nack = 0x084, // I2CSDNACK 78 I2c_spike_suppress = 0x0a0, // I2C_FSPKLEN 79 80 // Register block spacing. 81 82 I2c_block_offset = 0x1000 83 }; 84 85 enum I2c_control_bits : unsigned 86 { 87 I2c_disable_slave = 0x40, // SLVDIS (slave disabled) 88 I2c_enable_restart = 0x20, // RESTART 89 I2c_master_10bit = 0x10, // MATP (read-only) 90 I2c_slave_10bit = 0x08, // SATP 91 I2c_speed_mode_mask = 0x06, // SPEED 92 I2c_enable_master = 0x01, // MD (master enabled) 93 I2c_speed_bit = 1, // SPD 94 }; 95 96 enum I2c_speed_mode_values : unsigned 97 { 98 I2c_speed_standard = 1, 99 I2c_speed_fast = 2, 100 I2c_speed_high = 3, 101 }; 102 103 enum I2c_enable_bits : unsigned 104 { 105 I2c_enable_enabled = 0x01, // I2CEN 106 }; 107 108 enum I2c_status_bits : unsigned 109 { 110 I2c_status_master_act = 0x20, // MSTACT (master active) 111 I2c_status_rx_nempty = 0x08, // RFNE (read queue not empty) 112 I2c_status_tx_empty = 0x04, // TFE (write queue empty) 113 I2c_status_tx_nfull = 0x02, // TFNF (write queue not full) 114 I2c_status_active = 0x01, // ACT (device active as master or slave) 115 }; 116 117 enum I2c_target_bits : unsigned 118 { 119 I2c_target_master_10bit = 0x1000, 120 I2c_target_special = 0x0800, // SPECIAL: perform general call or start byte 121 I2c_target_start_byte = 0x0400, // Special: start byte (1) or general call (0) 122 I2c_target_10bits = 0x3ff, // Mask for 10-bit address 123 I2c_target_7bits = 0x7f, // Mask for 7-bit address 124 }; 125 126 enum I2c_hold_control_bits : unsigned 127 { 128 /* The hold enable flag has been removed since the JZ4780 and the hold time 129 field widened. */ 130 131 I2c_hold_mask = 0xffff, 132 }; 133 134 enum I2c_setup_control_bits : unsigned 135 { 136 I2c_setup_mask = 0x0ff, // SDASU 137 }; 138 139 enum I2c_command_bits : unsigned 140 { 141 I2c_command_restart = 0x400, // RESTART: explicit restart before next byte 142 I2c_command_stop = 0x200, // STOP: explicit stop after next byte 143 I2c_command_no_stop = 0x000, 144 I2c_command_read = 0x100, // CMD 145 I2c_command_write = 0x000, // CMD 146 }; 147 148 enum I2c_fifo_bits : unsigned 149 { 150 I2c_fifo_limit = 64, // RXTL, TXTL (256 noted in field description) 151 }; 152 153 enum Int_bits : unsigned 154 { 155 Int_call = 0x800, // IGC (general call received) 156 Int_start = 0x400, // ISTT (start/restart condition occurred) 157 Int_stop = 0x200, // ISTP (stop condition occurred) 158 Int_activity = 0x100, // IACT (bus activity interrupt) 159 Int_rx_done = 0x080, // RXDN (read from master device done) 160 Int_tx_abort = 0x040, // TXABT (transmit abort) 161 Int_rd_req = 0x020, // RDREQ (read request from master device) 162 Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) 163 Int_tx_of = 0x008, // TXOF (overflow when writing to queue) 164 Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) 165 Int_rx_of = 0x002, // RXOF (overflow from device) 166 Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) 167 }; 168 169 170 171 // Initialise a channel. 172 173 I2c_channel::I2c_channel(l4_addr_t start, 174 enum Clock_identifiers clock, 175 Cpm_chip *cpm, 176 uint32_t frequency) 177 : _cpm(cpm), _frequency(frequency) 178 { 179 _regs = new Hw::Mmio_register_block<32>(start); 180 _cpm->start_clock(clock); 181 } 182 183 // Enable the channel. 184 185 void 186 I2c_channel::enable() 187 { 188 _regs[I2c_enable] = I2c_enable_enabled; 189 while (!(_regs[I2c_enable_status] & I2c_enable_enabled)); 190 } 191 192 // Disable the channel. 193 194 void 195 I2c_channel::disable() 196 { 197 _regs[I2c_enable] = 0; 198 while (_regs[I2c_enable_status] & I2c_enable_enabled); 199 } 200 201 // Return the configured frequency. 202 203 uint32_t 204 I2c_channel::get_frequency() 205 { 206 return _frequency; 207 } 208 209 // Set the frequency-related peripheral parameters. 210 211 void 212 I2c_channel::set_frequency() 213 { 214 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 215 // obtained from the CPM unit. It is known as I2C_DEV_CLK here and is scaled 216 // to kHz in order to keep the numbers easily representable, as is the bus 217 // frequency. 218 219 uint32_t i2c_dev_clk = _cpm->get_frequency(Clock_pclock) / 1000; 220 221 // Note that this is not I2C_DEV_CLK but the actual I2C bus frequency. 222 223 uint32_t i2c_clk = _frequency / 1000; 224 225 // Select the appropriate speed. 226 227 unsigned int speed = (i2c_clk <= 100) ? I2c_speed_standard 228 : (i2c_clk <= 400 ? I2c_speed_fast 229 : I2c_speed_high); 230 231 // NOTE: Permit broader configuration elsewhere. 232 233 _regs[I2c_control] = (speed << I2c_speed_bit) | 234 I2c_disable_slave | 235 I2c_enable_restart | 236 I2c_enable_master; 237 238 // According to the programming manual, if the PCLK period is T{I2C_DEV_CLK} 239 // then the I2C clock period is... 240 241 // T{SCL} = T{SCL_high} + T{SCL_low} 242 243 // Where... 244 245 // T{SCL_low} = T{I2C_DEV_CLK} * (#cycles for low signal) 246 // T{SCL_high} = T{I2C_DEV_CLK} * (#cycles for high signal) 247 248 // Since, with minimum periods being defined... 249 250 // T{SCL} >= T{min_SCL} 251 // T{SCL_low} >= T{min_SCL_low} 252 // T{SCL_high} >= T{min_SCL_high} 253 // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} 254 255 // Then the following applies... 256 257 // T{I2C_DEV_CLK} * (#cycles for low signal)) >= T{min_SCL_low} 258 // T{I2C_DEV_CLK} * (#cycles for high signal) >= T{min_SCL_high} 259 260 // To work with different clock speeds while maintaining the low-to-high 261 // ratios: 262 263 // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} 264 // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) 265 266 // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} 267 // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) 268 269 // Constraints are given with respect to the high and low count registers. 270 271 // #cycles for high signal = I2CxHCNT + 8 272 // #cycles for low signal = I2CxLCNT + 1 273 274 // From earlier, this yields... 275 276 // T{I2C_DEV_CLK} * (I2CxLCNT + 1) >= T{min_SCL_low} 277 // T{I2C_DEV_CLK} * (I2CxHCNT + 8) >= T{min_SCL_high} 278 279 // Rearranging... 280 281 // I2CxLCNT >= (T{min_SCL_low} / T{I2C_DEV_CLK}) - 1 282 // >= T{min_SCL_low} * I2C_DEV_CLK - 1 283 284 // I2CxHCNT >= (T{min_SCL_high} / T{I2C_DEV_CLK}) - 8 285 // >= T{min_SCL_high} * I2C_DEV_CLK - 8 286 287 // Introducing the definitions for the high and low periods... 288 289 // I2CxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 1 290 // >= (T{min_SCL_low} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 1 291 292 // I2CxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 8 293 // >= (T{min_SCL_high} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 8 294 295 uint32_t high_reg, low_reg; 296 uint32_t high_count, low_count; 297 int32_t hold_count; 298 uint32_t setup_count; 299 300 // Level hold times: 301 302 // Standard Fast High 303 // SCL low 4.7us 1.3us 0.5us 304 // SCL high 4.0us 0.6us 0.26us + 305 // SCL period 8.7us 1.9us 0.76us = 306 307 // See: UM10204 "I2C-bus specification and user manual" 308 // Table 10: t{LOW} and t{HIGH} 309 310 if (i2c_clk <= 100) // 100 kHz 311 { 312 low_count = (i2c_dev_clk * 47) / (i2c_clk * 87) - 1; 313 high_count = (i2c_dev_clk * 40) / (i2c_clk * 87) - 8; 314 low_reg = Std_low_count; 315 high_reg = Std_high_count; 316 } 317 else if (i2c_clk <= 400) // 400 kHz 318 { 319 low_count = (i2c_dev_clk * 13) / (i2c_clk * 19) - 1; 320 high_count = (i2c_dev_clk * 6) / (i2c_clk * 19) - 8; 321 low_reg = Fast_low_count; 322 high_reg = Fast_high_count; 323 } 324 else // > 400 kHz 325 { 326 // Note how the frequencies are scaled to accommodate the extra precision 327 // required. 328 329 low_count = (i2c_dev_clk / 10 * 50) / (i2c_clk / 10 * 76) - 1; 330 high_count = (i2c_dev_clk / 10 * 26) / (i2c_clk / 10 * 76) - 8; 331 low_reg = High_low_count; 332 high_reg = High_high_count; 333 } 334 335 // Minimum counts are 8 and 6 for low and high respectively. 336 337 _regs[low_reg] = low_count < 8 ? 8 : low_count; 338 _regs[high_reg] = high_count < 6 ? 6 : high_count; 339 340 // Data hold and setup times: 341 342 // Standard Fast High 343 // t{HD;DAT} 300ns 300ns 300ns 344 // t{SU;DAT} 250ns 100ns 50ns 345 346 // See: UM10204 "I2C-bus specification and user manual" 347 // Table 10: t{HD;DAT} and t{SU;DAT}, also note [3] 348 349 // T{delay} = (I2CSDAHD + 2) * T{I2C_DEV_CLK} 350 // I2CSDAHD = T{delay} / T{I2C_DEV_CLK} - 2 351 // I2CSDAHD = I2C_DEV_CLK * T{delay} - 2 352 353 // Since the device clock is in kHz (scaled down by 1000) and the times are 354 // given in ns (scaled up by 1000000000), a division of 1000000 is introduced. 355 356 hold_count = (i2c_dev_clk * 300) / 1000000 - 1; 357 358 _regs[I2c_sda_hold_time] = (_regs[I2c_sda_hold_time] & ~I2c_hold_mask) | 359 (hold_count < 0 ? 0 360 : (hold_count < (int) I2c_hold_mask ? (uint32_t) hold_count 361 : I2c_hold_mask)); 362 363 // I2C_SDASU is apparently not used in master mode. 364 365 // T{delay} = (I2CSDASU - 1) * T{I2C_DEV_CLK} 366 // I2CSDASU = T{delay} / T{I2C_DEV_CLK} + 1 367 // I2CSDASU = I2C_DEV_CLK * T{delay} + 1 368 369 if (i2c_clk <= 100) 370 setup_count = (i2c_dev_clk * 250) / 1000000 + 1; 371 else if (i2c_clk <= 400) 372 setup_count = (i2c_dev_clk * 100) / 1000000 + 1; 373 else 374 setup_count = (i2c_dev_clk * 50) / 1000000 + 1; 375 376 _regs[I2c_sda_setup_time] = (_regs[I2c_sda_setup_time] & ~I2c_setup_mask) | 377 (setup_count < I2c_setup_mask ? setup_count : I2c_setup_mask); 378 } 379 380 // Set the target address and enable transfer. 381 // NOTE: Only supporting 7-bit addresses currently. 382 383 void 384 I2c_channel::set_target(uint8_t address) 385 { 386 disable(); 387 set_frequency(); 388 _regs[I2c_target_address] = address & I2c_target_7bits; 389 init_parameters(); 390 enable(); 391 } 392 393 394 395 // Reset interrupt flags upon certain conditions. 396 397 void 398 I2c_channel::reset_flags() 399 { 400 volatile uint32_t r; 401 402 _regs[Int_mask] = 0; 403 404 // Read from the register to clear interrupts. 405 406 r = _regs[Int_combined_clear]; 407 (void) r; 408 } 409 410 // Initialise interrupt flags and queue thresholds for reading and writing. 411 412 void 413 I2c_channel::init_parameters() 414 { 415 // Handle read queue conditions for data, write queue conditions for commands. 416 417 reset_flags(); 418 419 _regs[Tx_fifo_thold] = 0; // write when 0 in queue 420 } 421 422 423 424 // Return whether the device is active. 425 426 int 427 I2c_channel::active() 428 { 429 return _regs[I2c_status] & I2c_status_master_act; 430 } 431 432 // Return whether data is available to receive. 433 434 int 435 I2c_channel::have_input() 436 { 437 return _regs[I2c_status] & I2c_status_rx_nempty; 438 } 439 440 // Return whether data is queued for sending. 441 442 int 443 I2c_channel::have_output() 444 { 445 return !(_regs[I2c_status] & I2c_status_tx_empty); 446 } 447 448 // Return whether data can be queued for sending. 449 450 int 451 I2c_channel::can_send() 452 { 453 return _regs[I2c_status] & I2c_status_tx_nfull; 454 } 455 456 // Return whether a receive operation has failed. 457 458 int 459 I2c_channel::read_failed() 460 { 461 return _regs[Int_status] & Int_rx_of; 462 } 463 464 // Return whether a send operation has failed. 465 466 int 467 I2c_channel::write_failed() 468 { 469 return _regs[Int_status] & Int_tx_abort; 470 } 471 472 int 473 I2c_channel::read_done() 474 { 475 return _pos == _total; 476 } 477 478 int 479 I2c_channel::write_done() 480 { 481 return (_reqpos == _total) && !have_output(); 482 } 483 484 unsigned 485 I2c_channel::have_read() 486 { 487 return _pos; 488 } 489 490 unsigned 491 I2c_channel::have_written() 492 { 493 return _reqpos; 494 } 495 496 int 497 I2c_channel::failed() 498 { 499 return _fail; 500 } 501 502 503 504 // Send read commands for empty queue entries. 505 506 void 507 I2c_channel::queue_reads() 508 { 509 unsigned int remaining = _total - _reqpos; 510 unsigned int queued = _reqpos - _pos; 511 unsigned int can_queue = I2c_fifo_limit - queued; 512 513 // Keep the number of reads in progress below the length of the read queue. 514 515 if (!can_queue) 516 return; 517 518 // At most, only queue as many reads as are remaining. 519 520 if (remaining < can_queue) 521 can_queue = remaining; 522 523 // Queue read requests for any remaining queue entries. 524 525 while (can_queue && can_send()) 526 { 527 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 528 529 _regs[I2c_data_command] = I2c_command_read | stop; 530 _reqpos++; 531 can_queue--; 532 } 533 534 // Update the threshold to be notified of any reduced remaining amount. 535 536 set_read_threshold(); 537 } 538 539 // Send write commands for empty queue entries. 540 541 void 542 I2c_channel::queue_writes() 543 { 544 unsigned int remaining = _total - _reqpos; 545 unsigned int can_queue = I2c_fifo_limit; 546 547 if (remaining < can_queue) 548 can_queue = remaining; 549 550 // Queue write requests for any remaining queue entries. 551 552 while (can_queue && can_send()) 553 { 554 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 555 556 _regs[I2c_data_command] = I2c_command_write | _buf[_reqpos] | stop; 557 _reqpos++; 558 can_queue--; 559 } 560 } 561 562 // Store read command results from the queue. 563 564 void 565 I2c_channel::store_reads() 566 { 567 // Read any input and store it in the buffer. 568 569 while (have_input() && (_pos < _reqpos)) 570 { 571 _buf[_pos] = _regs[I2c_data_command] & 0xff; 572 _pos++; 573 } 574 } 575 576 void 577 I2c_channel::set_read_threshold() 578 { 579 unsigned int queued = _reqpos - _pos; 580 581 if (!queued) 582 return; 583 584 // Read all expected. 585 586 _regs[Rx_fifo_thold] = queued - 1; 587 } 588 589 // Read from the target device. 590 591 void 592 I2c_channel::start_read(uint8_t buf[], unsigned int total, int stop) 593 { 594 _buf = buf; 595 _total = total; 596 _pos = 0; 597 _reqpos = 0; 598 _fail = 0; 599 _stop = stop; 600 601 reset_flags(); 602 603 _regs[Int_mask] = Int_rx_full | // read condition (reading needed) 604 Int_rx_of | // abort condition 605 Int_tx_abort; // general abort condition 606 607 // Perform initial read requests. 608 609 read(); 610 } 611 612 void 613 I2c_channel::read() 614 { 615 // Test for the general transfer abort condition. 616 617 if (read_failed() || write_failed()) 618 { 619 _fail = 1; 620 _regs[Int_mask] = 0; 621 disable(); 622 enable(); 623 return; 624 } 625 626 if (_regs[Int_status] & Int_rx_full) 627 store_reads(); 628 629 // Always attempt to queue more read requests. 630 631 queue_reads(); 632 } 633 634 // Write to the target device. 635 636 void 637 I2c_channel::start_write(uint8_t buf[], unsigned int total, int stop) 638 { 639 _buf = buf; 640 _total = total; 641 _reqpos = 0; 642 _fail = 0; 643 _stop = stop; 644 645 reset_flags(); 646 647 // Enable interrupts for further writes. 648 649 _regs[Int_mask] = Int_tx_empty | // write condition (writing needed) 650 Int_tx_abort; // abort condition 651 652 // Perform initial writes. 653 654 write(); 655 } 656 657 void 658 I2c_channel::write() 659 { 660 if (write_failed()) 661 { 662 _fail = 1; 663 _regs[Int_mask] = 0; 664 disable(); 665 enable(); 666 return; 667 } 668 669 if (_regs[Int_status] & Int_tx_empty) 670 queue_writes(); 671 } 672 673 // Explicitly stop communication. 674 675 void 676 I2c_channel::stop() 677 { 678 } 679 680 681 682 // Initialise the I2C controller. 683 684 I2c_chip::I2c_chip(l4_addr_t start, l4_addr_t end, 685 Cpm_chip *cpm, 686 uint32_t frequency) 687 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 688 { 689 } 690 691 // Obtain a channel object. 692 693 I2c_channel * 694 I2c_chip::get_channel(uint8_t channel) 695 { 696 l4_addr_t block = _start + channel * I2c_block_offset; 697 698 // NOTE: Defining all the possible clocks. 699 700 enum Clock_identifiers clocks[] = {Clock_i2c0, Clock_i2c1, Clock_i2c2, Clock_i2c3, Clock_i2c4}; 701 702 if (channel < num_channels()) 703 return new I2c_channel(block, clocks[channel], _cpm, _frequency); 704 else 705 throw -L4_EINVAL; 706 }