1 /* 2 * DMA support for the JZ4730. 3 * 4 * Copyright (C) 2021, 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/dma-jz4730.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/ipc.h> 26 #include <l4/sys/irq.h> 27 #include <l4/sys/rcv_endpoint.h> 28 #include <l4/util/util.h> 29 30 #include <systypes/thread.h> 31 32 #include <stdio.h> 33 34 35 36 enum Global_regs 37 { 38 Dma_irq_pending = 0xf8, // IRQP 39 Dma_control = 0xfc, // DMAC 40 }; 41 42 enum Channel_regs 43 { 44 Dma_source = 0x00, // DSA 45 Dma_destination = 0x04, // DDA 46 Dma_transfer_count = 0x08, // DTC 47 Dma_request_source = 0x0c, // DRT 48 Dma_control_status = 0x10, // DCS 49 }; 50 51 enum Dma_irq_pending_shifts : unsigned 52 { 53 Dma_irq_pending_ch0 = 15, 54 Dma_irq_pending_ch1 = 14, 55 Dma_irq_pending_ch2 = 13, 56 Dma_irq_pending_ch3 = 12, 57 Dma_irq_pending_ch4 = 11, 58 Dma_irq_pending_ch5 = 10, 59 }; 60 61 enum Dma_control_bits : unsigned 62 { 63 Dma_control_priority_mode = 0x100, // PM 64 Dma_control_halt_occurred = 0x008, // HLT 65 Dma_control_address_error = 0x004, // AR 66 Dma_control_enable = 0x001, // DMAE 67 }; 68 69 enum Dma_control_priority_modes : unsigned 70 { 71 Dma_priority_mode_01234567 = 0, 72 Dma_priority_mode_02314675 = 1, 73 Dma_priority_mode_20136457 = 2, 74 Dma_priority_mode_round_robin = 3, 75 }; 76 77 enum Dma_transfer_count_bits : unsigned 78 { 79 Dma_transfer_count_mask = 0x00ffffff, 80 }; 81 82 enum Dma_request_source_bits : unsigned 83 { 84 Dma_request_type_mask = 0x0000001f, 85 }; 86 87 enum Dma_control_status_shifts : unsigned 88 { 89 Dma_ext_output_polarity = 31, 90 Dma_ext_output_mode_cycle = 30, 91 Dma_ext_req_detect_mode = 28, 92 Dma_ext_end_of_process_mode = 27, 93 Dma_req_detect_int_length = 16, 94 Dma_source_port_width = 14, 95 Dma_dest_port_width = 12, 96 Dma_trans_unit_size = 8, 97 Dma_trans_mode = 7, 98 }; 99 100 enum Dma_control_status_bits : unsigned 101 { 102 Dma_source_address_incr = 0x00800000, 103 Dma_source_address_no_incr = 0x00000000, 104 Dma_dest_address_incr = 0x00400000, 105 Dma_dest_address_no_incr = 0x00000000, 106 107 Dma_trans_unit_size_32_bit = 0x00000000, 108 Dma_trans_unit_size_8_bit = 0x00000100, 109 Dma_trans_unit_size_16_bit = 0x00000200, 110 Dma_trans_unit_size_16_byte = 0x00000300, 111 Dma_trans_unit_size_32_byte = 0x00000400, 112 113 Dma_address_error = 0x00000010, 114 Dma_trans_completed = 0x00000008, 115 Dma_trans_halted = 0x00000004, 116 Dma_channel_irq_enable = 0x00000002, 117 Dma_channel_enable = 0x00000001, 118 }; 119 120 enum Dma_port_width_values : unsigned 121 { 122 Dma_port_width_32_bit = 0, 123 Dma_port_width_8_bit = 1, 124 Dma_port_width_16_bit = 2, 125 }; 126 127 enum Dma_trans_mode_values : unsigned 128 { 129 Dma_trans_mode_single = 0, 130 Dma_trans_mode_block = 1, 131 }; 132 133 134 135 // Initialise a channel. 136 137 Dma_jz4730_channel::Dma_jz4730_channel(Dma_jz4730_chip *chip, uint8_t channel, 138 l4_addr_t start, l4_cap_idx_t irq) 139 : _chip(chip), _channel(channel), _irq(irq) 140 { 141 _regs = new Hw::Mmio_register_block<32>(start); 142 } 143 144 // Encode flags for an external transfer. 145 146 uint32_t 147 Dma_jz4730_channel::encode_external_transfer(enum Dma_jz4730_request_type type) 148 { 149 int external = (type == Dma_request_external) ? 1 : 0; 150 151 return 152 ((external ? (int) _ext_output_polarity : 0) << Dma_ext_output_polarity) | 153 ((external ? (int) _ext_output_mode_cycle : 0) << Dma_ext_output_mode_cycle) | 154 ((external ? (int) _ext_req_detect_mode : 0) << Dma_ext_req_detect_mode) | 155 ((external ? (int) _ext_end_of_process_mode : 0) << Dma_ext_end_of_process_mode); 156 } 157 158 // Return the closest interval length greater than or equal to the number of 159 // units given encoded in the request detection interval length field of the 160 // control/status register. 161 162 uint32_t 163 Dma_jz4730_channel::encode_req_detect_int_length(uint8_t units) 164 { 165 static uint8_t lengths[] = {0, 2, 4, 8, 12, 16, 20, 24, 28, 32, 48, 60, 64, 124, 128, 200}; 166 int i; 167 168 if (!units) 169 return 0; 170 171 for (i = 0; i <= 15; i++) 172 { 173 if (lengths[i] >= units) 174 break; 175 } 176 177 return i << Dma_req_detect_int_length; 178 } 179 180 // Encode the appropriate source port width. 181 182 uint32_t 183 Dma_jz4730_channel::encode_source_port_width(uint8_t width) 184 { 185 switch (width) 186 { 187 case 1: 188 return Dma_port_width_8_bit << Dma_source_port_width; 189 190 default: 191 return Dma_port_width_32_bit << Dma_source_port_width; 192 } 193 } 194 195 // Encode the appropriate destination port width for the given request type. 196 197 uint32_t 198 Dma_jz4730_channel::encode_destination_port_width(uint8_t width) 199 { 200 switch (width) 201 { 202 case 1: 203 return Dma_port_width_8_bit << Dma_dest_port_width; 204 205 default: 206 return Dma_port_width_32_bit << Dma_dest_port_width; 207 } 208 } 209 210 // Encode the transfer unit size. 211 212 uint32_t 213 Dma_jz4730_channel::encode_transfer_unit_size(uint8_t size) 214 { 215 switch (size) 216 { 217 case 1: 218 return Dma_trans_unit_size_8_bit; 219 220 case 2: 221 return Dma_trans_unit_size_16_bit; 222 223 case 16: 224 return Dma_trans_unit_size_16_byte; 225 226 case 32: 227 return Dma_trans_unit_size_32_byte; 228 229 default: 230 return Dma_trans_unit_size_32_bit; 231 } 232 } 233 234 // Transfer data between memory locations. 235 236 unsigned int 237 Dma_jz4730_channel::transfer(uint32_t source, uint32_t destination, 238 unsigned int count, 239 bool source_increment, bool destination_increment, 240 uint8_t source_width, uint8_t destination_width, 241 uint8_t transfer_unit_size, 242 enum Dma_jz4730_request_type type) 243 { 244 // Ensure an absence of address error and halt conditions globally and in this channel. 245 246 if (error() || halted()) 247 return 0; 248 249 // Ensure an absence of transaction completed and zero transfer count for this channel. 250 251 if (completed() || _regs[Dma_transfer_count]) 252 return 0; 253 254 // Disable the channel. 255 256 _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_channel_enable; 257 258 // Set addresses. 259 260 _regs[Dma_source] = source; 261 _regs[Dma_destination] = destination; 262 263 // Set transfer count to the number of units. 264 265 unsigned int units = count < Dma_transfer_count_mask ? count : Dma_transfer_count_mask; 266 267 _regs[Dma_transfer_count] = units; 268 269 // Set auto-request for memory-to-memory transfers. Otherwise, set the 270 // indicated request type. 271 272 _regs[Dma_request_source] = type; 273 274 // Set control/status fields. 275 // Enable the channel (and peripheral). 276 277 /* NOTE: To be considered... 278 * request detection interval length (currently left as 0) 279 * increments and port widths for external transfers 280 * port width overriding (for AIC...) 281 * transfer mode (currently left as single) 282 */ 283 284 _regs[Dma_control_status] = encode_external_transfer(type) | 285 (source_increment ? Dma_source_address_incr : Dma_source_address_no_incr) | 286 (destination_increment ? Dma_dest_address_incr : Dma_dest_address_no_incr) | 287 encode_source_port_width(source_width) | 288 encode_destination_port_width(destination_width) | 289 encode_transfer_unit_size(transfer_unit_size) | 290 (Dma_trans_mode_single << Dma_trans_mode) | 291 Dma_channel_irq_enable | 292 Dma_channel_enable; 293 294 // Return the number of units to transfer. 295 296 return units; 297 } 298 299 unsigned int 300 Dma_jz4730_channel::wait() 301 { 302 // An interrupt will occur upon completion, the completion flag will be set 303 // and the transfer count will be zero. 304 305 unsigned int remaining = 0; 306 307 do 308 { 309 if (!wait_for_irq(1000000)) 310 printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); 311 312 // Clearing the completion flag will clear the interrupt condition. 313 // Any remaining units must be read before clearing the condition. 314 315 else 316 { 317 remaining = _regs[Dma_transfer_count]; 318 ack_irq(); 319 break; 320 } 321 } 322 while (!error() && !halted() && !completed()); 323 324 // Reset the channel status. 325 326 _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_channel_enable | 327 Dma_trans_completed | Dma_address_error | 328 Dma_trans_halted); 329 _regs[Dma_transfer_count] = 0; 330 331 // Return the number of remaining units. 332 333 return remaining; 334 } 335 336 // Wait indefinitely for an interrupt request, returning true if one was delivered. 337 338 bool 339 Dma_jz4730_channel::wait_for_irq() 340 { 341 if (l4_error(l4_rcv_ep_bind_thread(_irq, get_current_thread(), 0))) 342 return false; 343 344 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && _chip->have_interrupt(_channel); 345 } 346 347 // Wait up to the given timeout (in microseconds) for an interrupt request, 348 // returning true if one was delivered. 349 350 bool 351 Dma_jz4730_channel::wait_for_irq(unsigned int timeout) 352 { 353 if (l4_error(l4_rcv_ep_bind_thread(_irq, get_current_thread(), 0))) 354 return false; 355 356 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))) && _chip->have_interrupt(_channel); 357 } 358 359 // Acknowledge an interrupt condition. 360 361 void 362 Dma_jz4730_channel::ack_irq() 363 { 364 _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_trans_completed; 365 } 366 367 // Return whether a transfer has completed. 368 369 bool 370 Dma_jz4730_channel::completed() 371 { 372 return _regs[Dma_control_status] & Dma_trans_completed ? true : false; 373 } 374 375 // Return whether an address error condition has arisen. 376 377 bool 378 Dma_jz4730_channel::error() 379 { 380 return _regs[Dma_control_status] & Dma_address_error ? true : false; 381 } 382 383 // Return whether a transfer has halted. 384 385 bool 386 Dma_jz4730_channel::halted() 387 { 388 return _regs[Dma_control_status] & Dma_trans_halted ? true : false; 389 } 390 391 392 393 // Initialise the I2C controller. 394 395 Dma_jz4730_chip::Dma_jz4730_chip(l4_addr_t start, l4_addr_t end, 396 Cpm_jz4730_chip *cpm) 397 : _start(start), _end(end), _cpm(cpm) 398 { 399 _regs = new Hw::Mmio_register_block<32>(start); 400 } 401 402 // Enable the peripheral. 403 404 void 405 Dma_jz4730_chip::enable() 406 { 407 // Make sure that the DMA clock is available. 408 409 _cpm->start_clock(Clock_dma); 410 411 // Enable the channel. 412 // NOTE: No configuration is done for channel priority mode. 413 414 _regs[Dma_control] = Dma_control_enable; 415 while (!(_regs[Dma_control] & Dma_control_enable)); 416 } 417 418 // Disable the channel. 419 420 void 421 Dma_jz4730_chip::disable() 422 { 423 _regs[Dma_control] = 0; 424 while (_regs[Dma_control] & Dma_control_enable); 425 } 426 427 // Obtain a channel object. 428 429 Dma_jz4730_channel * 430 Dma_jz4730_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) 431 { 432 if (channel < 6) 433 return new Dma_jz4730_channel(this, channel, _start + 0x20 * channel, irq); 434 else 435 throw -L4_EINVAL; 436 } 437 438 // Return whether an interrupt is pending on the given channel. 439 440 bool 441 Dma_jz4730_chip::have_interrupt(uint8_t channel) 442 { 443 return _regs[Dma_irq_pending] & (1 << (Dma_irq_pending_ch0 - channel)) ? true : false; 444 } 445 446 447 448 // C language interface functions. 449 450 void *jz4730_dma_init(l4_addr_t start, l4_addr_t end, void *cpm) 451 { 452 return (void *) new Dma_jz4730_chip(start, end, static_cast<Cpm_jz4730_chip *>(cpm)); 453 } 454 455 void jz4730_dma_disable(void *dma_chip) 456 { 457 static_cast<Dma_jz4730_chip *>(dma_chip)->disable(); 458 } 459 460 void jz4730_dma_enable(void *dma_chip) 461 { 462 static_cast<Dma_jz4730_chip *>(dma_chip)->enable(); 463 } 464 465 void *jz4730_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq) 466 { 467 return static_cast<Dma_jz4730_chip *>(dma)->get_channel(channel, irq); 468 } 469 470 void jz4730_dma_set_output_polarity(void *dma_channel, enum Dma_jz4730_ext_level polarity) 471 { 472 static_cast<Dma_jz4730_channel *>(dma_channel)->set_output_polarity(polarity); 473 } 474 475 void jz4730_dma_set_end_of_process_mode(void *dma_channel, enum Dma_jz4730_ext_level mode) 476 { 477 static_cast<Dma_jz4730_channel *>(dma_channel)->set_end_of_process_mode(mode); 478 } 479 480 void jz4730_dma_set_output_mode_cycle(void *dma_channel, enum Dma_jz4730_ext_output_mode_cycle cycle) 481 { 482 static_cast<Dma_jz4730_channel *>(dma_channel)->set_output_mode_cycle(cycle); 483 } 484 485 void jz4730_dma_set_req_detect_mode(void *dma_channel, enum Dma_jz4730_ext_req_detect_mode mode) 486 { 487 static_cast<Dma_jz4730_channel *>(dma_channel)->set_req_detect_mode(mode); 488 } 489 490 unsigned int jz4730_dma_transfer(void *dma_channel, 491 uint32_t source, uint32_t destination, 492 unsigned int count, 493 int source_increment, int destination_increment, 494 uint8_t source_width, uint8_t destination_width, 495 uint8_t transfer_unit_size, 496 enum Dma_jz4730_request_type type) 497 { 498 return static_cast<Dma_jz4730_channel *>(dma_channel)->transfer(source, 499 destination, count, source_increment, destination_increment, source_width, 500 destination_width, transfer_unit_size, type); 501 } 502 503 unsigned int jz4730_dma_wait(void *dma_channel) 504 { 505 return static_cast<Dma_jz4730_channel *>(dma_channel)->wait(); 506 }