1 /* 2 * JZ4780 HDMI peripheral support. 3 * 4 * Copyright (C) 2020 Paul Boddie <paul@boddie.org.uk> 5 * 6 * Techniques and operations introduced from the Linux DRM bridge driver for 7 * Synopsys DW-HDMI whose authors are as follows: 8 * 9 * Copyright (C) 2013-2015 Mentor Graphics Inc. 10 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 26 * Boston, MA 02110-1301, USA 27 * 28 * ---- 29 * 30 * Some acronyms: 31 * 32 * CEC (Consumer Electronics Control) is a HDMI device control interface for up 33 * to 15 devices. 34 * 35 * CSC (Colour Space Conversion) is the processing needed to convert from one 36 * representation of colours to another. 37 * 38 * HEAC (HDMI Ethernet and Audio Return Channel) is a combination of HEC (HDMI 39 * Ethernet Channel) which provides a 100Mb/s bidirectional link and ARC (Audio 40 * Return Channel) which permits the consumption of audio data from the device. 41 * 42 * MHL (Mobile High-Definition Link) is an adaptation of HDMI for mobile 43 * devices. 44 * 45 * TMDS (Transition-Minimized Differential Signaling) is the method by which 46 * audio, control and video data are all sent to the device. 47 */ 48 49 #include <l4/devices/hdmi-jz4780.h> 50 #include <l4/devices/hw_mmio_register_block.h> 51 #include <l4/devices/lcd-jz4740-config.h> 52 53 #include <l4/sys/irq.h> 54 #include <l4/sys/rcv_endpoint.h> 55 #include <l4/util/util.h> 56 57 #include <systypes/thread.h> 58 59 /* 60 I2C pins: 61 62 HDMI: PF25/SMB4_SDA/DDCSDA, PF24/SMB4_SCK/DDCSCK 63 64 See: http://mipscreator.imgtec.com/CI20/hardware/board/ci20_jz4780_v2.0.pdf 65 */ 66 67 enum Regs 68 { 69 // Identification. 70 71 Design_id = 0x000, // DESIGN_ID 72 Revision_id = 0x001, // REVISION_ID 73 Product_id0 = 0x002, // PRODUCT_ID0 74 Product_id1 = 0x003, // PRODUCT_ID1 75 Config_id0 = 0x004, // CONFIG_ID0 76 Config_id1 = 0x005, // CONFIG_ID1 77 Config_id2 = 0x006, // CONFIG_ID2 78 Config_id3 = 0x007, // CONFIG_ID3 79 80 // Top-level interrupt control. 81 82 Int_mask = 0x1ff, // MUTE 83 84 // Interrupt status and mask for various functions. 85 86 Fc_int_status0 = 0x100, // FC_STAT0 87 Fc_int_status1 = 0x101, // FC_STAT1 88 Fc_int_status2 = 0x102, // FC_STAT2 89 As_int_status = 0x103, // AS_STAT0 90 Phy_int_status = 0x104, // PHY_STAT0 91 Cec_int_status = 0x106, // CEC_STAT0 92 Vp_int_status = 0x107, // VP_STAT0 93 Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0 94 95 Fc_int_mask0 = 0x180, // MUTE_FC_STAT0 96 Fc_int_mask1 = 0x181, // MUTE_FC_STAT1 97 Fc_int_mask2 = 0x182, // MUTE_FC_STAT2 98 As_int_mask = 0x183, // MUTE_AS_STAT0 99 Phy_int_mask = 0x184, // MUTE_PHY_STAT0 100 Cec_int_mask = 0x186, // MUTE_CEC_STAT0 101 Vp_int_mask = 0x187, // MUTE_VP_STAT0 102 Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0 103 104 // I2C for E-DDC. 105 106 I2c_int_status = 0x105, // I2CM_STAT0 107 I2c_int_mask = 0x185, // MUTE_I2CM_STAT0 108 109 I2c_device_address = 0x7e00, // I2CM_SLAVE 110 I2c_register = 0x7e01, // I2CM_ADDRESS 111 I2c_data_out = 0x7e02, // I2CM_DATAO 112 I2c_data_in = 0x7e03, // I2CM_DATAI 113 I2c_operation = 0x7e04, // I2CM_OPERATION 114 I2c_int_config0 = 0x7e05, // I2CM_INT 115 I2c_int_config1 = 0x7e06, // I2CM_CTLINT 116 I2c_divider = 0x7e07, // I2CM_DIV 117 I2c_segment_address = 0x7e08, // I2CM_SEGADDR 118 I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ 119 I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR 120 121 // I2C for PHY. 122 123 I2c_phy_int_status = 0x108, // I2CMPHY_STAT0 124 I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0 125 126 I2c_phy_device_address = 0x3020, // PHY_I2CM_SLAVE_ADDR 127 I2c_phy_register = 0x3021, // PHY_I2CM_ADDRESS_ADDR 128 I2c_phy_data_out1 = 0x3022, // PHY_I2CM_DATAO_1_ADDR 129 I2c_phy_data_out0 = 0x3023, // PHY_I2CM_DATAO_0_ADDR 130 I2c_phy_data_in1 = 0x3024, // PHY_I2CM_DATAI_1_ADDR 131 I2c_phy_data_in0 = 0x3025, // PHY_I2CM_DATAI_0_ADDR 132 I2c_phy_operation = 0x3026, // PHY_I2CM_OPERATION_ADDR 133 I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR 134 I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR 135 I2c_phy_divider = 0x3029, // PHY_I2CM_DIV_ADDR 136 I2c_phy_software_reset = 0x302a, // PHY_I2CM_SOFTRSTZ_ADDR 137 138 // PHY registers. 139 140 Phy_config = 0x3000, // PHY_CONF0 141 Phy_test0 = 0x3001, // PHY_TST0 142 Phy_test1 = 0x3002, // PHY_TST1 143 Phy_test2 = 0x3003, // PHY_TST2 144 Phy_status = 0x3004, // PHY_STAT0 145 Phy_int_config = 0x3005, // PHY_INT0 146 Phy_mask = 0x3006, // PHY_MASK0 147 Phy_polarity = 0x3007, // PHY_POL0 148 149 // Main controller registers. 150 151 Main_clock_disable = 0x4001, // MC_CLKDIS 152 Main_software_reset = 0x4002, // MC_SWRSTZ 153 Main_flow_control = 0x4004, // MC_FLOWCTRL 154 Main_reset = 0x4005, // MC_PHYRSTZ 155 Main_heac_phy_reset = 0x4007, // MC_HEACPHY_RST 156 157 // Frame composer registers for input video. 158 159 Fc_video_config = 0x1000, // FC_INVIDCONF 160 Fc_horizontal_active_width0 = 0x1001, // FC_INHACTV0 161 Fc_horizontal_active_width1 = 0x1002, // FC_INHACTV1 162 Fc_horizontal_blank_width0 = 0x1003, // FC_INHBLANK0 163 Fc_horizontal_blank_width1 = 0x1004, // FC_INHBLANK1 164 Fc_vertical_active_height0 = 0x1005, // FC_INVACTV0 165 Fc_vertical_active_height1 = 0x1006, // FC_INVACTV1 166 Fc_vertical_blank_height = 0x1007, // FC_INVBLANK 167 168 // Frame composer registers for sync pulses. 169 170 Fc_hsync_delay0 = 0x1008, // FC_HSYNCINDELAY0 171 Fc_hsync_delay1 = 0x1009, // FC_HSYNCINDELAY1 172 Fc_hsync_width0 = 0x100A, // FC_HSYNCINWIDTH0 173 Fc_hsync_width1 = 0x100B, // FC_HSYNCINWIDTH1 174 Fc_vsync_delay = 0x100C, // FC_VSYNCINDELAY 175 Fc_vsync_height = 0x100D, // FC_VSYNCINWIDTH 176 177 // Frame composer registers for video path configuration. 178 179 Fc_control_duration = 0x1011, // FC_CTRLDUR 180 Fc_ex_control_duration = 0x1012, // FC_EXCTRLDUR 181 Fc_ex_control_space = 0x1013, // FC_EXCTRLSPAC 182 Fc_channel0_preamble = 0x1014, // FC_CH0PREAM 183 Fc_channel1_preamble = 0x1015, // FC_CH1PREAM 184 Fc_channel2_preamble = 0x1016, // FC_CH2PREAM 185 186 // Colour space conversion registers. 187 188 Csc_config = 0x4100, // CSC_CFG 189 Csc_scale = 0x4101, // CSC_SCALE 190 191 // HDCP registers. 192 193 Hdcp_config0 = 0x5000, // A_HDCPCFG0 194 Hdcp_config1 = 0x5001, // A_HDCPCFG1 195 Hdcp_video_polarity = 0x5009, // A_VIDPOLCFG 196 197 // Video sample registers. 198 199 Sample_video_config = 0x0200, // TX_INVID0 200 Sample_video_stuffing = 0x0201, // TX_INSTUFFING 201 Sample_gy_data0 = 0x0202, // TX_GYDATA0 202 Sample_gy_data1 = 0x0203, // TX_GYDATA1 203 Sample_rcr_data0 = 0x0204, // TX_RCRDATA0 204 Sample_rcr_data1 = 0x0205, // TX_RCRDATA1 205 Sample_bcb_data0 = 0x0206, // TX_BCBDATA0 206 Sample_bcb_data1 = 0x0207, // TX_BCBDATA1 207 208 // Video packetizer registers. 209 210 Packet_status = 0x0800, // VP_STATUS 211 Packet_pr_cd = 0x0801, // VP_PR_CD 212 Packet_stuffing = 0x0802, // VP_STUFF 213 Packet_remap = 0x0803, // VP_REMAP 214 Packet_config = 0x0804, // VP_CONF 215 }; 216 217 // Identification values. 218 219 enum Product_id_values : uint8_t 220 { 221 Product_id0_transmitter = 0xa0, // PRODUCT_ID0_HDMI_TX 222 223 Product_id1_hdcp = 0xc0, // PRODUCT_ID1_HDCP 224 Product_id1_receiver = 0x02, // PRODUCT_ID1_HDMI_RX 225 Product_id1_transmitter = 0x01, // PRODUCT_ID1_HDMI_TX 226 }; 227 228 // Configuration values. 229 230 enum Config_id_values : uint8_t 231 { 232 Config_id0_i2s = 0x10, // CONFIG0_I2S 233 Config_id0_cec = 0x02, // CONFIG0_CEC 234 235 Config_id1_ahb = 0x01, // CONFIG1_AHB 236 237 Config2_dwc_hdmi_tx_phy = 0x00, // DWC_HDMI_TX_PHY 238 Config2_dwc_mhl_phy_heac = 0xb2, // DWC_MHL_PHY_HEAC 239 Config2_dwc_mhl_phy = 0xc2, // DWC_MHL_PHY 240 Config2_dwc_hdmi_3d_tx_phy_heac = 0xe2, // DWC_HDMI_3D_TX_PHY_HEAC 241 Config2_dwc_hdmi_3d_tx_phy = 0xf2, // DWC_HDMI_3D_TX_PHY 242 Config2_dwc_hdmi20_tx_phy = 0xf3, // DWC_HDMI20_TX_PHY 243 Config2_vendor_phy = 0xfe, // VENDOR_PHY 244 245 Config_id3_ahb_audio_dma = 0x02, // CONFIG3_AHBAUDDMA 246 Config_id3_gp_audio = 0x01, // CONFIG3_GPAUD 247 }; 248 249 // Status and mask bits. 250 251 enum Int_mask_bits : uint8_t 252 { 253 Int_mask_wakeup = 0x02, 254 Int_mask_all = 0x01, 255 }; 256 257 // I2C status and mask bits, also for PHY I2C. 258 259 enum I2c_int_status_bits : uint8_t 260 { 261 I2c_int_status_done = 0x02, 262 I2c_int_status_error = 0x01, 263 }; 264 265 // I2C operation bits. 266 267 enum I2c_operation_bits : uint8_t 268 { 269 I2c_operation_write = 0x10, 270 I2c_operation_segment_read = 0x02, // not PHY I2C 271 I2c_operation_read = 0x01, 272 }; 273 274 // Device addresses. 275 276 enum I2c_phy_device_addresses : uint8_t 277 { 278 I2c_phy_device_phy_gen2 = 0x69, // PHY_I2CM_SLAVE_ADDR_PHY_GEN2 279 I2c_phy_device_phy_heac = 0x49, // PHY_I2CM_SLAVE_ADDR_HEAC_PHY 280 }; 281 282 // Device registers. 283 284 enum I2c_phy_device_registers : uint8_t 285 { 286 I2c_phy_3d_tx_clock_cal_ctrl = 0x05, // 3D_TX_PHY_CKCALCTRL 287 I2c_phy_3d_tx_cpce_ctrl = 0x06, // 3D_TX_PHY_CPCE_CTRL 288 I2c_phy_3d_tx_clock_symbol_ctrl = 0x09, // 3D_TX_PHY_CKSYMTXCTRL 289 I2c_phy_3d_tx_vlevel_ctrl = 0x0e, // 3D_TX_PHY_VLEVCTRL 290 I2c_phy_3d_tx_curr_ctrl = 0x10, // 3D_TX_PHY_CURRCTRL 291 I2c_phy_3d_tx_pll_phby_ctrl = 0x13, // 3D_TX_PHY_PLLPHBYCTRL 292 I2c_phy_3d_tx_gmp_ctrl = 0x15, // 3D_TX_PHY_GMPCTRL 293 I2c_phy_3d_tx_msm_ctrl = 0x17, // 3D_TX_PHY_MSM_CTRL 294 I2c_phy_3d_tx_term = 0x19, // 3D_TX_PHY_TXTERM 295 }; 296 297 // PHY I2C register values. 298 299 enum Msm_ctrl_bits : uint16_t 300 { 301 Msm_ctrl_clock_output_select_fb = 1 << 3, // 3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK 302 }; 303 304 enum Clock_cal_ctrl_bits : uint16_t 305 { 306 Clock_cal_ctrl_override = 1 << 15, // 3D_TX_PHY_CKCALCTRL_OVERRIDE 307 }; 308 309 // Interrupt configuration bits, also for PHY I2C. 310 311 enum I2c_int_config0_bits : uint8_t 312 { 313 I2c_int_config0_done_polarity = 0x08, 314 I2c_int_config0_done_mask = 0x04, 315 }; 316 317 enum I2c_int_config1_bits : uint8_t 318 { 319 I2c_int_config1_nack_polarity = 0x80, 320 I2c_int_config1_nack_mask = 0x40, 321 I2c_int_config1_arb_polarity = 0x08, 322 I2c_int_config1_arb_mask = 0x04, 323 }; 324 325 // PHY configuration values. 326 327 enum Phy_config_bits : uint8_t 328 { 329 Phy_config_powerdown_disable = 0x80, // PHY_CONF0_PDZ_MASK 330 Phy_config_tmds = 0x40, // PHY_CONF0_ENTMDS_MASK 331 Phy_config_svsret = 0x20, // PHY_CONF0_SVSRET_MASK 332 Phy_config_gen2_powerdown = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK 333 Phy_config_gen2_tx_power = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK 334 Phy_config_gen2_hotplug_detect_rx_sense = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK 335 Phy_config_select_data_enable_polarity = 0x02, // PHY_CONF0_SELDATAENPOL_MASK 336 Phy_config_select_interface_control = 0x01, // PHY_CONF0_SELDIPIF_MASK 337 }; 338 339 enum Phy_test_bits : uint8_t 340 { 341 Phy_test0_clear_mask = 0x20, // PHY_TST0_TSTCLR_MASK 342 Phy_test0_enable_mask = 0x10, // PHY_TST0_TSTEN_MASK 343 Phy_test0_clock_mask = 0x01, // PHY_TST0_TSTCLK_MASK 344 }; 345 346 // PHY status and mask values. 347 348 enum Phy_status_bits : uint8_t 349 { 350 Phy_status_all = 0xf3, 351 Phy_status_rx_sense_all = 0xf0, 352 Phy_status_rx_sense3 = 0x80, // PHY_RX_SENSE3 353 Phy_status_rx_sense2 = 0x40, // PHY_RX_SENSE2 354 Phy_status_rx_sense1 = 0x20, // PHY_RX_SENSE1 355 Phy_status_rx_sense0 = 0x10, // PHY_RX_SENSE0 356 Phy_status_hotplug_detect = 0x02, // PHY_HPD 357 Phy_status_tx_phy_lock = 0x01, // PHY_TX_PHY_LOCK 358 Phy_status_none = 0, 359 }; 360 361 // PHY interrupt status and mask values. 362 363 enum Phy_int_status_bits : uint8_t 364 { 365 Phy_int_status_all = 0x3f, 366 Phy_int_status_rx_sense_all = 0x3c, 367 Phy_int_status_rx_sense3 = 0x20, // IH_PHY_STAT0_RX_SENSE3 368 Phy_int_status_rx_sense2 = 0x10, // IH_PHY_STAT0_RX_SENSE2 369 Phy_int_status_rx_sense1 = 0x08, // IH_PHY_STAT0_RX_SENSE1 370 Phy_int_status_rx_sense0 = 0x04, // IH_PHY_STAT0_RX_SENSE0 371 Phy_int_status_tx_phy_lock = 0x02, // IH_PHY_STAT0_TX_PHY_LOCK 372 Phy_int_status_hotplug_detect = 0x01, // IH_PHY_STAT0_HPD 373 Phy_int_status_none = 0, 374 }; 375 376 // PHY main register values. 377 378 enum Main_heac_phy_reset_bits : uint8_t 379 { 380 Main_heac_phy_reset_assert = 0x01, // MC_HEACPHY_RST_ASSERT 381 }; 382 383 enum Main_flow_control_bits : uint8_t 384 { 385 Main_flow_control_csc_active = 0x01, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH 386 Main_flow_control_csc_inactive = 0x00, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS 387 }; 388 389 enum Main_clock_disable_bits : uint8_t 390 { 391 Main_clock_disable_hdcp = 0x40, // MC_CLKDIS_HDCPCLK_DISABLE 392 Main_clock_disable_cec = 0x20, // MC_CLKDIS_CECCLK_DISABLE 393 Main_clock_disable_csc = 0x10, // MC_CLKDIS_CSCCLK_DISABLE 394 Main_clock_disable_audio = 0x08, // MC_CLKDIS_AUDCLK_DISABLE 395 Main_clock_disable_prep = 0x04, // MC_CLKDIS_PREPCLK_DISABLE 396 Main_clock_disable_tmds = 0x02, // MC_CLKDIS_TMDSCLK_DISABLE 397 Main_clock_disable_pixel = 0x01, // MC_CLKDIS_PIXELCLK_DISABLE 398 }; 399 400 enum Main_software_reset_bits : uint8_t 401 { 402 Main_software_reset_tmds = 0x02, // MC_SWRSTZ_TMDSSWRST_REQ 403 }; 404 405 // Frame composer values. 406 407 enum Fc_video_config_bits : uint8_t 408 { 409 Fc_video_config_hdcp_keepout_active = 0x80, // FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE 410 Fc_video_config_hdcp_keepout_inactive = 0x00, // FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE 411 Fc_video_config_vsync_active_high = 0x40, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH 412 Fc_video_config_vsync_active_low = 0x00, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW 413 Fc_video_config_hsync_active_high = 0x20, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH 414 Fc_video_config_hsync_active_low = 0x00, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW 415 Fc_video_config_data_enable_active_high = 0x10, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH 416 Fc_video_config_data_enable_active_low = 0x00, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW 417 Fc_video_config_hdmi_mode = 0x08, // FC_INVIDCONF_DVI_MODEZ_HDMI_MODE 418 Fc_video_config_dvi_mode = 0x00, // FC_INVIDCONF_DVI_MODEZ_DVI_MODE 419 Fc_video_config_osc_active_high = 0x02, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH 420 Fc_video_config_osc_active_low = 0x00, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW 421 Fc_video_config_interlaced = 0x01, // FC_INVIDCONF_IN_I_P_INTERLACED 422 Fc_video_config_progressive = 0x00, // FC_INVIDCONF_IN_I_P_PROGRESSIVE 423 }; 424 425 enum Fc_int_status2_bits : uint8_t 426 { 427 Fc_int_status2_overflow = 0x03, // FC_STAT2_OVERFLOW_MASK 428 Fc_int_status2_overflow_low = 0x02, // FC_STAT2_LOW_PRIORITY_OVERFLOW 429 Fc_int_status2_overflow_high = 0x01 // FC_STAT2_HIGH_PRIORITY_OVERFLOW, 430 }; 431 432 // Colour space conversion values. 433 434 enum Csc_config_bits : uint8_t 435 { 436 Csc_config_interpolation_mask = 0x30, // CSC_CFG_INTMODE_MASK 437 Csc_config_interpolation_disable = 0x00, // CSC_CFG_INTMODE_DISABLE 438 Csc_config_interpolation_form1 = 0x10, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 439 Csc_config_interpolation_form2 = 0x20, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 440 Csc_config_decimation_mask = 0x3, // CSC_CFG_DECMODE_MASK 441 Csc_config_decimation_disable = 0x0, // CSC_CFG_DECMODE_DISABLE 442 Csc_config_decimation_form1 = 0x1, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 443 Csc_config_decimation_form2 = 0x2, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 444 Csc_config_decimation_form3 = 0x3, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 445 }; 446 447 enum Csc_scale_bits : uint8_t 448 { 449 Csc_scale_colour_depth_mask = 0xf0, // CSC_SCALE_CSC_COLORDE_PTH_MASK 450 Csc_scale_colour_depth_24bpp = 0x00, // CSC_SCALE_CSC_COLORDE_PTH_24BPP 451 Csc_scale_colour_depth_30bpp = 0x50, // CSC_SCALE_CSC_COLORDE_PTH_30BPP 452 Csc_scale_colour_depth_36bpp = 0x60, // CSC_SCALE_CSC_COLORDE_PTH_36BPP 453 Csc_scale_colour_depth_48bpp = 0x70, // CSC_SCALE_CSC_COLORDE_PTH_48BPP 454 Csc_scale_mask = 0x03, // CSC_SCALE_CSCSCALE_MASK 455 }; 456 457 // HDCP register values. 458 459 enum Hdcp_config0_bits : uint8_t 460 { 461 Hdcp_config0_rxdetect_enable = 0x4, // A_HDCPCFG0_RXDETECT_ENABLE 462 }; 463 464 enum Hdcp_config1_bits : uint8_t 465 { 466 Hdcp_config1_encryption_disable = 0x2, // A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE 467 }; 468 469 enum Hdcp_video_polarity_bits : uint8_t 470 { 471 Hdcp_video_polarity_data_enable_active_high = 0x10, // A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH 472 }; 473 474 // Video sample register values. 475 476 enum Sample_video_config_bits : uint8_t 477 { 478 Sample_video_config_data_enable_active = 0x80, // TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE 479 Sample_video_config_mapping_mask = 0x1f, // TX_INVID0_VIDEO_MAPPING_MASK 480 }; 481 482 enum Sample_video_stuffing_bits : uint8_t 483 { 484 Sample_video_stuffing_bdb_data = 0x04, // TX_INSTUFFING_BDBDATA_STUFFING_ENABLE 485 Sample_video_stuffing_rcr_data = 0x02, // TX_INSTUFFING_RCRDATA_STUFFING_ENABLE 486 Sample_video_stuffing_gy_data = 0x01, // TX_INSTUFFING_GYDATA_STUFFING_ENABLE 487 }; 488 489 // Video packetizer register values. 490 491 enum Packet_stuffing_bits : uint8_t 492 { 493 Packet_stuffing_default_phase = 0x20, // VP_STUFF_IDEFAULT_PHASE_MASK 494 Packet_stuffing_ifix_pp_to_last = 0x10, // VP_STUFF_IFIX_PP_TO_LAST_MASK 495 Packet_stuffing_icx = 0x08, // VP_STUFF_ICX_GOTO_P0_ST_MASK 496 Packet_stuffing_ycc422 = 0x04, // VP_STUFF_YCC422_STUFFING_STUFFING_MODE 497 Packet_stuffing_pp = 0x02, // VP_STUFF_PP_STUFFING_STUFFING_MODE 498 Packet_stuffing_pr = 0x01, // VP_STUFF_PR_STUFFING_STUFFING_MODE 499 }; 500 501 enum Packet_config_bits : uint8_t 502 { 503 Packet_config_bypass_enable = 0x40, // VP_CONF_BYPASS_EN_ENABLE 504 Packet_config_pp_enable = 0x20, // VP_CONF_PP_EN_ENABLE 505 Packet_config_pr_enable = 0x10, // VP_CONF_PR_EN_ENABLE 506 Packet_config_ycc422_enable = 0x8, // VP_CONF_YCC422_EN_ENABLE 507 Packet_config_bypass_select_packetizer = 0x4, // VP_CONF_BYPASS_SELECT_VID_PACKETIZER 508 Packet_config_output_selector_mask = 0x3, // VP_CONF_OUTPUT_SELECTOR_MASK 509 Packet_config_output_selector_bypass = 0x3, // VP_CONF_OUTPUT_SELECTOR_BYPASS 510 Packet_config_output_selector_ycc422 = 0x1, // VP_CONF_OUTPUT_SELECTOR_YCC422 511 Packet_config_output_selector_pp = 0x0, // VP_CONF_OUTPUT_SELECTOR_PP 512 }; 513 514 enum Packet_remap_bits : uint8_t 515 { 516 Packet_remap_mask = 0x3, // VP_REMAP_MASK 517 Packet_remap_ycc422_24bit = 0x2, // VP_REMAP_YCC422_24bit 518 Packet_remap_ycc422_20bit = 0x1, // VP_REMAP_YCC422_20bit 519 Packet_remap_ycc422_16bit = 0x0, // VP_REMAP_YCC422_16bit 520 }; 521 522 enum Packet_pr_cd_bits : uint8_t 523 { 524 Packet_pr_cd_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK 525 Packet_pr_cd_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET 526 Packet_pr_cd_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK 527 Packet_pr_cd_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET 528 }; 529 530 531 532 // PHY capabilities. 533 534 static const Phy_capabilities phy_capabilities[] = { 535 // name gen svsret configure 536 {Config2_dwc_hdmi_tx_phy, "DWC_HDMI_TX_PHY", 1, false, false}, 537 {Config2_dwc_mhl_phy_heac, "DWC_MHL_PHY_HEAC", 2, true, true}, 538 {Config2_dwc_mhl_phy, "DWC_MHL_PHY", 2, true, true}, 539 {Config2_dwc_hdmi_3d_tx_phy_heac, "DWC_HDMI_3D_TX_PHY_HEAC", 2, false, true}, 540 {Config2_dwc_hdmi_3d_tx_phy, "DWC_HDMI_3D_TX_PHY", 2, false, true}, 541 {Config2_dwc_hdmi20_tx_phy, "DWC_HDMI20_TX_PHY", 2, true, true}, 542 {0, "Vendor PHY", 0, false, false}, 543 }; 544 545 546 547 // PHY configuration, adopting the Linux driver's tables of values. 548 549 static const struct Phy_mpll_config phy_mpll_config[] = { 550 // 8bpc 10bpc 12bpc 551 // pixelclock cpce gmp cpce gmp cpce gmp 552 { 45250000, { {0x01e0, 0x0000}, {0x21e1, 0x0000}, {0x41e2, 0x0000} } }, 553 { 92500000, { {0x0140, 0x0005}, {0x2141, 0x0005}, {0x4142, 0x0005} } }, 554 { 148500000, { {0x00a0, 0x000a}, {0x20a1, 0x000a}, {0x40a2, 0x000a} } }, 555 { 216000000, { {0x00a0, 0x000a}, {0x2001, 0x000f}, {0x4002, 0x000f} } }, 556 { ~0UL, { {0x0000, 0x0000}, {0x0000, 0x0000}, {0x0000, 0x0000} } } 557 }; 558 559 static const struct Phy_curr_ctrl phy_curr_ctrl[] = { 560 // pixelclock 8bpc 10bpc 12bpc 561 { 54000000, {0x091c, 0x091c, 0x06dc} }, 562 { 58400000, {0x091c, 0x06dc, 0x06dc} }, 563 { 72000000, {0x06dc, 0x06dc, 0x091c} }, 564 { 74250000, {0x06dc, 0x0b5c, 0x091c} }, 565 { 118800000, {0x091c, 0x091c, 0x06dc} }, 566 { 216000000, {0x06dc, 0x0b5c, 0x091c} }, 567 { ~0UL, {0x0000, 0x0000, 0x0000} } 568 }; 569 570 static const struct Phy_config phy_config[] = { 571 // pixelclock symbol term vlevel 572 { 216000000, 0x800d, 0x0005, 0x01ad}, 573 { ~0UL, 0x0000, 0x0000, 0x0000} 574 }; 575 576 577 578 // Initialise the HDMI peripheral. 579 580 Hdmi_jz4780_chip::Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, 581 l4_cap_idx_t irq, 582 struct Jz4740_lcd_panel *panel) 583 : _start(start), _end(end), _irq(irq), _panel(panel) 584 { 585 // 8-bit registers with 2-bit address shifting. 586 587 _regs = new Hw::Mmio_register_block<8>(start, 2); 588 589 // Initialise I2C state for DDC. 590 591 _segment_read = false; 592 _device_register = 0; 593 594 // Initialise I2C state for PHY initialisation. 595 596 _phy_device_register = 0; 597 598 // Initialise identifying details and capabilities of the hardware. 599 600 get_identification(); 601 602 // Reset interrupts to a minimal, enabled state. 603 604 irq_init(); 605 606 // Set up DDC and PHY communication. 607 608 i2c_init(I2c_software_reset, I2c_divider, I2c_int_config0, I2c_int_config1, 609 I2c_int_status, I2c_int_mask); 610 i2c_init(I2c_phy_software_reset, I2c_phy_divider, I2c_phy_int_config0, I2c_phy_int_config1, 611 I2c_phy_int_status, I2c_phy_int_mask); 612 613 // Enable PHY interrupts. 614 615 phy_irq_init(); 616 } 617 618 // Pixel clock frequency calculation. 619 620 unsigned long Hdmi_jz4780_chip::get_pixelclock() 621 { 622 return _pixelclock; 623 624 /* Calculated frequency, which may not be the actual pixelclock frequency... 625 626 return (_panel->line_start + _panel->width + _panel->line_end + _panel->hsync) * 627 (_panel->frame_start + _panel->height + _panel->frame_end + _panel->vsync) * 628 _panel->frame_rate; 629 */ 630 } 631 632 633 634 // Update a register by enabling/setting or disabling/clearing the given bits. 635 636 void Hdmi_jz4780_chip::reg_update(uint32_t reg, uint32_t bits, bool enable) 637 { 638 if (enable) 639 _regs[reg] = _regs[reg] | bits; 640 else 641 _regs[reg] = _regs[reg] & ~bits; 642 } 643 644 // Update a field. The bits must be shifted to coincide with the mask. 645 646 void Hdmi_jz4780_chip::reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits) 647 { 648 _regs[reg] = (_regs[reg] & ~(mask)) | (bits & mask); 649 } 650 651 void Hdmi_jz4780_chip::reg_fill_field(uint32_t reg, uint32_t mask) 652 { 653 _regs[reg] = _regs[reg] | mask; 654 } 655 656 657 658 // Chipset querying. 659 660 void Hdmi_jz4780_chip::get_identification() 661 { 662 _version = (_regs[Design_id] << 8) | _regs[Revision_id]; 663 _phy_type = _regs[Config_id2]; 664 665 // Initialise a member to any matching capabilities or leave it as the "null" 666 // entry. 667 668 _phy_def = phy_capabilities; 669 670 while (_phy_def->gen && (_phy_def->type != _phy_type)) 671 _phy_def++; 672 } 673 674 void Hdmi_jz4780_chip::get_version(uint8_t *major, uint16_t *minor) 675 { 676 *major = (_version >> 12) & 0xfff; 677 *minor = _version & 0xfff; 678 } 679 680 void Hdmi_jz4780_chip::get_phy_capabilities(const struct Phy_capabilities **phy_def) 681 { 682 *phy_def = _phy_def; 683 } 684 685 686 687 // Initialisation. 688 689 void Hdmi_jz4780_chip::irq_init() 690 { 691 // Disable interrupts. 692 693 _regs[Int_mask] = _regs[Int_mask] | (Int_mask_wakeup | Int_mask_all); 694 695 // Mask all interrupts. 696 697 _regs[Fc_int_mask0] = 0xff; 698 _regs[Fc_int_mask1] = 0xff; 699 _regs[Fc_int_mask2] = 0xff; 700 _regs[As_int_mask] = 0xff; 701 _regs[Phy_int_mask] = 0xff; 702 _regs[I2c_int_mask] = 0xff; 703 _regs[I2c_phy_int_mask] = 0xff; 704 _regs[Cec_int_mask] = 0xff; 705 _regs[Vp_int_mask] = 0xff; 706 _regs[Ahb_dma_audio_int_mask] = 0xff; 707 708 // Enable interrupts. 709 710 _regs[Int_mask] = _regs[Int_mask] & ~(Int_mask_wakeup | Int_mask_all); 711 } 712 713 void Hdmi_jz4780_chip::phy_irq_init() 714 { 715 // Set PHY interrupt polarities. 716 717 _regs[Phy_polarity] = Phy_status_all; 718 719 // Enable/unmask second-level interrupts. 720 721 _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_all); 722 723 // Clear pending interrupts. 724 725 _regs[Phy_int_status] = Phy_int_status_all; 726 727 // Enable/unmask interrupts. 728 729 _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_all); 730 } 731 732 733 734 // I2C support. 735 736 void Hdmi_jz4780_chip::i2c_init(uint32_t reset, uint32_t divider, 737 uint32_t config0, uint32_t config1, 738 uint32_t status, uint32_t mask) 739 { 740 // Software reset. 741 742 _regs[reset] = 0; 743 744 // Standard mode (100kHz). 745 746 _regs[divider] = 0; 747 748 // Set interrupt polarities. 749 750 _regs[config0] = I2c_int_config0_done_polarity; 751 _regs[config1] = I2c_int_config1_nack_polarity | I2c_int_config1_arb_polarity; 752 753 // Clear and mask/mute interrupts. 754 755 _regs[status] = I2c_int_status_done | I2c_int_status_error; 756 _regs[mask] = I2c_int_status_done | I2c_int_status_error; 757 } 758 759 long Hdmi_jz4780_chip::i2c_wait(uint32_t status) 760 { 761 long err; 762 uint8_t int_status; 763 l4_msgtag_t tag; 764 765 err = l4_error(l4_rcv_ep_bind_thread(_irq, get_current_thread(), 0)); 766 767 if (err) 768 return err; 769 770 do 771 { 772 tag = l4_irq_receive(_irq, L4_IPC_NEVER); 773 774 err = l4_ipc_error(tag, l4_utcb()); 775 if (err) 776 return err; 777 778 int_status = _regs[status]; 779 780 // Test for an error condition. 781 782 if (int_status & I2c_int_status_error) 783 return -L4_EIO; 784 785 // Acknowledge the interrupt. 786 787 _regs[status] = int_status; 788 789 } while (!(int_status & I2c_int_status_done)); 790 791 return L4_EOK; 792 } 793 794 int Hdmi_jz4780_chip::i2c_read(uint8_t *buf, unsigned int length) 795 { 796 unsigned int i; 797 long err; 798 799 // Unmask interrupts. 800 801 _regs[I2c_int_mask] = 0; 802 803 for (i = 0; i < length; i++) 804 { 805 // Increment the device register. 806 807 _regs[I2c_register] = _device_register++; 808 _regs[I2c_operation] = _segment_read ? I2c_operation_segment_read 809 : I2c_operation_read; 810 811 // Wait and then read. 812 813 err = i2c_wait(I2c_int_status); 814 if (err) 815 break; 816 817 buf[i] = _regs[I2c_data_in]; 818 } 819 820 // Mask interrupts again. 821 822 _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error; 823 824 return i; 825 } 826 827 int Hdmi_jz4780_chip::i2c_phy_write(uint8_t address, uint16_t value) 828 { 829 i2c_phy_set_address(address); 830 return i2c_phy_write(&value, 1); 831 } 832 833 int Hdmi_jz4780_chip::i2c_phy_write(uint16_t *buf, unsigned int length) 834 { 835 unsigned int i; 836 long err; 837 838 // Unmask interrupts. 839 840 _regs[I2c_phy_int_mask] = 0; 841 842 for (i = 0; i < length; i++) 843 { 844 // Increment the device register. 845 846 _regs[I2c_phy_register] = _device_register++; 847 _regs[I2c_phy_operation] = I2c_operation_write; 848 849 // Write and then wait. 850 851 _regs[I2c_phy_data_out1] = (buf[i] >> 8) & 0xff; 852 _regs[I2c_phy_data_out0] = buf[i] & 0xff; 853 854 err = i2c_wait(I2c_phy_int_status); 855 if (err) 856 break; 857 } 858 859 // Mask interrupts again. 860 861 _regs[I2c_phy_int_mask] = I2c_int_status_done | I2c_int_status_error; 862 863 return i; 864 } 865 866 void Hdmi_jz4780_chip::i2c_set_address(uint8_t address) 867 { 868 _regs[I2c_device_address] = address; 869 _segment_read = false; 870 i2c_set_register(0); 871 } 872 873 void Hdmi_jz4780_chip::i2c_phy_set_address(uint8_t address) 874 { 875 // The Linux drivers seem to set the clear field when changing the PHY device 876 // address, presumably because some manual says so. 877 878 _regs[Phy_test0] = _regs[Phy_test0] | Phy_test0_clear_mask; 879 _regs[I2c_phy_device_address] = address; 880 _regs[Phy_test0] = _regs[Phy_test0] & ~Phy_test0_clear_mask; 881 882 i2c_phy_set_register(0); 883 } 884 885 void Hdmi_jz4780_chip::i2c_set_segment(uint8_t segment) 886 { 887 _regs[I2c_segment_address] = 0x30; 888 _regs[I2c_segment_pointer] = segment; 889 _segment_read = true; 890 i2c_set_register(0); 891 } 892 893 void Hdmi_jz4780_chip::i2c_set_register(uint8_t device_register) 894 { 895 _device_register = device_register; 896 } 897 898 void Hdmi_jz4780_chip::i2c_phy_set_register(uint8_t device_register) 899 { 900 _phy_device_register = device_register; 901 } 902 903 904 905 // PHY operations. 906 907 void Hdmi_jz4780_chip::phy_enable_powerdown(bool enable) 908 { 909 reg_update(Phy_config, Phy_config_powerdown_disable, !enable); 910 } 911 912 void Hdmi_jz4780_chip::phy_enable_tmds(bool enable) 913 { 914 reg_update(Phy_config, Phy_config_tmds, enable); 915 } 916 917 void Hdmi_jz4780_chip::phy_enable_svsret(bool enable) 918 { 919 reg_update(Phy_config, Phy_config_svsret, enable); 920 } 921 922 void Hdmi_jz4780_chip::phy_enable_gen2_powerdown(bool enable) 923 { 924 reg_update(Phy_config, Phy_config_gen2_powerdown, enable); 925 } 926 927 void Hdmi_jz4780_chip::phy_enable_gen2_tx_power(bool enable) 928 { 929 reg_update(Phy_config, Phy_config_gen2_tx_power, enable); 930 } 931 932 void Hdmi_jz4780_chip::phy_enable_interface(bool enable) 933 { 934 reg_update(Phy_config, Phy_config_select_data_enable_polarity, enable); 935 reg_update(Phy_config, Phy_config_select_interface_control, !enable); 936 } 937 938 // Configure the PHY. Various things not supported by the JZ4780 PHY are ignored 939 // such as the TDMS clock ratio (dependent on HDMI 2 and content scrambling). 940 941 long Hdmi_jz4780_chip::phy_configure() 942 { 943 long err; 944 945 phy_power_off(); 946 947 if (_phy_def->svsret) 948 phy_enable_svsret(true); 949 950 phy_reset(); 951 952 _regs[Main_heac_phy_reset] = Main_heac_phy_reset_assert; 953 954 i2c_phy_set_address(I2c_phy_device_phy_gen2); 955 956 if (_phy_def->configure) 957 { 958 err = phy_configure_specific(); 959 if (err) 960 return err; 961 } 962 963 // NOTE: TMDS clock delay here in Linux driver. 964 965 phy_power_on(); 966 967 return L4_EOK; 968 } 969 970 // Configure for the JZ4780 specifically. 971 972 long Hdmi_jz4780_chip::phy_configure_specific() 973 { 974 const struct Phy_mpll_config *m = phy_mpll_config; 975 const struct Phy_curr_ctrl *c = phy_curr_ctrl; 976 const struct Phy_config *p = phy_config; 977 unsigned long pixelclock = get_pixelclock(); 978 979 // Find MPLL, CURR_CTRL and PHY configuration settings appropriate for the 980 // pixel clock frequency. 981 982 while (m->pixelclock && (pixelclock > m->pixelclock)) 983 m++; 984 985 while (c->pixelclock && (pixelclock > c->pixelclock)) 986 c++; 987 988 while (p->pixelclock && (pixelclock > p->pixelclock)) 989 p++; 990 991 if (!m->pixelclock || !c->pixelclock || !p->pixelclock) 992 return -L4_EINVAL; 993 994 // Using values for 8bpc from the tables. 995 996 // Initialise MPLL. 997 998 i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, m->res[Phy_resolution_8bpc].cpce); 999 i2c_phy_write(I2c_phy_3d_tx_gmp_ctrl, m->res[Phy_resolution_8bpc].gmp); 1000 1001 // Initialise CURRCTRL. 1002 1003 i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, c->curr[Phy_resolution_8bpc]); 1004 1005 // Initialise PHY_CONFIG. 1006 1007 i2c_phy_write(I2c_phy_3d_tx_pll_phby_ctrl, 0); 1008 i2c_phy_write(I2c_phy_3d_tx_msm_ctrl, Msm_ctrl_clock_output_select_fb); 1009 1010 i2c_phy_write(I2c_phy_3d_tx_term, p->term); 1011 i2c_phy_write(I2c_phy_3d_tx_clock_symbol_ctrl, p->symbol); 1012 i2c_phy_write(I2c_phy_3d_tx_vlevel_ctrl, p->vlevel); 1013 1014 // Override and disable clock termination. 1015 1016 i2c_phy_write(I2c_phy_3d_tx_clock_cal_ctrl, Clock_cal_ctrl_override); 1017 1018 return L4_EOK; 1019 } 1020 1021 long Hdmi_jz4780_chip::phy_init() 1022 { 1023 long err; 1024 int i; 1025 1026 // Initialisation repeated for HDMI PHY specification reasons. 1027 1028 for (i = 0; i < 2; i++) 1029 { 1030 phy_enable_interface(true); 1031 err = phy_configure(); 1032 if (err) 1033 return err; 1034 } 1035 1036 return L4_EOK; 1037 } 1038 1039 void Hdmi_jz4780_chip::phy_reset() 1040 { 1041 _regs[Main_reset] = 1; 1042 _regs[Main_reset] = 0; 1043 } 1044 1045 void Hdmi_jz4780_chip::phy_power_off() 1046 { 1047 if (_phy_def && (_phy_def->gen == 1)) 1048 { 1049 phy_enable_tmds(false); 1050 phy_enable_powerdown(true); 1051 return; 1052 } 1053 1054 phy_enable_gen2_tx_power(false); 1055 1056 wait_for_tx_phy_lock(0); 1057 1058 phy_enable_gen2_powerdown(true); 1059 } 1060 1061 void Hdmi_jz4780_chip::phy_power_on() 1062 { 1063 if (_phy_def && (_phy_def->gen == 1)) 1064 { 1065 phy_enable_powerdown(false); 1066 phy_enable_tmds(false); 1067 phy_enable_tmds(true); 1068 return; 1069 } 1070 1071 phy_enable_gen2_tx_power(true); 1072 phy_enable_gen2_powerdown(false); 1073 1074 wait_for_tx_phy_lock(1); 1075 } 1076 1077 1078 1079 // Hotplug detection. 1080 1081 bool Hdmi_jz4780_chip::connected() 1082 { 1083 return (_regs[Phy_status] & Phy_status_hotplug_detect) != 0; 1084 } 1085 1086 long Hdmi_jz4780_chip::wait_for_connection() 1087 { 1088 return wait_for_phy_irq(Phy_int_status_hotplug_detect, Phy_status_hotplug_detect, 1089 Phy_status_hotplug_detect); 1090 } 1091 1092 // General PHY interrupt handling. 1093 1094 long Hdmi_jz4780_chip::wait_for_phy_irq(uint32_t int_status_flags, 1095 uint32_t status_flags, 1096 uint32_t status_values) 1097 { 1098 long err; 1099 uint8_t int_status, status; 1100 uint8_t status_unchanged = ~(status_values) & status_flags; 1101 l4_msgtag_t tag; 1102 1103 do 1104 { 1105 tag = l4_irq_receive(_irq, L4_IPC_NEVER); 1106 1107 err = l4_ipc_error(tag, l4_utcb()); 1108 if (err) 1109 return err; 1110 1111 // Obtain the details. 1112 1113 int_status = _regs[Phy_int_status]; 1114 status = _regs[Phy_status]; 1115 1116 // Acknowledge the interrupt. 1117 1118 _regs[Phy_int_status] = int_status_flags; 1119 1120 // Continue without a handled event. 1121 // An event is handled when detected and when the status differs from 1122 // the unchanged state. 1123 1124 } while (!((int_status & int_status_flags) && 1125 ((status & status_flags) ^ status_unchanged))); 1126 1127 return L4_EOK; 1128 } 1129 1130 // Wait for TX_PHY_LOCK to become high or low. 1131 1132 long Hdmi_jz4780_chip::wait_for_tx_phy_lock(int level) 1133 { 1134 if (!!(_regs[Phy_status] & Phy_status_tx_phy_lock) == level) 1135 return L4_EOK; 1136 1137 return wait_for_phy_irq(Phy_int_status_tx_phy_lock, Phy_status_tx_phy_lock, 1138 level ? Phy_status_tx_phy_lock : Phy_status_none); 1139 } 1140 1141 1142 1143 // Output setup operations. 1144 1145 long Hdmi_jz4780_chip::enable(unsigned long pixelclock) 1146 { 1147 _pixelclock = pixelclock; 1148 1149 // Disable frame composer overflow interrupts. 1150 1151 enable_overflow_irq(false); 1152 1153 // NOTE: Here, CEA modes are normally detected and thus the output encoding. 1154 // NOTE: Instead, a fixed RGB output encoding and format is used. 1155 // NOTE: Meanwhile, the input encoding and format will also be fixed to a RGB 1156 // NOTE: representation. 1157 1158 // _bits_per_channel = 8; 1159 // _data_enable_polarity = true; 1160 1161 // HDMI initialisation "step B.1": video frame initialisation. 1162 1163 frame_init(); 1164 1165 // HDMI initialisation "step B.2": PHY initialisation. 1166 1167 long err = phy_init(); 1168 if (err) 1169 return err; 1170 1171 // HDMI initialisation "step B.3": video signal initialisation. 1172 1173 data_path_init(); 1174 1175 // With audio, various clock updates are needed. 1176 1177 // NOTE: DVI mode is being assumed for now, for simplicity. 1178 1179 // In non-DVI mode, the AVI, vendor-specific infoframe and regular infoframe 1180 // are set up. 1181 1182 packet_init(); 1183 csc_init(); 1184 sample_init(); 1185 hdcp_init(); 1186 1187 // Enable frame composer overflow interrupts. 1188 1189 enable_overflow_irq(true); 1190 1191 return L4_EOK; 1192 } 1193 1194 void Hdmi_jz4780_chip::enable_overflow_irq(bool enable) 1195 { 1196 if (!enable) 1197 reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable); 1198 1199 // Apparent workaround required. 1200 1201 else 1202 { 1203 uint8_t config = _regs[Fc_video_config]; 1204 1205 _regs[Main_software_reset] = ~(Main_software_reset_tmds); 1206 1207 for (int i = 0; i < 4; i++) 1208 _regs[Fc_video_config] = config; 1209 } 1210 } 1211 1212 void Hdmi_jz4780_chip::frame_init() 1213 { 1214 // Initialise the video configuration. This is rather like the initialisation 1215 // of the LCD controller. The sync and data enable polarities are set up, plus 1216 // extras like HDCP, DVI mode, progressive/interlace. 1217 // NOTE: Here, the JZ4740-specific configuration is used to store the picture 1218 // NOTE: properties, but a neutral structure should be adopted. 1219 1220 uint8_t config = 0; 1221 1222 config |= (_panel->config & Jz4740_lcd_hsync_negative) 1223 ? Fc_video_config_hsync_active_low 1224 : Fc_video_config_hsync_active_high; 1225 1226 config |= (_panel->config & Jz4740_lcd_vsync_negative) 1227 ? Fc_video_config_vsync_active_low 1228 : Fc_video_config_vsync_active_high; 1229 1230 config |= (_panel->config & Jz4740_lcd_de_negative) 1231 ? Fc_video_config_data_enable_active_low 1232 : Fc_video_config_data_enable_active_high; 1233 1234 // NOTE: Only supporting DVI mode so far. 1235 1236 config |= Fc_video_config_dvi_mode; 1237 1238 // NOTE: Not supporting HDCP. 1239 1240 config |= Fc_video_config_hdcp_keepout_inactive; 1241 1242 // NOTE: Only supporting progressive scan so far. 1243 1244 config |= Fc_video_config_progressive; 1245 config |= Fc_video_config_osc_active_low; 1246 1247 _regs[Fc_video_config] = config; 1248 1249 // Then, the frame characteristics (visible area, sync pulse) are set. Indeed, 1250 // the frame area details should be practically the same as those used by the 1251 // LCD controller. 1252 1253 uint16_t hblank = _panel->line_start + _panel->line_end + _panel->hsync, 1254 vblank = _panel->frame_start + _panel->frame_end + _panel->vsync, 1255 hsync_delay = _panel->line_end, 1256 vsync_delay = _panel->frame_end, 1257 hsync_width = _panel->hsync, 1258 vsync_height = _panel->vsync; 1259 1260 _regs[Fc_horizontal_active_width1] = (_panel->width >> 8) & 0xff; 1261 _regs[Fc_horizontal_active_width0] = _panel->width & 0xff; 1262 1263 _regs[Fc_horizontal_blank_width1] = (hblank >> 8) & 0xff; 1264 _regs[Fc_horizontal_blank_width0] = hblank & 0xff; 1265 1266 _regs[Fc_vertical_active_height1] = (_panel->height >> 8) & 0xff; 1267 _regs[Fc_vertical_active_height0] = _panel->height & 0xff; 1268 1269 _regs[Fc_vertical_blank_height] = vblank & 0xff; 1270 1271 _regs[Fc_hsync_delay1] = (hsync_delay >> 8) & 0xff; 1272 _regs[Fc_hsync_delay0] = hsync_delay & 0xff; 1273 1274 _regs[Fc_vsync_delay] = vsync_delay & 0xff; 1275 1276 _regs[Fc_hsync_width1] = (hsync_width >> 8) & 0xff; 1277 _regs[Fc_hsync_width0] = hsync_width & 0xff; 1278 1279 _regs[Fc_vsync_height] = vsync_height & 0xff; 1280 } 1281 1282 void Hdmi_jz4780_chip::data_path_init() 1283 { 1284 // Initialise the path of the video data. Here, the elements of the data 1285 // stream are defined such as the control period duration, data channel 1286 // characteristics, pixel and TMDS clocks, and the involvement of colour space 1287 // conversion. 1288 1289 // Control period minimum duration. 1290 1291 _regs[Fc_control_duration] = 12; 1292 _regs[Fc_ex_control_duration] = 32; 1293 _regs[Fc_ex_control_space] = 1; 1294 1295 // Set to fill TMDS data channels. 1296 1297 _regs[Fc_channel0_preamble] = 0x0b; 1298 _regs[Fc_channel1_preamble] = 0x16; 1299 _regs[Fc_channel2_preamble] = 0x21; 1300 1301 // Apparent two-stage clock activation. 1302 1303 uint8_t clock_disable = Main_clock_disable_hdcp | 1304 Main_clock_disable_csc | 1305 Main_clock_disable_audio | 1306 Main_clock_disable_prep | 1307 Main_clock_disable_tmds; 1308 1309 // Activate the pixel clock. 1310 1311 _regs[Main_clock_disable] = clock_disable; 1312 1313 // Then activate the TMDS clock. 1314 1315 clock_disable &= ~(Main_clock_disable_tmds); 1316 _regs[Main_clock_disable] = clock_disable; 1317 1318 // NOTE: Bypass colour space conversion for now. 1319 1320 _regs[Main_flow_control] = Main_flow_control_csc_inactive; 1321 } 1322 1323 void Hdmi_jz4780_chip::packet_init() 1324 { 1325 // Initialise the video packet details. 1326 // NOTE: With 24bpp RGB output only for now, no pixel repetition. 1327 1328 int colour_depth = 4; 1329 1330 _regs[Packet_pr_cd] = 1331 ((colour_depth << Packet_pr_cd_depth_offset) & 1332 Packet_pr_cd_depth_mask); 1333 1334 _regs[Packet_remap] = Packet_remap_ycc422_16bit; 1335 1336 reg_fill_field(Packet_stuffing, Packet_stuffing_pr | 1337 Packet_stuffing_default_phase | 1338 Packet_stuffing_pp | 1339 Packet_stuffing_ycc422); 1340 1341 // Disable pixel repeater. 1342 1343 reg_update_field(Packet_config, Packet_config_bypass_enable | 1344 Packet_config_pr_enable | 1345 Packet_config_pp_enable | 1346 Packet_config_ycc422_enable | 1347 Packet_config_bypass_select_packetizer | 1348 Packet_config_output_selector_mask, 1349 Packet_config_bypass_enable | 1350 Packet_config_bypass_select_packetizer | 1351 Packet_config_output_selector_bypass); 1352 } 1353 1354 void Hdmi_jz4780_chip::csc_init() 1355 { 1356 // Initialise the colour space conversion details. 1357 // NOTE: No conversion will be done yet (see data_path_init). 1358 1359 _regs[Csc_config] = Csc_config_interpolation_disable | 1360 Csc_config_decimation_disable; 1361 1362 // NOTE: Use 8bpc (24bpp) for now. 1363 1364 reg_update_field(Csc_scale, Csc_scale_colour_depth_mask, Csc_scale_colour_depth_24bpp); 1365 1366 // NOTE: Coefficients should be set here. 1367 } 1368 1369 void Hdmi_jz4780_chip::sample_init() 1370 { 1371 // Initialise the mapping of video input data. 1372 // NOTE: With 24bpp RGB input only for now. 1373 1374 int colour_format = 0x01; 1375 1376 // Data enable inactive. 1377 1378 _regs[Sample_video_config] = (colour_format & Sample_video_config_mapping_mask); 1379 1380 // Transmission stuffing when data enable is inactive. 1381 1382 _regs[Sample_video_stuffing] = Sample_video_stuffing_bdb_data | 1383 Sample_video_stuffing_rcr_data | 1384 Sample_video_stuffing_gy_data; 1385 1386 _regs[Sample_gy_data0] = 0; 1387 _regs[Sample_gy_data1] = 0; 1388 _regs[Sample_rcr_data0] = 0; 1389 _regs[Sample_rcr_data1] = 0; 1390 _regs[Sample_bcb_data0] = 0; 1391 _regs[Sample_bcb_data1] = 0; 1392 } 1393 1394 void Hdmi_jz4780_chip::hdcp_init() 1395 { 1396 // Initialise HDCP registers, mostly turning things off. 1397 1398 reg_update(Hdcp_config0, Hdcp_config0_rxdetect_enable, false); 1399 1400 reg_update(Hdcp_video_polarity, 1401 Hdcp_video_polarity_data_enable_active_high, 1402 !(_panel->config & Jz4740_lcd_de_negative)); 1403 1404 reg_update(Hdcp_config1, Hdcp_config1_encryption_disable, true); 1405 } 1406 1407 1408 1409 // C language interface functions. 1410 1411 void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq, 1412 struct Jz4740_lcd_panel *panel) 1413 { 1414 return (void *) new Hdmi_jz4780_chip(start, end, irq, panel); 1415 } 1416 1417 void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor) 1418 { 1419 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_version(major, minor); 1420 } 1421 1422 void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def) 1423 { 1424 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_phy_capabilities(phy_def); 1425 } 1426 1427 int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length) 1428 { 1429 return static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_read(buf, length); 1430 } 1431 1432 void jz4780_hdmi_i2c_set_address(void *hdmi, uint8_t address) 1433 { 1434 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_address(address); 1435 } 1436 1437 void jz4780_hdmi_i2c_set_segment(void *hdmi, uint8_t segment) 1438 { 1439 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_segment(segment); 1440 } 1441 1442 void jz4780_hdmi_i2c_set_register(void *hdmi, uint8_t device_register) 1443 { 1444 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_register(device_register); 1445 } 1446 1447 int jz4780_hdmi_connected(void *hdmi) 1448 { 1449 return (int) static_cast<Hdmi_jz4780_chip *>(hdmi)->connected(); 1450 } 1451 1452 long jz4780_hdmi_wait_for_connection(void *hdmi) 1453 { 1454 return static_cast<Hdmi_jz4780_chip *>(hdmi)->wait_for_connection(); 1455 } 1456 1457 long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock) 1458 { 1459 return static_cast<Hdmi_jz4780_chip *>(hdmi)->enable(pixelclock); 1460 }