1 /* 2 * I2C support for the JZ4730. 3 * 4 * Copyright (C) 2017, 2018, 2020, 2021 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-jz4730.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/icu.h> 26 #include <l4/sys/ipc.h> 27 #include <l4/sys/irq.h> 28 #include <l4/util/util.h> 29 30 #include <cstdio> 31 32 /* 33 I2C pins are dedicated to I2C only and are not GPIO-controlled: 34 35 I2C0: Y4/SMB0_SDA, V5/SMB0_SCK 36 37 Note that there is effectively only one I2C channel. 38 */ 39 40 enum Regs 41 { 42 I2c_data = 0x000, // I2CDR 43 I2c_control = 0x004, // I2CCR 44 I2c_status = 0x008, // I2CSR 45 I2c_clock = 0x00c, // I2CGR 46 }; 47 48 enum I2c_control_bits : unsigned 49 { 50 I2c_control_enable_irq = 0x10, // IEN 51 I2c_control_start = 0x08, // STA 52 I2c_control_stop = 0x04, // STO 53 I2c_control_nack = 0x02, // AC 54 I2c_control_enable = 0x01, // I2CE 55 }; 56 57 enum I2c_status_bits : unsigned 58 { 59 I2c_status_buffer_nempty = 0x10, // STX 60 I2c_status_busy = 0x08, // BUSY 61 I2c_status_transmit_end = 0x04, // TEND 62 I2c_status_data_valid = 0x02, // DRF 63 I2c_status_nack = 0x01, // ACKF 64 }; 65 66 enum I2c_clock_values : unsigned 67 { 68 I2c_clock_max = 0xffff, 69 I2c_clock_min = 0, 70 }; 71 72 73 74 // Initialise a channel. 75 76 I2c_jz4730_channel::I2c_jz4730_channel(l4_addr_t start, 77 Cpm_jz4730_chip *cpm, 78 uint32_t frequency, 79 l4_cap_idx_t irq) 80 : _cpm(cpm), _frequency(frequency), _irq(irq) 81 { 82 _regs = new Hw::Mmio_register_block<32>(start); 83 } 84 85 // Enable the channel. 86 87 void 88 I2c_jz4730_channel::enable() 89 { 90 // Make sure that the I2C clock is available. 91 92 _cpm->start_clock(Clock_i2c); 93 94 // Set the bus clock frequency. 95 96 set_frequency(); 97 98 // Enable the channel and interrupts. 99 100 _regs[I2c_control] = I2c_control_enable | I2c_control_enable_irq; 101 while (!(_regs[I2c_control] & I2c_control_enable)); 102 } 103 104 // Disable the channel. 105 106 void 107 I2c_jz4730_channel::disable() 108 { 109 _regs[I2c_control] = 0; 110 while (_regs[I2c_control] & I2c_control_enable); 111 } 112 113 // Set the frequency-related peripheral parameters. 114 115 void 116 I2c_jz4730_channel::set_frequency() 117 { 118 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 119 // obtained from the CPM unit and is scaled to kHz in order to keep the 120 // numbers easily representable, as is the bus frequency. 121 122 uint32_t pclk = _cpm->get_pclock_frequency() / 1000; 123 uint32_t i2c_clk = _frequency / 1000; 124 uint32_t division = pclk / (16 * i2c_clk); 125 126 if (division > I2c_clock_min) 127 { 128 division -= 1; 129 if (division > I2c_clock_max) 130 division = I2c_clock_max; 131 } 132 133 _regs[I2c_clock] = division; 134 } 135 136 // State machine controller. 137 138 void 139 I2c_jz4730_channel::communicate() 140 { 141 enum I2c_jz4730_state state = I2c_jz4730_pre_start; 142 _limit = 10; 143 144 do 145 { 146 wait_for_irq(1000); 147 148 switch (state) 149 { 150 case I2c_jz4730_pre_start: 151 state = pre_start(); 152 break; 153 154 case I2c_jz4730_start_read: 155 state = start_read(); 156 break; 157 158 case I2c_jz4730_perform_read: 159 state = perform_read(); 160 break; 161 162 case I2c_jz4730_perform_write: 163 state = perform_write(); 164 break; 165 166 case I2c_jz4730_stop_write: 167 state = stop_write(); 168 break; 169 170 default: 171 break; 172 } 173 } 174 while (state != I2c_jz4730_end); 175 } 176 177 // State machine implementation handlers. 178 179 // Assert not busy state, issue start, present the address on the bus. 180 181 enum I2c_jz4730_state 182 I2c_jz4730_channel::pre_start() 183 { 184 // Wait again if busy up to the limit. 185 186 if (busy()) 187 { 188 if (!(--_limit)) 189 return I2c_jz4730_end; 190 else 191 return I2c_jz4730_pre_start; 192 } 193 194 // Use a longer time limit in subsequent activities. 195 196 _limit = 1000; 197 198 // Start, send address, proceed to the operation. 199 200 start(); 201 202 _regs[I2c_data] = (_address << 1) | (_read ? 1 : 0); 203 204 send_next(); 205 206 return _read ? I2c_jz4730_start_read : I2c_jz4730_perform_write; 207 } 208 209 // Wait for an opportunity to begin reading. 210 211 enum I2c_jz4730_state 212 I2c_jz4730_channel::start_read() 213 { 214 // Wait again if not ready to read. 215 216 if (transferring() || (!data_valid() && !nack())) 217 return I2c_jz4730_start_read; 218 219 return I2c_jz4730_perform_read; 220 } 221 222 // Attempt to read from the device. 223 224 enum I2c_jz4730_state 225 I2c_jz4730_channel::perform_read() 226 { 227 // Wait again if no available data. 228 229 if (!data_valid() && !nack()) 230 { 231 if (!(--_limit)) 232 { 233 stop(); 234 return I2c_jz4730_end; 235 } 236 else 237 return I2c_jz4730_perform_read; 238 } 239 240 // Stop if NACK received. 241 242 if (nack()) 243 { 244 stop(); 245 return I2c_jz4730_end; 246 } 247 248 // Signal last byte if appropriate. 249 250 if ((!_nread && (_length == 1)) || (_nread == _length - 2)) 251 signal_last(); 252 253 // Store and solicit data. 254 255 _buf[_nread++] = _regs[I2c_data]; 256 clear_next(); 257 258 // Stop if all data received. 259 260 if (_nread >= _length) 261 { 262 stop(); 263 return I2c_jz4730_end; 264 } 265 266 // Wait for more data otherwise. 267 268 _limit = 1000; 269 return I2c_jz4730_perform_read; 270 } 271 272 // Attempt to write to the device. 273 274 enum I2c_jz4730_state 275 I2c_jz4730_channel::perform_write() 276 { 277 // Wait for data (address or previous data) to be sent. 278 279 if (data_valid() && !nack()) 280 { 281 if (!(--_limit)) 282 { 283 stop(); 284 return I2c_jz4730_end; 285 } 286 else 287 return I2c_jz4730_perform_write; 288 } 289 290 // Stop if all data written or NACK received. 291 292 if ((_nwritten >= _length) || nack()) 293 { 294 stop(); 295 _limit = 1000; 296 return I2c_jz4730_stop_write; 297 } 298 299 // Write more data. 300 301 _regs[I2c_data] = _buf[_nwritten++]; 302 send_next(); 303 304 // Wait for the data to be sent. 305 306 _limit = 1000; 307 return I2c_jz4730_perform_write; 308 } 309 310 // Terminate the write transaction. 311 312 enum I2c_jz4730_state 313 I2c_jz4730_channel::stop_write() 314 { 315 if (!transferred()) 316 { 317 if (--_limit) 318 return I2c_jz4730_stop_write; 319 } 320 321 return I2c_jz4730_end; 322 } 323 324 // Wait up to the given timeout (in microseconds) for an interrupt request, 325 // returning true if one was delivered. 326 327 bool 328 I2c_jz4730_channel::wait_for_irq(unsigned int timeout) 329 { 330 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))); 331 } 332 333 // Read data from the bus. 334 335 unsigned int 336 I2c_jz4730_channel::read(uint8_t address, uint8_t buf[], unsigned int length) 337 { 338 _nread = 0; 339 _length = length; 340 _address = address; 341 _buf = &buf[0]; 342 _read = true; 343 344 communicate(); 345 346 return _nread; 347 } 348 349 // Write data to the bus. 350 351 unsigned int 352 I2c_jz4730_channel::write(uint8_t address, uint8_t buf[], unsigned int length) 353 { 354 _nwritten = 0; 355 _length = length; 356 _address = address; 357 _buf = &buf[0]; 358 _read = false; 359 360 communicate(); 361 362 return _nwritten; 363 } 364 365 // Test for data validity. 366 367 bool 368 I2c_jz4730_channel::data_valid() 369 { 370 return (_regs[I2c_status] & I2c_status_data_valid) ? true : false; 371 } 372 373 // Request the next byte by clearing the data validity flag. 374 375 void 376 I2c_jz4730_channel::clear_next() 377 { 378 _regs[I2c_status] = _regs[I2c_status] & ~I2c_status_data_valid; 379 } 380 381 // Indicate data ready for sending. 382 383 void 384 I2c_jz4730_channel::send_next() 385 { 386 _regs[I2c_status] = _regs[I2c_status] | I2c_status_data_valid; 387 } 388 389 // Test for non-acknowledgement. 390 391 bool 392 I2c_jz4730_channel::nack() 393 { 394 return (_regs[I2c_status] & I2c_status_nack) ? true : false; 395 } 396 397 // Set non-acknowledgement when receiving data. 398 399 void 400 I2c_jz4730_channel::signal_last() 401 { 402 _regs[I2c_control] = _regs[I2c_control] | I2c_control_nack; 403 } 404 405 // Test for bus activity. 406 407 bool 408 I2c_jz4730_channel::busy() 409 { 410 return (_regs[I2c_status] & I2c_status_busy) ? true : false; 411 } 412 413 // Test for transfer activity. 414 415 bool 416 I2c_jz4730_channel::transferring() 417 { 418 return (_regs[I2c_status] & I2c_status_buffer_nempty) ? true : false; 419 } 420 421 // Test for write transfer completion. 422 423 bool 424 I2c_jz4730_channel::transferred() 425 { 426 return (_regs[I2c_status] & I2c_status_transmit_end) ? true : false; 427 } 428 429 // Explicitly start communication. 430 431 void 432 I2c_jz4730_channel::start() 433 { 434 _regs[I2c_control] = (_regs[I2c_control] & ~I2c_control_nack) | I2c_control_start; 435 } 436 437 // Explicitly stop communication. 438 439 void 440 I2c_jz4730_channel::stop() 441 { 442 _regs[I2c_control] = _regs[I2c_control] | I2c_control_stop; 443 } 444 445 446 447 // Initialise the I2C controller. 448 449 I2c_jz4730_chip::I2c_jz4730_chip(l4_addr_t start, l4_addr_t end, 450 Cpm_jz4730_chip *cpm, 451 uint32_t frequency) 452 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 453 { 454 } 455 456 // Obtain a channel object. Only one channel is supported. 457 458 I2c_jz4730_channel * 459 I2c_jz4730_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) 460 { 461 if (channel == 0) 462 return new I2c_jz4730_channel(_start, _cpm, _frequency, irq); 463 else 464 throw -L4_EINVAL; 465 } 466 467 468 469 // C language interface functions. 470 471 void *jz4730_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 472 { 473 return (void *) new I2c_jz4730_chip(start, end, static_cast<Cpm_jz4730_chip *>(cpm), frequency); 474 } 475 476 void *jz4730_i2c_get_channel(void *i2c, uint8_t channel, l4_cap_idx_t irq) 477 { 478 return static_cast<I2c_jz4730_chip *>(i2c)->get_channel(channel, irq); 479 } 480 481 void jz4730_i2c_disable(void *i2c_channel) 482 { 483 static_cast<I2c_jz4730_channel *>(i2c_channel)->disable(); 484 } 485 486 void jz4730_i2c_enable(void *i2c_channel) 487 { 488 static_cast<I2c_jz4730_channel *>(i2c_channel)->enable(); 489 } 490 491 unsigned int jz4730_i2c_read(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) 492 { 493 return static_cast<I2c_jz4730_channel *>(i2c_channel)->read(address, buf, length); 494 } 495 496 unsigned int jz4730_i2c_write(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) 497 { 498 return static_cast<I2c_jz4730_channel *>(i2c_channel)->write(address, buf, length); 499 }