1 /* 2 * I2C support for the JZ4730. 3 * 4 * Copyright (C) 2017, 2018, 2020, 2021 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-jz4730.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/icu.h> 26 #include <l4/sys/ipc.h> 27 #include <l4/sys/irq.h> 28 #include <l4/util/util.h> 29 30 #include <cstdio> 31 32 /* 33 I2C pins are dedicated to I2C only and are not GPIO-controlled: 34 35 I2C0: Y4/SMB0_SDA, V5/SMB0_SCK 36 37 Note that there is effectively only one I2C channel. 38 */ 39 40 enum Regs 41 { 42 I2c_data = 0x000, // I2CDR 43 I2c_control = 0x004, // I2CCR 44 I2c_status = 0x008, // I2CSR 45 I2c_clock = 0x00c, // I2CGR 46 }; 47 48 enum I2c_control_bits : unsigned 49 { 50 I2c_control_enable_irq = 0x10, // IEN 51 I2c_control_start = 0x08, // STA 52 I2c_control_stop = 0x04, // STO 53 I2c_control_nack = 0x02, // AC 54 I2c_control_enable = 0x01, // I2CE 55 }; 56 57 enum I2c_status_bits : unsigned 58 { 59 I2c_status_buffer_nempty = 0x10, // STX 60 I2c_status_busy = 0x08, // BUSY 61 I2c_status_transmit_end = 0x04, // TEND 62 I2c_status_data_valid = 0x02, // DRF 63 I2c_status_nack = 0x01, // ACKF 64 }; 65 66 enum I2c_clock_values : unsigned 67 { 68 I2c_clock_max = 0xffff, 69 I2c_clock_min = 0, 70 }; 71 72 73 74 // Initialise a channel. 75 76 I2c_jz4730_channel::I2c_jz4730_channel(l4_addr_t start, 77 Cpm_jz4730_chip *cpm, 78 uint32_t frequency, 79 l4_cap_idx_t irq) 80 : _cpm(cpm), _frequency(frequency), _irq(irq) 81 { 82 _regs = new Hw::Mmio_register_block<32>(start); 83 } 84 85 // Enable the channel. 86 87 void 88 I2c_jz4730_channel::enable() 89 { 90 // Make sure that the I2C clock is available. 91 92 _cpm->start_clock(Clock_i2c); 93 94 // Set the bus clock frequency. 95 96 set_frequency(); 97 98 // Enable the channel and interrupts. 99 100 _regs[I2c_control] = I2c_control_enable | I2c_control_enable_irq; 101 while (!(_regs[I2c_control] & I2c_control_enable)); 102 } 103 104 // Disable the channel. 105 106 void 107 I2c_jz4730_channel::disable() 108 { 109 _regs[I2c_control] = 0; 110 while (_regs[I2c_control] & I2c_control_enable); 111 } 112 113 // Set the frequency-related peripheral parameters. 114 115 void 116 I2c_jz4730_channel::set_frequency() 117 { 118 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 119 // obtained from the CPM unit and is scaled to kHz in order to keep the 120 // numbers easily representable, as is the bus frequency. 121 122 uint32_t pclk = _cpm->get_pclock_frequency() / 1000; 123 uint32_t i2c_clk = _frequency / 1000; 124 uint32_t division = pclk / (16 * i2c_clk); 125 126 if (division > I2c_clock_min) 127 { 128 division -= 1; 129 if (division > I2c_clock_max) 130 division = I2c_clock_max; 131 } 132 133 _regs[I2c_clock] = division; 134 } 135 136 // State machine controller. 137 138 void 139 I2c_jz4730_channel::communicate() 140 { 141 enum I2c_jz4730_state state = I2c_jz4730_pre_start; 142 _limit = 1; 143 144 do 145 { 146 wait_for_irq(100000); 147 148 switch (state) 149 { 150 case I2c_jz4730_pre_start: 151 state = pre_start(); 152 break; 153 154 case I2c_jz4730_start_read: 155 state = start_read(); 156 break; 157 158 case I2c_jz4730_perform_read: 159 state = perform_read(); 160 break; 161 162 case I2c_jz4730_perform_write: 163 state = perform_write(); 164 break; 165 166 case I2c_jz4730_stop_write: 167 state = stop_write(); 168 break; 169 170 default: 171 break; 172 } 173 } 174 while (state != I2c_jz4730_end); 175 } 176 177 // State machine implementation handlers. 178 179 // Assert not busy state, issue start, present the address on the bus. 180 181 enum I2c_jz4730_state 182 I2c_jz4730_channel::pre_start() 183 { 184 // Wait again if busy up to the limit. 185 186 if (busy()) 187 { 188 if (!(--_limit)) 189 { 190 start_not_possible++; 191 return I2c_jz4730_end; 192 } 193 else 194 return I2c_jz4730_pre_start; 195 } 196 197 // Use a longer time limit in subsequent activities. 198 199 _limit = 1; 200 201 // Start, send address, proceed to the operation. 202 203 start(); 204 205 _regs[I2c_data] = (_address << 1) | (_read ? 1 : 0); 206 207 send_next(); 208 209 return _read ? I2c_jz4730_start_read : I2c_jz4730_perform_write; 210 } 211 212 // Wait for an opportunity to begin reading. 213 214 enum I2c_jz4730_state 215 I2c_jz4730_channel::start_read() 216 { 217 // Wait again if not ready to read. 218 219 if (transferring() || (!data_valid() && !nack())) 220 { 221 read_not_ready++; 222 if (transferring()) 223 read_not_ready_stx++; 224 else 225 read_not_ready_clear++; 226 return I2c_jz4730_start_read; 227 } 228 229 return I2c_jz4730_perform_read; 230 } 231 232 // Attempt to read from the device. 233 234 enum I2c_jz4730_state 235 I2c_jz4730_channel::perform_read() 236 { 237 // Wait again if no available data. 238 239 if (!data_valid() && !nack()) 240 { 241 if (!(--_limit)) 242 { 243 read_not_possible++; 244 stop(); 245 return I2c_jz4730_end; 246 } 247 else 248 return I2c_jz4730_perform_read; 249 } 250 251 // Stop if NACK received. 252 253 if (nack()) 254 { 255 read_nack++; 256 stop(); 257 return I2c_jz4730_end; 258 } 259 260 // Signal last byte if appropriate. 261 262 if ((!_nread && (_length == 1)) || (_nread == _length - 2)) 263 signal_last(); 264 265 // Store and solicit data. 266 267 _buf[_nread++] = _regs[I2c_data]; 268 clear_next(); 269 270 // Stop if all data received. 271 272 if (_nread >= _length) 273 { 274 read_complete++; 275 stop(); 276 return I2c_jz4730_end; 277 } 278 279 // Wait for more data otherwise. 280 281 _limit = 1; 282 return I2c_jz4730_perform_read; 283 } 284 285 // Attempt to write to the device. 286 287 enum I2c_jz4730_state 288 I2c_jz4730_channel::perform_write() 289 { 290 // Wait for data (address or previous data) to be sent. 291 292 if (data_valid() && !nack()) 293 { 294 if (!(--_limit)) 295 { 296 write_not_possible++; 297 stop(); 298 return I2c_jz4730_end; 299 } 300 else 301 return I2c_jz4730_perform_write; 302 } 303 304 // Stop if all data written or NACK received. 305 306 if ((_nwritten >= _length) || nack()) 307 { 308 write_complete++; 309 stop(); 310 _limit = 1; 311 return I2c_jz4730_stop_write; 312 } 313 314 // Write more data. 315 316 _regs[I2c_data] = _buf[_nwritten++]; 317 send_next(); 318 319 // Wait for the data to be sent. 320 321 _limit = 1; 322 return I2c_jz4730_perform_write; 323 } 324 325 // Terminate the write transaction. 326 327 enum I2c_jz4730_state 328 I2c_jz4730_channel::stop_write() 329 { 330 if (!transferred()) 331 { 332 if (--_limit) 333 return I2c_jz4730_stop_write; 334 } 335 336 return I2c_jz4730_end; 337 } 338 339 // Wait up to the given timeout (in microseconds) for an interrupt request, 340 // returning true if one was delivered. 341 342 bool 343 I2c_jz4730_channel::wait_for_irq(unsigned int timeout) 344 { 345 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))); 346 } 347 348 // Read data from the bus. 349 350 unsigned int 351 I2c_jz4730_channel::read(uint8_t address, uint8_t buf[], unsigned int length) 352 { 353 _nread = 0; 354 _length = length; 355 _address = address; 356 _buf = &buf[0]; 357 _read = true; 358 total_reads++; 359 360 communicate(); 361 362 return _nread; 363 } 364 365 // Write data to the bus. 366 367 unsigned int 368 I2c_jz4730_channel::write(uint8_t address, uint8_t buf[], unsigned int length) 369 { 370 _nwritten = 0; 371 _length = length; 372 _address = address; 373 _buf = &buf[0]; 374 _read = false; 375 376 communicate(); 377 378 return _nwritten; 379 } 380 381 // Test for data validity. 382 383 bool 384 I2c_jz4730_channel::data_valid() 385 { 386 return (_regs[I2c_status] & I2c_status_data_valid) ? true : false; 387 } 388 389 // Request the next byte by clearing the data validity flag. 390 391 void 392 I2c_jz4730_channel::clear_next() 393 { 394 _regs[I2c_status] = _regs[I2c_status] & ~I2c_status_data_valid; 395 } 396 397 // Indicate data ready for sending. 398 399 void 400 I2c_jz4730_channel::send_next() 401 { 402 _regs[I2c_status] = _regs[I2c_status] | I2c_status_data_valid; 403 } 404 405 // Test for non-acknowledgement. 406 407 bool 408 I2c_jz4730_channel::nack() 409 { 410 return (_regs[I2c_status] & I2c_status_nack) ? true : false; 411 } 412 413 // Set non-acknowledgement when receiving data. 414 415 void 416 I2c_jz4730_channel::signal_last() 417 { 418 _regs[I2c_control] = _regs[I2c_control] | I2c_control_nack; 419 } 420 421 // Test for bus activity. 422 423 bool 424 I2c_jz4730_channel::busy() 425 { 426 return (_regs[I2c_status] & I2c_status_busy) ? true : false; 427 } 428 429 // Test for transfer activity. 430 431 bool 432 I2c_jz4730_channel::transferring() 433 { 434 return (_regs[I2c_status] & I2c_status_buffer_nempty) ? true : false; 435 } 436 437 // Test for write transfer completion. 438 439 bool 440 I2c_jz4730_channel::transferred() 441 { 442 return (_regs[I2c_status] & I2c_status_transmit_end) ? true : false; 443 } 444 445 // Explicitly start communication. 446 447 void 448 I2c_jz4730_channel::start() 449 { 450 _regs[I2c_control] = (_regs[I2c_control] & ~I2c_control_nack) | I2c_control_start; 451 } 452 453 // Explicitly stop communication. 454 455 void 456 I2c_jz4730_channel::stop() 457 { 458 _regs[I2c_control] = _regs[I2c_control] | I2c_control_stop; 459 } 460 461 462 463 // Initialise the I2C controller. 464 465 I2c_jz4730_chip::I2c_jz4730_chip(l4_addr_t start, l4_addr_t end, 466 Cpm_jz4730_chip *cpm, 467 uint32_t frequency) 468 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 469 { 470 } 471 472 // Obtain a channel object. Only one channel is supported. 473 474 I2c_jz4730_channel * 475 I2c_jz4730_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) 476 { 477 if (channel == 0) 478 return new I2c_jz4730_channel(_start, _cpm, _frequency, irq); 479 else 480 throw -L4_EINVAL; 481 } 482 483 484 485 // C language interface functions. 486 487 void *jz4730_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 488 { 489 return (void *) new I2c_jz4730_chip(start, end, static_cast<Cpm_jz4730_chip *>(cpm), frequency); 490 } 491 492 void *jz4730_i2c_get_channel(void *i2c, uint8_t channel, l4_cap_idx_t irq) 493 { 494 return static_cast<I2c_jz4730_chip *>(i2c)->get_channel(channel, irq); 495 } 496 497 void jz4730_i2c_disable(void *i2c_channel) 498 { 499 static_cast<I2c_jz4730_channel *>(i2c_channel)->disable(); 500 } 501 502 void jz4730_i2c_enable(void *i2c_channel) 503 { 504 static_cast<I2c_jz4730_channel *>(i2c_channel)->enable(); 505 } 506 507 unsigned int jz4730_i2c_read(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) 508 { 509 return static_cast<I2c_jz4730_channel *>(i2c_channel)->read(address, buf, length); 510 } 511 512 unsigned int jz4730_i2c_write(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) 513 { 514 return static_cast<I2c_jz4730_channel *>(i2c_channel)->write(address, buf, length); 515 } 516 517 unsigned int jz4730_i2c_start_not_possible(void *i2c_channel) 518 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->start_not_possible; } 519 520 unsigned int jz4730_i2c_read_not_ready(void *i2c_channel) 521 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->read_not_ready; } 522 523 unsigned int jz4730_i2c_read_not_ready_clear(void *i2c_channel) 524 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->read_not_ready_clear; } 525 526 unsigned int jz4730_i2c_read_not_ready_stx(void *i2c_channel) 527 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->read_not_ready_stx; } 528 529 unsigned int jz4730_i2c_read_not_possible(void *i2c_channel) 530 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->read_not_possible; } 531 532 unsigned int jz4730_i2c_read_nack(void *i2c_channel) 533 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->read_nack; } 534 535 unsigned int jz4730_i2c_read_complete(void *i2c_channel) 536 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->read_complete; } 537 538 unsigned int jz4730_i2c_write_not_possible(void *i2c_channel) 539 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->write_not_possible; } 540 541 unsigned int jz4730_i2c_write_complete(void *i2c_channel) 542 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->write_complete; } 543 544 unsigned int jz4730_i2c_total_reads(void *i2c_channel) 545 { return reinterpret_cast<I2c_jz4730_channel *>(i2c_channel)->total_reads; }