1 /* 2 * Common clock functionality. 3 * 4 * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #pragma once 23 24 #ifdef __cplusplus 25 26 #include <l4/devices/clocks.h> 27 #include <l4/devices/hw_register_block.h> 28 #include <l4/sys/types.h> 29 #include <stdint.h> 30 31 /* Forward declaration. */ 32 33 class Clock_base; 34 35 36 37 /* Register access type. */ 38 39 class Cpm_regs 40 { 41 protected: 42 Hw::Register_block<32> _regs; 43 Clock_base **_clocks; 44 45 public: 46 explicit Cpm_regs(l4_addr_t addr, Clock_base *clocks[]); 47 48 // Utility methods. 49 50 uint32_t get_field(uint32_t reg, uint32_t mask, uint8_t shift); 51 void set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value); 52 53 Clock_base *get_clock(int num); 54 }; 55 56 57 58 // Register field abstraction. 59 60 class Field 61 { 62 uint32_t reg; 63 uint32_t mask; 64 uint8_t bit; 65 bool defined; 66 uint32_t _asserted = 0, _deasserted = 0; 67 68 public: 69 explicit Field() 70 : defined(false) 71 { 72 } 73 74 explicit Field(uint32_t reg, uint32_t mask, uint32_t bit, 75 bool inverted = false) 76 : reg(reg), mask(mask), bit(bit), defined(true) 77 { 78 if (inverted) 79 _deasserted = mask; 80 else 81 _asserted = mask; 82 } 83 84 uint32_t get_field(Cpm_regs ®s); 85 void set_field(Cpm_regs ®s, uint32_t value); 86 87 uint32_t get_asserted() { return _asserted; } 88 uint32_t get_deasserted() { return _deasserted; } 89 90 bool is_defined() { return defined; } 91 uint32_t get_limit() { return mask; } 92 93 // Undefined field object. 94 95 static Field undefined; 96 }; 97 98 99 100 // Clock sources. 101 102 class Mux 103 { 104 int _num_inputs; 105 enum Clock_identifiers *_inputs, _input; 106 107 public: 108 explicit Mux(int num_inputs, enum Clock_identifiers inputs[]) 109 : _num_inputs(num_inputs), _inputs(inputs) 110 { 111 } 112 113 explicit Mux(enum Clock_identifiers input) 114 : _num_inputs(1), _inputs(&_input) 115 { 116 _input = input; 117 } 118 119 explicit Mux() 120 : _num_inputs(0), _inputs(NULL) 121 { 122 } 123 124 int get_number() { return _num_inputs; } 125 enum Clock_identifiers get_input(int num); 126 }; 127 128 129 130 // Controllable clock source. 131 132 class Source 133 { 134 Mux _inputs; 135 Field _source; 136 137 public: 138 explicit Source(Mux inputs, Field source) 139 : _inputs(inputs), _source(source) 140 { 141 } 142 143 explicit Source(Mux inputs) 144 : _inputs(inputs) 145 { 146 } 147 148 explicit Source() 149 { 150 } 151 152 int get_number() { return _inputs.get_number(); } 153 enum Clock_identifiers get_input(int num) { return _inputs.get_input(num); } 154 155 // Clock source. 156 157 uint8_t get_source(Cpm_regs ®s); 158 void set_source(Cpm_regs ®s, uint8_t source); 159 enum Clock_identifiers get_source_clock(Cpm_regs ®s); 160 void set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock); 161 162 // Clock source frequency. 163 164 uint32_t get_frequency(Cpm_regs ®s); 165 }; 166 167 168 169 // Common clock control. 170 171 class Control_base 172 { 173 public: 174 virtual ~Control_base(); 175 176 virtual void change_disable(Cpm_regs ®s); 177 virtual void change_enable(Cpm_regs ®s); 178 179 virtual void wait_busy(Cpm_regs ®s) = 0; 180 virtual int have_clock(Cpm_regs ®s) = 0; 181 virtual void start_clock(Cpm_regs ®s) = 0; 182 virtual void stop_clock(Cpm_regs ®s) = 0; 183 }; 184 185 186 187 // Clock control. 188 189 class Control : public Control_base 190 { 191 Field _gate, _change_enable, _busy; 192 193 public: 194 explicit Control(Field gate, 195 Field change_enable = Field::undefined, 196 Field busy = Field::undefined) 197 : _gate(gate), _change_enable(change_enable), _busy(busy) 198 { 199 } 200 201 explicit Control() 202 : _gate(Field::undefined), _change_enable(Field::undefined), 203 _busy(Field::undefined) 204 { 205 } 206 207 // Clock control. 208 209 void change_disable(Cpm_regs ®s); 210 void change_enable(Cpm_regs ®s); 211 212 void wait_busy(Cpm_regs ®s); 213 int have_clock(Cpm_regs ®s); 214 void start_clock(Cpm_regs ®s); 215 void stop_clock(Cpm_regs ®s); 216 217 // Undefined control object. 218 219 static Control undefined; 220 }; 221 222 223 224 // PLL control. 225 226 class Control_pll : public Control_base 227 { 228 Field _enable, _stable, _bypass; 229 230 // PLL_specific control. 231 232 int have_pll(Cpm_regs ®s); 233 int pll_enabled(Cpm_regs ®s); 234 235 public: 236 explicit Control_pll(Field enable, Field stable, Field bypass) 237 : _enable(enable), _stable(stable), _bypass(bypass) 238 { 239 } 240 241 // Clock control. 242 243 int pll_bypassed(Cpm_regs ®s); 244 245 void pll_bypass(Cpm_regs ®s); 246 void pll_engage(Cpm_regs ®s); 247 248 void wait_busy(Cpm_regs ®s); 249 int have_clock(Cpm_regs ®s); 250 void start_clock(Cpm_regs ®s); 251 void stop_clock(Cpm_regs ®s); 252 }; 253 254 255 256 // Frequency transformation. 257 258 class Divider_base 259 { 260 public: 261 virtual ~Divider_base(); 262 263 // Output frequency. 264 265 virtual uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency) = 0; 266 virtual int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) = 0; 267 268 // Other operations. 269 270 virtual int get_parameters(Cpm_regs ®s, uint32_t parameters[]) = 0; 271 272 virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) = 0; 273 }; 274 275 276 277 // Simple divider for regular clocks. 278 279 class Divider : public Divider_base 280 { 281 Field _divider; 282 283 public: 284 explicit Divider(Field divider) 285 : _divider(divider) 286 { 287 } 288 289 explicit Divider() 290 : _divider(Field::undefined) 291 { 292 } 293 294 // Clock divider. 295 296 uint32_t get_divider(Cpm_regs ®s); 297 void set_divider(Cpm_regs ®s, uint32_t divider); 298 299 // Output frequency. 300 301 uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); 302 int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); 303 304 // Other operations. 305 306 int get_parameters(Cpm_regs ®s, uint32_t parameters[]); 307 int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); 308 }; 309 310 311 312 // Divider for PLLs. 313 314 class Divider_pll : public Divider_base 315 { 316 Field _multiplier, _input_divider, _output_divider0, _output_divider1; 317 double _intermediate_min, _intermediate_max; 318 319 // General frequency modifiers. 320 321 uint32_t get_multiplier(Cpm_regs ®s); 322 void set_multiplier(Cpm_regs ®s, uint32_t multiplier); 323 uint32_t get_input_divider(Cpm_regs ®s); 324 void set_input_divider(Cpm_regs ®s, uint32_t divider); 325 uint32_t get_output_divider(Cpm_regs ®s); 326 void set_output_divider(Cpm_regs ®s, uint32_t divider); 327 328 public: 329 330 // Double output divider constructor. 331 332 explicit Divider_pll(Field multiplier, Field input_divider, 333 Field output_divider0, Field output_divider1, 334 double intermediate_min, double intermediate_max) 335 : _multiplier(multiplier), _input_divider(input_divider), 336 _output_divider0(output_divider0), _output_divider1(output_divider1), 337 _intermediate_min(intermediate_min), _intermediate_max(intermediate_max) 338 { 339 } 340 341 // Single output divider constructor. 342 343 explicit Divider_pll(Field multiplier, Field input_divider, 344 Field output_divider, 345 double intermediate_min, double intermediate_max) 346 : _multiplier(multiplier), _input_divider(input_divider), 347 _output_divider0(output_divider), _output_divider1(Field::undefined), 348 _intermediate_min(intermediate_min), _intermediate_max(intermediate_max) 349 { 350 } 351 352 // Output frequency. 353 354 uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); 355 int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); 356 357 // Other operations. 358 359 int get_parameters(Cpm_regs ®s, uint32_t parameters[]); 360 int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); 361 }; 362 363 364 365 // Divider for I2S clocks. 366 367 class Divider_i2s : public Divider_base 368 { 369 Field _multiplier, _divider_N, _divider_D, _auto_N, _auto_D; 370 371 // General frequency modifiers. 372 373 uint32_t get_multiplier(Cpm_regs ®s); 374 uint32_t get_divider_N(Cpm_regs ®s); 375 uint32_t get_divider_D(Cpm_regs ®s); 376 377 public: 378 explicit Divider_i2s(Field multiplier, Field divider_N, Field divider_D, 379 Field auto_N, Field auto_D) 380 : _multiplier(multiplier), _divider_N(divider_N), _divider_D(divider_D), 381 _auto_N(auto_N), _auto_D(auto_D) 382 { 383 } 384 385 // Output frequency. 386 387 uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); 388 int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); 389 390 // Other operations. 391 392 int get_parameters(Cpm_regs ®s, uint32_t parameters[]); 393 394 int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); 395 }; 396 397 398 399 // Common clock abstraction. 400 401 class Clock_base 402 { 403 public: 404 virtual ~Clock_base(); 405 406 virtual const char *clock_type() { return "unset"; } 407 408 // Clock control. 409 410 virtual int have_clock(Cpm_regs ®s) = 0; 411 virtual void start_clock(Cpm_regs ®s) = 0; 412 virtual void stop_clock(Cpm_regs ®s) = 0; 413 414 // Output frequency. 415 416 virtual uint32_t get_frequency(Cpm_regs ®s) = 0; 417 }; 418 419 420 421 // Null (absent or undefined) clock abstraction. 422 423 class Clock_null : public Clock_base 424 { 425 public: 426 const char *clock_type() { return "null"; } 427 428 // Clock control. 429 430 int have_clock(Cpm_regs ®s); 431 void start_clock(Cpm_regs ®s); 432 void stop_clock(Cpm_regs ®s); 433 434 // Output frequency. 435 436 uint32_t get_frequency(Cpm_regs ®s); 437 }; 438 439 440 441 // Passive (root or input) clock without any source of its own. 442 443 class Clock_passive : public Clock_base 444 { 445 protected: 446 uint32_t _frequency; 447 448 public: 449 explicit Clock_passive(uint32_t frequency) 450 : _frequency(frequency) 451 { 452 } 453 454 const char *clock_type() { return "passive"; } 455 456 // Clock control. 457 458 virtual int have_clock(Cpm_regs ®s); 459 virtual void start_clock(Cpm_regs ®s); 460 virtual void stop_clock(Cpm_regs ®s); 461 462 // Output frequency. 463 464 uint32_t get_frequency(Cpm_regs ®s); 465 }; 466 467 468 469 class Clock_controlled : public Clock_base 470 { 471 protected: 472 virtual Control_base &_get_control() = 0; 473 474 public: 475 476 // Clock control. 477 478 virtual int have_clock(Cpm_regs ®s); 479 virtual void start_clock(Cpm_regs ®s); 480 virtual void stop_clock(Cpm_regs ®s); 481 }; 482 483 484 485 // An actively managed clock with source. 486 487 class Clock_active : public Clock_controlled 488 { 489 protected: 490 Source _source; 491 492 public: 493 explicit Clock_active(Source source) 494 : _source(source) 495 { 496 } 497 498 virtual ~Clock_active(); 499 500 // Clock source. 501 502 virtual uint8_t get_source(Cpm_regs ®s); 503 virtual void set_source(Cpm_regs ®s, uint8_t source); 504 enum Clock_identifiers get_source_clock(Cpm_regs ®s); 505 void set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock); 506 507 // Clock source frequency. 508 509 virtual uint32_t get_source_frequency(Cpm_regs ®s); 510 511 // Output frequency. 512 513 virtual uint32_t get_frequency(Cpm_regs ®s); 514 }; 515 516 517 518 // Divided clock interface. 519 520 class Clock_divided_base : public Clock_active 521 { 522 protected: 523 virtual Divider_base &_get_divider() = 0; 524 525 public: 526 explicit Clock_divided_base(Source source) 527 : Clock_active(source) 528 { 529 } 530 531 virtual ~Clock_divided_base(); 532 533 virtual int get_parameters(Cpm_regs ®s, uint32_t parameters[]); 534 virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]); 535 536 // Output frequency. 537 538 uint32_t get_frequency(Cpm_regs ®s); 539 virtual int set_frequency(Cpm_regs ®s, uint32_t frequency); 540 }; 541 542 543 544 // PLL description. 545 546 class Pll : public Clock_divided_base 547 { 548 Control_pll _control; 549 Divider_pll _divider; 550 551 virtual Control_base &_get_control() { return _control; } 552 virtual Divider_base &_get_divider() { return _divider; } 553 554 public: 555 explicit Pll(Source source, Control_pll control, Divider_pll divider) 556 : Clock_divided_base(source), _control(control), _divider(divider) 557 { 558 } 559 560 virtual ~Pll(); 561 562 const char *clock_type() { return "pll"; } 563 564 // Output frequency. 565 566 uint32_t get_frequency(Cpm_regs ®s); 567 int set_frequency(Cpm_regs ®s, uint32_t frequency); 568 }; 569 570 571 572 // Plain clock description. 573 574 class Clock : public Clock_active 575 { 576 Control _control; 577 578 virtual Control_base &_get_control() { return _control; } 579 580 public: 581 explicit Clock(Source source, Control control) 582 : Clock_active(source), _control(control) 583 { 584 } 585 586 explicit Clock(Source source) 587 : Clock_active(source) 588 { 589 } 590 591 const char *clock_type() { return "clock"; } 592 }; 593 594 595 596 // Divided clock description. 597 598 class Clock_divided : public Clock_divided_base 599 { 600 Control _control; 601 Divider _divider; 602 603 virtual Control_base &_get_control() { return _control; } 604 virtual Divider_base &_get_divider() { return _divider; } 605 606 public: 607 explicit Clock_divided(Source source, Control control, Divider divider) 608 : Clock_divided_base(source), _control(control), _divider(divider) 609 { 610 } 611 612 explicit Clock_divided(Source source, Divider divider) 613 : Clock_divided_base(source), _control(Control::undefined), _divider(divider) 614 { 615 } 616 617 const char *clock_type() { return "divided"; } 618 }; 619 620 621 622 // I2S clock description. 623 624 class Clock_divided_i2s : public Clock_divided_base 625 { 626 Control _control; 627 Divider_i2s _divider; 628 629 virtual Control_base &_get_control() { return _control; } 630 virtual Divider_base &_get_divider() { return _divider; } 631 632 public: 633 explicit Clock_divided_i2s(Source source, Control control, Divider_i2s divider) 634 : Clock_divided_base(source), _control(control), _divider(divider) 635 { 636 } 637 638 const char *clock_type() { return "i2s"; } 639 }; 640 641 #endif /* __cplusplus */