1 /* 2 * Common clock functionality. 3 * 4 * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/hw_mmio_register_block.h> 23 24 #include "cpm-common.h" 25 #include <math.h> 26 #include <stdio.h> 27 28 29 30 // Register access. 31 32 Cpm_regs::Cpm_regs(l4_addr_t addr, Clock_base *clocks[]) 33 : _clocks(clocks) 34 { 35 _regs = new Hw::Mmio_register_block<32>(addr); 36 } 37 38 // Utility methods. 39 40 uint32_t 41 Cpm_regs::get_field(uint32_t reg, uint32_t mask, uint8_t shift) 42 { 43 return (_regs[reg] & (mask << shift)) >> shift; 44 } 45 46 void 47 Cpm_regs::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) 48 { 49 _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); 50 } 51 52 Clock_base * 53 Cpm_regs::get_clock(int num) 54 { 55 return _clocks[num]; 56 } 57 58 59 60 // Field methods. 61 62 uint32_t 63 Field::get_field(Cpm_regs ®s) 64 { 65 if (defined) 66 return regs.get_field(reg, mask, bit); 67 else 68 return 0; 69 } 70 71 void 72 Field::set_field(Cpm_regs ®s, uint32_t value) 73 { 74 if (defined) 75 regs.set_field(reg, mask, bit, value); 76 } 77 78 // Undefined field. 79 80 Field Field::undefined; 81 82 83 84 // Clock sources. 85 86 enum Clock_identifiers 87 Mux::get_input(int num) 88 { 89 if (num < _num_inputs) 90 return _inputs[num]; 91 else 92 return Clock_undefined; 93 } 94 95 // Clock sources. 96 97 uint8_t 98 Source::get_source(Cpm_regs ®s) 99 { 100 if (_source.is_defined()) 101 return _source.get_field(regs); 102 else 103 return 0; 104 } 105 106 void 107 Source::set_source(Cpm_regs ®s, uint8_t source) 108 { 109 if (!_source.is_defined()) 110 return; 111 112 _source.set_field(regs, source); 113 } 114 115 enum Clock_identifiers 116 Source::get_source_clock(Cpm_regs ®s) 117 { 118 return get_input(get_number() == 1 ? 0 : get_source(regs)); 119 } 120 121 void 122 Source::set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock) 123 { 124 for (int source = 0; source < _inputs.get_number(); source++) 125 if (get_input(source) == clock) 126 _source.set_field(regs, source); 127 } 128 129 // Clock source frequencies. 130 131 uint32_t 132 Source::get_frequency(Cpm_regs ®s) 133 { 134 enum Clock_identifiers input = get_source_clock(regs); 135 136 if (input != Clock_undefined) 137 return regs.get_clock(input)->get_frequency(regs); 138 else 139 return 0; 140 } 141 142 143 144 // Clock control. 145 146 Control_base::~Control_base() 147 { 148 } 149 150 void 151 Control_base::change_disable(Cpm_regs ®s) 152 { 153 (void) regs; 154 } 155 156 void 157 Control_base::change_enable(Cpm_regs ®s) 158 { 159 (void) regs; 160 } 161 162 int 163 Control::have_clock(Cpm_regs ®s) 164 { 165 if (_gate.is_defined()) 166 return _gate.get_field(regs) == _gate.get_asserted(); 167 else 168 return true; 169 } 170 171 void 172 Control::start_clock(Cpm_regs ®s) 173 { 174 if (_gate.is_defined()) 175 _gate.set_field(regs, _gate.get_asserted()); 176 } 177 178 void 179 Control::stop_clock(Cpm_regs ®s) 180 { 181 if (_gate.is_defined()) 182 _gate.set_field(regs, _gate.get_deasserted()); 183 } 184 185 void 186 Control::wait_busy(Cpm_regs ®s) 187 { 188 if (_busy.is_defined()) 189 while (_busy.get_field(regs)); 190 } 191 192 void 193 Control::change_disable(Cpm_regs ®s) 194 { 195 if (_change_enable.is_defined()) 196 _change_enable.set_field(regs, 0); 197 } 198 199 void 200 Control::change_enable(Cpm_regs ®s) 201 { 202 if (_change_enable.is_defined()) 203 _change_enable.set_field(regs, 1); 204 } 205 206 // Undefined control. 207 208 Control Control::undefined; 209 210 211 212 // PLL-specific control. 213 214 int 215 Control_pll::have_pll(Cpm_regs ®s) 216 { 217 return _stable.get_field(regs); 218 } 219 220 int 221 Control_pll::pll_enabled(Cpm_regs ®s) 222 { 223 return _enable.get_field(regs); 224 } 225 226 int 227 Control_pll::pll_bypassed(Cpm_regs ®s) 228 { 229 return _bypass.get_field(regs); 230 } 231 232 void 233 Control_pll::pll_bypass(Cpm_regs ®s) 234 { 235 _bypass.set_field(regs, 1); 236 } 237 238 void 239 Control_pll::pll_engage(Cpm_regs ®s) 240 { 241 _bypass.set_field(regs, 0); 242 } 243 244 // Clock control. 245 246 int 247 Control_pll::have_clock(Cpm_regs ®s) 248 { 249 return have_pll(regs) && pll_enabled(regs); 250 } 251 252 void 253 Control_pll::start_clock(Cpm_regs ®s) 254 { 255 _enable.set_field(regs, 1); 256 while (!have_pll(regs)); 257 } 258 259 void 260 Control_pll::stop_clock(Cpm_regs ®s) 261 { 262 _enable.set_field(regs, 0); 263 while (have_pll(regs)); 264 } 265 266 void 267 Control_pll::wait_busy(Cpm_regs ®s) 268 { 269 if (pll_enabled(regs) && !pll_bypassed(regs)) 270 while (!have_pll(regs)); 271 } 272 273 274 275 // Clock dividers. 276 277 Divider_base::~Divider_base() 278 { 279 } 280 281 282 283 uint32_t 284 Divider::get_divider(Cpm_regs ®s) 285 { 286 if (_divider.is_defined()) 287 return _divider.get_field(regs) + 1; 288 else 289 return 1; 290 } 291 292 void 293 Divider::set_divider(Cpm_regs ®s, uint32_t divider) 294 { 295 if (_divider.is_defined()) 296 _divider.set_field(regs, divider - 1); 297 } 298 299 // Output clock frequencies. 300 301 uint32_t 302 Divider::get_frequency(Cpm_regs ®s, uint32_t source_frequency) 303 { 304 return source_frequency / get_divider(regs); 305 } 306 307 int 308 Divider::set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) 309 { 310 set_divider(regs, (uint32_t) round((double) source_frequency / (double) frequency)); 311 return 1; 312 } 313 314 int 315 Divider::get_parameters(Cpm_regs ®s, uint32_t parameters[]) 316 { 317 parameters[0] = get_divider(regs); 318 return 1; 319 } 320 321 int 322 Divider::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) 323 { 324 if (num_parameters) 325 { 326 set_divider(regs, parameters[0]); 327 return 1; 328 } 329 330 return 0; 331 } 332 333 334 335 // Common divider functionality. 336 337 static int is_integer(double x) 338 { 339 double target = round(x) * 1000; 340 double rounded = floor(x * 1000); 341 342 return (target - 100 < rounded) && (rounded < target + 100); 343 } 344 345 static double getscale_part(double x) 346 { 347 double part = x - floor(x); 348 349 if (part > 0.5) 350 return 1 / (1 - part); 351 else if (part > 0) 352 return 1 / part; 353 else 354 return 1; 355 } 356 357 static double getscale(double x) 358 { 359 double scale = getscale_part(x); 360 361 if (is_integer(scale)) 362 return scale; 363 else 364 return scale * getscale(scale); 365 } 366 367 static void get_divider_operands(double frequency, double source_frequency, 368 double *multiplier, double *divider) 369 { 370 double ratio = frequency / source_frequency; 371 double scale = getscale(ratio); 372 373 *multiplier = scale * ratio; 374 *divider = scale; 375 } 376 377 static void reduce_divider_operands(uint32_t *m, uint32_t *n, uint32_t m_limit, 378 uint32_t n_limit) 379 { 380 while ((*m > m_limit) && (*n > n_limit) && (*m > 1) && (*n > 1)) 381 { 382 *m >>= 1; 383 *n >>= 1; 384 } 385 } 386 387 #define zero_as_one(X) ((X) ? (X) : 1) 388 389 390 391 // Feedback multiplier. 392 393 uint32_t 394 Divider_pll::get_multiplier(Cpm_regs ®s) 395 { 396 return zero_as_one(_multiplier.get_field(regs)); 397 } 398 399 void 400 Divider_pll::set_multiplier(Cpm_regs ®s, uint32_t multiplier) 401 { 402 _multiplier.set_field(regs, multiplier); 403 } 404 405 // Input divider. 406 407 uint32_t 408 Divider_pll::get_input_divider(Cpm_regs ®s) 409 { 410 return zero_as_one(_input_divider.get_field(regs)); 411 } 412 413 void 414 Divider_pll::set_input_divider(Cpm_regs ®s, uint32_t divider) 415 { 416 _input_divider.set_field(regs, divider); 417 } 418 419 // Output dividers. 420 421 uint32_t 422 Divider_pll::get_output_divider(Cpm_regs ®s) 423 { 424 uint32_t d0 = zero_as_one(_output_divider0.get_field(regs)); 425 uint32_t d1 = _output_divider1.is_defined() ? 426 zero_as_one(_output_divider1.get_field(regs)) : 1; 427 428 return d0 * d1; 429 } 430 431 void 432 Divider_pll::set_output_divider(Cpm_regs ®s, uint32_t divider) 433 { 434 uint32_t d0, d1; 435 436 // Assert 1 as a minimum. 437 438 if (!divider) 439 divider = 1; 440 441 // Attempt to set any single divider. 442 443 if (!_output_divider1.is_defined()) 444 { 445 _output_divider0.set_field(regs, divider); 446 return; 447 } 448 449 // For two-divider implementations such as the X1600, divider 0 must be less 450 // than or equal to divider 1. 451 452 if (divider < _output_divider1.get_limit()) 453 { 454 d0 = 1; 455 d1 = divider; 456 } 457 else 458 { 459 d0 = (uint32_t) floor(sqrt(divider)); 460 d1 = divider / d0; 461 } 462 463 _output_divider0.set_field(regs, d0); 464 _output_divider1.set_field(regs, d1); 465 } 466 467 uint32_t 468 Divider_pll::get_frequency(Cpm_regs ®s, uint32_t source_frequency) 469 { 470 return (source_frequency * get_multiplier(regs)) / 471 (get_input_divider(regs) * get_output_divider(regs)); 472 } 473 474 int 475 Divider_pll::set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) 476 { 477 double intermediate_multiplier, intermediate_input_divider; 478 uint32_t output_min, output_max, output0, output1; 479 uint32_t multiplier, input_divider, output_divider; 480 481 // Define the range for the output dividers using the intermediate frequency 482 // range applying to each chip, this being the result of the multiplier and 483 // input divider. 484 485 output_min = (uint32_t) ceil(_intermediate_min / frequency); 486 output_max = (uint32_t) floor(_intermediate_max / frequency); 487 488 // Distribute the divider across the input and output dividers. 489 490 output_divider = output_min; 491 492 while (output_divider <= output_max) 493 { 494 bool usable_divider; 495 496 // Test divider constraints. 497 498 if (_output_divider1.is_defined()) 499 { 500 output0 = (uint32_t) floor(sqrt(output_divider)); 501 output1 = (uint32_t) floor(output_divider / output0); 502 503 usable_divider = ((output0 * output1 == output_divider) && 504 (output0 <= _output_divider0.get_limit()) && 505 (output1 <= _output_divider1.get_limit())); 506 } 507 else 508 usable_divider = output_divider <= _output_divider0.get_limit(); 509 510 // Apply any usable divider. 511 512 if (usable_divider) 513 { 514 // Calculate the other parameters. Start by working back from the desired 515 // output frequency to obtain an intermediate frequency using the proposed 516 // divider. 517 518 uint32_t intermediate_frequency = frequency * output_divider; 519 520 // Calculate the required multiplier and divider. 521 522 get_divider_operands(intermediate_frequency, source_frequency, 523 &intermediate_multiplier, &intermediate_input_divider); 524 525 multiplier = (uint32_t) round(intermediate_multiplier); 526 input_divider = (uint32_t) round(intermediate_input_divider); 527 528 // Attempt to reduce the multiplier and divider to usable values. 529 530 uint32_t multiplier_limit = _multiplier.get_limit(); 531 uint32_t input_divider_limit = _input_divider.get_limit(); 532 533 reduce_divider_operands(&multiplier, &input_divider, 534 multiplier_limit, input_divider_limit); 535 536 if ((multiplier <= multiplier_limit) && (input_divider <= input_divider_limit)) 537 { 538 set_multiplier(regs, multiplier); 539 set_input_divider(regs, input_divider); 540 set_output_divider(regs, output_divider); 541 542 return 1; 543 } 544 } 545 546 output_divider++; 547 } 548 549 return 0; 550 } 551 552 int 553 Divider_pll::get_parameters(Cpm_regs ®s, uint32_t parameters[]) 554 { 555 parameters[0] = get_multiplier(regs); 556 parameters[1] = get_input_divider(regs); 557 parameters[2] = get_output_divider(regs); 558 return 3; 559 } 560 561 int 562 Divider_pll::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) 563 { 564 if (num_parameters > 2) 565 { 566 set_multiplier(regs, parameters[0]); 567 set_input_divider(regs, parameters[1]); 568 set_output_divider(regs, parameters[2]); 569 570 return 3; 571 } 572 573 return 0; 574 } 575 576 577 578 // I2S clock divider. 579 580 uint32_t 581 Divider_i2s::get_multiplier(Cpm_regs ®s) 582 { 583 return _multiplier.get_field(regs); 584 } 585 586 uint32_t 587 Divider_i2s::get_divider_N(Cpm_regs ®s) 588 { 589 return _divider_N.get_field(regs); 590 } 591 592 uint32_t 593 Divider_i2s::get_divider_D(Cpm_regs ®s) 594 { 595 return _divider_D.get_field(regs); 596 } 597 598 uint32_t 599 Divider_i2s::get_frequency(Cpm_regs ®s, uint32_t source_frequency) 600 { 601 /* NOTE: Assuming that this is the formula, given that the manual does not 602 really describe how D is used. */ 603 604 return (source_frequency * get_multiplier(regs)) / 605 (get_divider_N(regs) * get_divider_D(regs)); 606 } 607 608 int 609 Divider_i2s::set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) 610 { 611 double m, n; 612 613 get_divider_operands(frequency, source_frequency, &m, &n); 614 615 uint32_t multiplier = (uint32_t) round(m); 616 uint32_t divider = (uint32_t) round(n); 617 618 reduce_divider_operands(&multiplier, ÷r, 619 _multiplier.get_limit(), 620 _divider_N.get_limit()); 621 622 // Test for operand within limits and the N >= 2M constraint. 623 624 if ((multiplier <= _multiplier.get_limit()) && (divider <= _divider_N.get_limit()) && 625 (divider >= 2 * multiplier)) 626 { 627 /* NOTE: Setting D to 1. Even though it seems that D might also be used, 628 it does not seem necessary in practice, and the documentation is 629 unclear about its use. */ 630 631 uint32_t parameters[] = {multiplier, divider, 1}; 632 633 set_parameters(regs, 3, parameters); 634 return 1; 635 } 636 637 return 0; 638 } 639 640 int 641 Divider_i2s::get_parameters(Cpm_regs ®s, uint32_t parameters[]) 642 { 643 parameters[0] = get_multiplier(regs); 644 parameters[1] = get_divider_N(regs); 645 parameters[2] = get_divider_D(regs); 646 return 3; 647 } 648 649 int 650 Divider_i2s::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) 651 { 652 if (num_parameters == 1) 653 { 654 // Set automatic N and D value calculation if only one parameter is given. 655 656 _auto_N.set_field(regs, 0); 657 _auto_D.set_field(regs, 0); 658 _multiplier.set_field(regs, parameters[0]); 659 660 return 1; 661 } 662 else if (num_parameters > 1) 663 { 664 // Require N >= 2M, returning otherwise. 665 666 if (parameters[1] < 2 * parameters[0]) 667 return 0; 668 669 // Set automatic D value calculation if only two parameters are given. 670 671 _auto_N.set_field(regs, 1); 672 _auto_D.set_field(regs, (num_parameters == 2) ? 0 : 1); 673 674 _multiplier.set_field(regs, parameters[0]); 675 _divider_N.set_field(regs, parameters[1]); 676 677 // Set D explicitly if given. 678 679 if (num_parameters > 2) 680 _divider_D.set_field(regs, parameters[2]); 681 682 return num_parameters; 683 } 684 685 return 0; 686 } 687 688 689 690 // Clock interface. 691 692 Clock_base::~Clock_base() 693 { 694 } 695 696 697 698 // Null clock. 699 700 int 701 Clock_null::have_clock(Cpm_regs ®s) 702 { 703 (void) regs; 704 return false; 705 } 706 707 void 708 Clock_null::start_clock(Cpm_regs ®s) 709 { 710 (void) regs; 711 } 712 713 void 714 Clock_null::stop_clock(Cpm_regs ®s) 715 { 716 (void) regs; 717 } 718 719 // Output clock frequencies. 720 721 uint32_t 722 Clock_null::get_frequency(Cpm_regs ®s) 723 { 724 (void) regs; 725 return 0; 726 } 727 728 729 730 // Passive clock. 731 732 int 733 Clock_passive::have_clock(Cpm_regs ®s) 734 { 735 (void) regs; 736 return true; 737 } 738 739 void 740 Clock_passive::start_clock(Cpm_regs ®s) 741 { 742 (void) regs; 743 } 744 745 void 746 Clock_passive::stop_clock(Cpm_regs ®s) 747 { 748 (void) regs; 749 } 750 751 // Output clock frequencies. 752 753 uint32_t 754 Clock_passive::get_frequency(Cpm_regs ®s) 755 { 756 (void) regs; 757 return _frequency; 758 } 759 760 761 762 // Clock control. 763 764 int 765 Clock_controlled::have_clock(Cpm_regs ®s) 766 { 767 return _get_control().have_clock(regs); 768 } 769 770 void 771 Clock_controlled::start_clock(Cpm_regs ®s) 772 { 773 _get_control().start_clock(regs); 774 } 775 776 void 777 Clock_controlled::stop_clock(Cpm_regs ®s) 778 { 779 _get_control().stop_clock(regs); 780 } 781 782 783 784 // Active clock interface. 785 786 Clock_active::~Clock_active() 787 { 788 } 789 790 // Clock sources. 791 792 uint8_t 793 Clock_active::get_source(Cpm_regs ®s) 794 { 795 return _source.get_source(regs); 796 } 797 798 void 799 Clock_active::set_source(Cpm_regs ®s, uint8_t source) 800 { 801 _get_control().change_enable(regs); 802 _source.set_source(regs, source); 803 _get_control().wait_busy(regs); 804 _get_control().change_disable(regs); 805 } 806 807 enum Clock_identifiers 808 Clock_active::get_source_clock(Cpm_regs ®s) 809 { 810 return _source.get_source_clock(regs); 811 } 812 813 void 814 Clock_active::set_source_clock(Cpm_regs ®s, enum Clock_identifiers clock) 815 { 816 _source.set_source_clock(regs, clock); 817 } 818 819 // Clock source frequencies. 820 821 uint32_t 822 Clock_active::get_source_frequency(Cpm_regs ®s) 823 { 824 return _source.get_frequency(regs); 825 } 826 827 // Output clock frequencies. 828 829 uint32_t 830 Clock_active::get_frequency(Cpm_regs ®s) 831 { 832 return get_source_frequency(regs); 833 } 834 835 836 837 // Divided clock interface. 838 839 Clock_divided_base::~Clock_divided_base() 840 { 841 } 842 843 // Output clock frequencies. 844 845 uint32_t 846 Clock_divided_base::get_frequency(Cpm_regs ®s) 847 { 848 return _get_divider().get_frequency(regs, get_source_frequency(regs)); 849 } 850 851 int 852 Clock_divided_base::set_frequency(Cpm_regs ®s, uint32_t frequency) 853 { 854 _get_control().change_enable(regs); 855 int result = _get_divider().set_frequency(regs, get_source_frequency(regs), frequency); 856 _get_control().wait_busy(regs); 857 _get_control().change_disable(regs); 858 859 return result; 860 } 861 862 int 863 Clock_divided_base::get_parameters(Cpm_regs ®s, uint32_t parameters[]) 864 { 865 return _get_divider().get_parameters(regs, parameters); 866 } 867 868 int 869 Clock_divided_base::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) 870 { 871 _get_control().change_enable(regs); 872 int n = _get_divider().set_parameters(regs, num_parameters, parameters); 873 _get_control().wait_busy(regs); 874 _get_control().change_disable(regs); 875 876 return n; 877 } 878 879 880 881 // PLL functionality. 882 883 Pll::~Pll() 884 { 885 } 886 887 uint32_t 888 Pll::get_frequency(Cpm_regs ®s) 889 { 890 if (!_control.pll_bypassed(regs)) 891 return _divider.get_frequency(regs, get_source_frequency(regs)); 892 else 893 return get_source_frequency(regs); 894 } 895 896 int 897 Pll::set_frequency(Cpm_regs ®s, uint32_t frequency) 898 { 899 int result = Clock_divided_base::set_frequency(regs, frequency); 900 _control.pll_engage(regs); 901 902 return result; 903 }