1 /* 2 * I2C support for the JZ4730. 3 * 4 * Copyright (C) 2017, 2018, 2020, 2021 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-jz4730.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/icu.h> 26 #include <l4/sys/ipc.h> 27 #include <l4/sys/irq.h> 28 #include <l4/util/util.h> 29 30 #include <cstdio> 31 32 /* 33 I2C pins are dedicated to I2C only and are not GPIO-controlled: 34 35 I2C0: Y4/SMB0_SDA, V5/SMB0_SCK 36 37 Note that there is effectively only one I2C channel. 38 */ 39 40 enum Regs 41 { 42 I2c_data = 0x000, // I2CDR 43 I2c_control = 0x004, // I2CCR 44 I2c_status = 0x008, // I2CSR 45 I2c_clock = 0x00c, // I2CGR 46 }; 47 48 enum I2c_control_bits : unsigned 49 { 50 I2c_control_enable_irq = 0x10, // IEN 51 I2c_control_start = 0x08, // STA 52 I2c_control_stop = 0x04, // STO 53 I2c_control_nack = 0x02, // AC 54 I2c_control_enable = 0x01, // I2CE 55 }; 56 57 enum I2c_status_bits : unsigned 58 { 59 I2c_status_buffer_nempty = 0x10, // STX 60 I2c_status_busy = 0x08, // BUSY 61 I2c_status_transmit_end = 0x04, // TEND 62 I2c_status_data_valid = 0x02, // DRF 63 I2c_status_nack = 0x01, // ACKF 64 }; 65 66 enum I2c_clock_values : unsigned 67 { 68 I2c_clock_max = 0xffff, 69 I2c_clock_min = 0, 70 }; 71 72 73 74 // Initialise a channel. 75 76 I2c_jz4730_channel::I2c_jz4730_channel(l4_addr_t start, 77 Cpm_jz4730_chip *cpm, 78 uint32_t frequency, 79 l4_cap_idx_t irq) 80 : _cpm(cpm), _frequency(frequency), _irq(irq) 81 { 82 _regs = new Hw::Mmio_register_block<32>(start); 83 } 84 85 // Enable the channel. 86 87 void 88 I2c_jz4730_channel::enable() 89 { 90 // Make sure that the I2C clock is available. 91 92 _cpm->start_clock(Clock_i2c); 93 94 // Set the bus clock frequency. 95 96 set_frequency(); 97 98 // Enable the channel and interrupts. 99 100 _regs[I2c_control] = I2c_control_enable | I2c_control_enable_irq; 101 while (!(_regs[I2c_control] & I2c_control_enable)); 102 } 103 104 // Disable the channel. 105 106 void 107 I2c_jz4730_channel::disable() 108 { 109 _regs[I2c_control] = 0; 110 while (_regs[I2c_control] & I2c_control_enable); 111 } 112 113 // Set the frequency-related peripheral parameters. 114 115 void 116 I2c_jz4730_channel::set_frequency() 117 { 118 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 119 // obtained from the CPM unit and is scaled to kHz in order to keep the 120 // numbers easily representable, as is the bus frequency. 121 122 uint32_t pclk = _cpm->get_pclock_frequency() / 1000; 123 uint32_t i2c_clk = _frequency / 1000; 124 uint32_t division = pclk / (16 * i2c_clk); 125 126 if (division > I2c_clock_min) 127 { 128 division -= 1; 129 if (division > I2c_clock_max) 130 division = I2c_clock_max; 131 } 132 133 _regs[I2c_clock] = division; 134 } 135 136 // Present the address on the bus. 137 138 bool 139 I2c_jz4730_channel::set_address(uint8_t address, bool read) 140 { 141 // Waiting for long enough may eliminate a busy condition and thus permit a 142 // new transaction. 10ms appears to be long enough, whereas 1ms does not 143 // appear to be. In case this is insufficient, permit failure. 144 145 unsigned int limit = 10; 146 147 do 148 { 149 if (!wait_for_irq(1000) && !(--limit)) 150 return false; 151 } 152 while (busy()); 153 154 start(); 155 156 _regs[I2c_data] = (address << 1) | (read ? 1 : 0); 157 158 send_next(); 159 160 return true; 161 } 162 163 // Wait up to the given timeout (in microseconds) for an interrupt request, 164 // returning true if one was delivered. 165 166 bool 167 I2c_jz4730_channel::wait_for_irq(unsigned int timeout) 168 { 169 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))); 170 } 171 172 // Read data from the bus. 173 174 unsigned int 175 I2c_jz4730_channel::read(uint8_t address, uint8_t buf[], unsigned int length) 176 { 177 unsigned int nread = 0; 178 179 if (!set_address(address, true)) 180 return 0; 181 182 // Wait for an opportunity to begin reading. 183 184 do 185 { 186 if (!wait_for_irq(1000000)) 187 printf("start (no irq): status = %x\n", (uint32_t) _regs[I2c_status]); 188 } 189 while (transferring() || (!data_valid() && !nack())); 190 191 // Device apparently unavailable. 192 193 if (nack()) 194 { 195 stop(); 196 return nread; 197 } 198 199 // Attempt to read from the device. 200 201 while (nread < length) 202 { 203 do 204 { 205 if (!wait_for_irq(1000000)) 206 { 207 stop(); 208 return nread; 209 } 210 } 211 while (!data_valid() && !nack()); 212 213 if (nack()) 214 break; 215 216 if ((!nread && (length == 1)) || (nread == length - 2)) 217 signal_last(); 218 219 buf[nread++] = _regs[I2c_data]; 220 clear_next(); 221 } 222 223 stop(); 224 return nread; 225 } 226 227 // Write data to the bus. 228 229 unsigned int 230 I2c_jz4730_channel::write(uint8_t address, uint8_t buf[], unsigned int length) 231 { 232 unsigned int nwritten = 0; 233 234 if (!set_address(address, false)) 235 return 0; 236 237 do 238 { 239 if (!wait_for_irq(1000000)) 240 { 241 printf("write (no irq): status = %x\n", (uint32_t) _regs[I2c_status]); 242 stop(); 243 return nwritten; 244 } 245 } 246 while (data_valid() && !nack()); 247 248 while ((nwritten < length) && !nack()) 249 { 250 _regs[I2c_data] = buf[nwritten++]; 251 send_next(); 252 253 do 254 { 255 if (!wait_for_irq(1000000)) 256 { 257 printf("write (no irq): status = %x\n", (uint32_t) _regs[I2c_status]); 258 stop(); 259 return nwritten; 260 } 261 } 262 while (data_valid() && !nack()); 263 } 264 265 stop(); 266 267 do 268 { 269 if (!wait_for_irq(1000000)) 270 break; 271 } 272 while (!transferred()); 273 274 return nwritten; 275 } 276 277 // Test for data validity. 278 279 bool 280 I2c_jz4730_channel::data_valid() 281 { 282 return (_regs[I2c_status] & I2c_status_data_valid) ? true : false; 283 } 284 285 // Request the next byte by clearing the data validity flag. 286 287 void 288 I2c_jz4730_channel::clear_next() 289 { 290 _regs[I2c_status] = _regs[I2c_status] & ~I2c_status_data_valid; 291 } 292 293 // Indicate data ready for sending. 294 295 void 296 I2c_jz4730_channel::send_next() 297 { 298 _regs[I2c_status] = _regs[I2c_status] | I2c_status_data_valid; 299 } 300 301 // Test for non-acknowledgement. 302 303 bool 304 I2c_jz4730_channel::nack() 305 { 306 return (_regs[I2c_status] & I2c_status_nack) ? true : false; 307 } 308 309 // Set non-acknowledgement when receiving data. 310 311 void 312 I2c_jz4730_channel::signal_last() 313 { 314 _regs[I2c_control] = _regs[I2c_control] | I2c_control_nack; 315 } 316 317 // Test for bus activity. 318 319 bool 320 I2c_jz4730_channel::busy() 321 { 322 return (_regs[I2c_status] & I2c_status_busy) ? true : false; 323 } 324 325 // Test for transfer activity. 326 327 bool 328 I2c_jz4730_channel::transferring() 329 { 330 return (_regs[I2c_status] & I2c_status_buffer_nempty) ? true : false; 331 } 332 333 // Test for write transfer completion. 334 335 bool 336 I2c_jz4730_channel::transferred() 337 { 338 return (_regs[I2c_status] & I2c_status_transmit_end) ? true : false; 339 } 340 341 // Explicitly start communication. 342 343 void 344 I2c_jz4730_channel::start() 345 { 346 _regs[I2c_control] = (_regs[I2c_control] & ~I2c_control_nack) | I2c_control_start; 347 } 348 349 // Explicitly stop communication. 350 351 void 352 I2c_jz4730_channel::stop() 353 { 354 _regs[I2c_control] = _regs[I2c_control] | I2c_control_stop; 355 } 356 357 358 359 // Initialise the I2C controller. 360 361 I2c_jz4730_chip::I2c_jz4730_chip(l4_addr_t start, l4_addr_t end, 362 Cpm_jz4730_chip *cpm, 363 uint32_t frequency) 364 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 365 { 366 } 367 368 // Obtain a channel object. Only one channel is supported. 369 370 I2c_jz4730_channel * 371 I2c_jz4730_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) 372 { 373 if (channel == 0) 374 return new I2c_jz4730_channel(_start, _cpm, _frequency, irq); 375 else 376 throw -L4_EINVAL; 377 } 378 379 380 381 // C language interface functions. 382 383 void *jz4730_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 384 { 385 return (void *) new I2c_jz4730_chip(start, end, static_cast<Cpm_jz4730_chip *>(cpm), frequency); 386 } 387 388 void *jz4730_i2c_get_channel(void *i2c, uint8_t channel, l4_cap_idx_t irq) 389 { 390 return static_cast<I2c_jz4730_chip *>(i2c)->get_channel(channel, irq); 391 } 392 393 void jz4730_i2c_disable(void *i2c_channel) 394 { 395 static_cast<I2c_jz4730_channel *>(i2c_channel)->disable(); 396 } 397 398 void jz4730_i2c_enable(void *i2c_channel) 399 { 400 static_cast<I2c_jz4730_channel *>(i2c_channel)->enable(); 401 } 402 403 unsigned int jz4730_i2c_read(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) 404 { 405 return static_cast<I2c_jz4730_channel *>(i2c_channel)->read(address, buf, length); 406 } 407 408 unsigned int jz4730_i2c_write(void *i2c_channel, uint8_t address, uint8_t buf[], unsigned int length) 409 { 410 return static_cast<I2c_jz4730_channel *>(i2c_channel)->write(address, buf, length); 411 }