1 /* 2 * JZ4780 HDMI peripheral support. 3 * 4 * Copyright (C) 2020 Paul Boddie <paul@boddie.org.uk> 5 * 6 * Techniques and operations introduced from the Linux DRM bridge driver for 7 * Synopsys DW-HDMI whose authors are as follows: 8 * 9 * Copyright (C) 2013-2015 Mentor Graphics Inc. 10 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 11 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 26 * Boston, MA 02110-1301, USA 27 * 28 * ---- 29 * 30 * Some acronyms: 31 * 32 * CEC (Consumer Electronics Control) is a HDMI device control interface for up 33 * to 15 devices. 34 * 35 * CSC (Colour Space Conversion) is the processing needed to convert from one 36 * representation of colours to another. 37 * 38 * HEAC (HDMI Ethernet and Audio Return Channel) is a combination of HEC (HDMI 39 * Ethernet Channel) which provides a 100Mb/s bidirectional link and ARC (Audio 40 * Return Channel) which permits the consumption of audio data from the device. 41 * 42 * MHL (Mobile High-Definition Link) is an adaptation of HDMI for mobile 43 * devices. 44 * 45 * TMDS (Transition-Minimized Differential Signaling) is the method by which 46 * audio, control and video data are all sent to the device. 47 */ 48 49 #include <l4/devices/hdmi-jz4780.h> 50 #include <l4/devices/hw_mmio_register_block.h> 51 #include <l4/devices/lcd-jz4740-config.h> 52 53 #include <l4/sys/irq.h> 54 #include <l4/util/util.h> 55 56 /* 57 I2C pins: 58 59 HDMI: PF25/SMB4_SDA/DDCSDA, PF24/SMB4_SCK/DDCSCK 60 61 See: http://mipscreator.imgtec.com/CI20/hardware/board/ci20_jz4780_v2.0.pdf 62 */ 63 64 enum Regs 65 { 66 // Identification. 67 68 Design_id = 0x000, // DESIGN_ID 69 Revision_id = 0x001, // REVISION_ID 70 Product_id0 = 0x002, // PRODUCT_ID0 71 Product_id1 = 0x003, // PRODUCT_ID1 72 Config_id0 = 0x004, // CONFIG_ID0 73 Config_id1 = 0x005, // CONFIG_ID1 74 Config_id2 = 0x006, // CONFIG_ID2 75 Config_id3 = 0x007, // CONFIG_ID3 76 77 // Top-level interrupt control. 78 79 Int_mask = 0x1ff, // MUTE 80 81 // Interrupt status and mask for various functions. 82 83 Fc_int_status0 = 0x100, // FC_STAT0 84 Fc_int_status1 = 0x101, // FC_STAT1 85 Fc_int_status2 = 0x102, // FC_STAT2 86 As_int_status = 0x103, // AS_STAT0 87 Phy_int_status = 0x104, // PHY_STAT0 88 Cec_int_status = 0x106, // CEC_STAT0 89 Vp_int_status = 0x107, // VP_STAT0 90 Ahb_dma_audio_int_status = 0x109, // AHBDMAAUD_STAT0 91 92 Fc_int_mask0 = 0x180, // MUTE_FC_STAT0 93 Fc_int_mask1 = 0x181, // MUTE_FC_STAT1 94 Fc_int_mask2 = 0x182, // MUTE_FC_STAT2 95 As_int_mask = 0x183, // MUTE_AS_STAT0 96 Phy_int_mask = 0x184, // MUTE_PHY_STAT0 97 Cec_int_mask = 0x186, // MUTE_CEC_STAT0 98 Vp_int_mask = 0x187, // MUTE_VP_STAT0 99 Ahb_dma_audio_int_mask = 0x189, // MUTE_AHBDMAAUD_STAT0 100 101 // I2C for E-DDC. 102 103 I2c_int_status = 0x105, // I2CM_STAT0 104 I2c_int_mask = 0x185, // MUTE_I2CM_STAT0 105 106 I2c_device_address = 0x7e00, // I2CM_SLAVE 107 I2c_register = 0x7e01, // I2CM_ADDRESS 108 I2c_data_out = 0x7e02, // I2CM_DATAO 109 I2c_data_in = 0x7e03, // I2CM_DATAI 110 I2c_operation = 0x7e04, // I2CM_OPERATION 111 I2c_int_config0 = 0x7e05, // I2CM_INT 112 I2c_int_config1 = 0x7e06, // I2CM_CTLINT 113 I2c_divider = 0x7e07, // I2CM_DIV 114 I2c_segment_address = 0x7e08, // I2CM_SEGADDR 115 I2c_software_reset = 0x7e09, // I2CM_SOFTRSTZ 116 I2c_segment_pointer = 0x7e0a, // I2CM_SEGPTR 117 118 // I2C for PHY. 119 120 I2c_phy_int_status = 0x108, // I2CMPHY_STAT0 121 I2c_phy_int_mask = 0x188, // MUTE_I2CMPHY_STAT0 122 123 I2c_phy_device_address = 0x3020, // PHY_I2CM_SLAVE_ADDR 124 I2c_phy_register = 0x3021, // PHY_I2CM_ADDRESS_ADDR 125 I2c_phy_data_out1 = 0x3022, // PHY_I2CM_DATAO_1_ADDR 126 I2c_phy_data_out0 = 0x3023, // PHY_I2CM_DATAO_0_ADDR 127 I2c_phy_data_in1 = 0x3024, // PHY_I2CM_DATAI_1_ADDR 128 I2c_phy_data_in0 = 0x3025, // PHY_I2CM_DATAI_0_ADDR 129 I2c_phy_operation = 0x3026, // PHY_I2CM_OPERATION_ADDR 130 I2c_phy_int_config0 = 0x3027, // PHY_I2CM_INT_ADDR 131 I2c_phy_int_config1 = 0x3028, // PHY_I2CM_CTLINT_ADDR 132 I2c_phy_divider = 0x3029, // PHY_I2CM_DIV_ADDR 133 I2c_phy_software_reset = 0x302a, // PHY_I2CM_SOFTRSTZ_ADDR 134 135 // PHY registers. 136 137 Phy_config = 0x3000, // PHY_CONF0 138 Phy_test0 = 0x3001, // PHY_TST0 139 Phy_test1 = 0x3002, // PHY_TST1 140 Phy_test2 = 0x3003, // PHY_TST2 141 Phy_status = 0x3004, // PHY_STAT0 142 Phy_int_config = 0x3005, // PHY_INT0 143 Phy_mask = 0x3006, // PHY_MASK0 144 Phy_polarity = 0x3007, // PHY_POL0 145 146 // Main controller registers. 147 148 Main_clock_disable = 0x4001, // MC_CLKDIS 149 Main_software_reset = 0x4002, // MC_SWRSTZ 150 Main_flow_control = 0x4004, // MC_FLOWCTRL 151 Main_reset = 0x4005, // MC_PHYRSTZ 152 Main_heac_phy_reset = 0x4007, // MC_HEACPHY_RST 153 154 // Frame composer registers for input video. 155 156 Fc_video_config = 0x1000, // FC_INVIDCONF 157 Fc_horizontal_active_width0 = 0x1001, // FC_INHACTV0 158 Fc_horizontal_active_width1 = 0x1002, // FC_INHACTV1 159 Fc_horizontal_blank_width0 = 0x1003, // FC_INHBLANK0 160 Fc_horizontal_blank_width1 = 0x1004, // FC_INHBLANK1 161 Fc_vertical_active_height0 = 0x1005, // FC_INVACTV0 162 Fc_vertical_active_height1 = 0x1006, // FC_INVACTV1 163 Fc_vertical_blank_height = 0x1007, // FC_INVBLANK 164 165 // Frame composer registers for sync pulses. 166 167 Fc_hsync_delay0 = 0x1008, // FC_HSYNCINDELAY0 168 Fc_hsync_delay1 = 0x1009, // FC_HSYNCINDELAY1 169 Fc_hsync_width0 = 0x100A, // FC_HSYNCINWIDTH0 170 Fc_hsync_width1 = 0x100B, // FC_HSYNCINWIDTH1 171 Fc_vsync_delay = 0x100C, // FC_VSYNCINDELAY 172 Fc_vsync_height = 0x100D, // FC_VSYNCINWIDTH 173 174 // Frame composer registers for video path configuration. 175 176 Fc_control_duration = 0x1011, // FC_CTRLDUR 177 Fc_ex_control_duration = 0x1012, // FC_EXCTRLDUR 178 Fc_ex_control_space = 0x1013, // FC_EXCTRLSPAC 179 Fc_channel0_preamble = 0x1014, // FC_CH0PREAM 180 Fc_channel1_preamble = 0x1015, // FC_CH1PREAM 181 Fc_channel2_preamble = 0x1016, // FC_CH2PREAM 182 183 // Colour space conversion registers. 184 185 Csc_config = 0x4100, // CSC_CFG 186 Csc_scale = 0x4101, // CSC_SCALE 187 188 // HDCP registers. 189 190 Hdcp_config0 = 0x5000, // A_HDCPCFG0 191 Hdcp_config1 = 0x5001, // A_HDCPCFG1 192 Hdcp_video_polarity = 0x5009, // A_VIDPOLCFG 193 194 // Video sample registers. 195 196 Sample_video_config = 0x0200, // TX_INVID0 197 Sample_video_stuffing = 0x0201, // TX_INSTUFFING 198 Sample_gy_data0 = 0x0202, // TX_GYDATA0 199 Sample_gy_data1 = 0x0203, // TX_GYDATA1 200 Sample_rcr_data0 = 0x0204, // TX_RCRDATA0 201 Sample_rcr_data1 = 0x0205, // TX_RCRDATA1 202 Sample_bcb_data0 = 0x0206, // TX_BCBDATA0 203 Sample_bcb_data1 = 0x0207, // TX_BCBDATA1 204 205 // Video packetizer registers. 206 207 Packet_status = 0x0800, // VP_STATUS 208 Packet_pr_cd = 0x0801, // VP_PR_CD 209 Packet_stuffing = 0x0802, // VP_STUFF 210 Packet_remap = 0x0803, // VP_REMAP 211 Packet_config = 0x0804, // VP_CONF 212 }; 213 214 // Identification values. 215 216 enum Product_id_values : uint8_t 217 { 218 Product_id0_transmitter = 0xa0, // PRODUCT_ID0_HDMI_TX 219 220 Product_id1_hdcp = 0xc0, // PRODUCT_ID1_HDCP 221 Product_id1_receiver = 0x02, // PRODUCT_ID1_HDMI_RX 222 Product_id1_transmitter = 0x01, // PRODUCT_ID1_HDMI_TX 223 }; 224 225 // Configuration values. 226 227 enum Config_id_values : uint8_t 228 { 229 Config_id0_i2s = 0x10, // CONFIG0_I2S 230 Config_id0_cec = 0x02, // CONFIG0_CEC 231 232 Config_id1_ahb = 0x01, // CONFIG1_AHB 233 234 Config2_dwc_hdmi_tx_phy = 0x00, // DWC_HDMI_TX_PHY 235 Config2_dwc_mhl_phy_heac = 0xb2, // DWC_MHL_PHY_HEAC 236 Config2_dwc_mhl_phy = 0xc2, // DWC_MHL_PHY 237 Config2_dwc_hdmi_3d_tx_phy_heac = 0xe2, // DWC_HDMI_3D_TX_PHY_HEAC 238 Config2_dwc_hdmi_3d_tx_phy = 0xf2, // DWC_HDMI_3D_TX_PHY 239 Config2_dwc_hdmi20_tx_phy = 0xf3, // DWC_HDMI20_TX_PHY 240 Config2_vendor_phy = 0xfe, // VENDOR_PHY 241 242 Config_id3_ahb_audio_dma = 0x02, // CONFIG3_AHBAUDDMA 243 Config_id3_gp_audio = 0x01, // CONFIG3_GPAUD 244 }; 245 246 // Status and mask bits. 247 248 enum Int_mask_bits : uint8_t 249 { 250 Int_mask_wakeup = 0x02, 251 Int_mask_all = 0x01, 252 }; 253 254 // I2C status and mask bits, also for PHY I2C. 255 256 enum I2c_int_status_bits : uint8_t 257 { 258 I2c_int_status_done = 0x02, 259 I2c_int_status_error = 0x01, 260 }; 261 262 // I2C operation bits. 263 264 enum I2c_operation_bits : uint8_t 265 { 266 I2c_operation_write = 0x10, 267 I2c_operation_segment_read = 0x02, // not PHY I2C 268 I2c_operation_read = 0x01, 269 }; 270 271 // Device addresses. 272 273 enum I2c_phy_device_addresses : uint8_t 274 { 275 I2c_phy_device_phy_gen2 = 0x69, // PHY_I2CM_SLAVE_ADDR_PHY_GEN2 276 I2c_phy_device_phy_heac = 0x49, // PHY_I2CM_SLAVE_ADDR_HEAC_PHY 277 }; 278 279 // Device registers. 280 281 enum I2c_phy_device_registers : uint8_t 282 { 283 I2c_phy_3d_tx_clock_cal_ctrl = 0x05, // 3D_TX_PHY_CKCALCTRL 284 I2c_phy_3d_tx_cpce_ctrl = 0x06, // 3D_TX_PHY_CPCE_CTRL 285 I2c_phy_3d_tx_clock_symbol_ctrl = 0x09, // 3D_TX_PHY_CKSYMTXCTRL 286 I2c_phy_3d_tx_vlevel_ctrl = 0x0e, // 3D_TX_PHY_VLEVCTRL 287 I2c_phy_3d_tx_curr_ctrl = 0x10, // 3D_TX_PHY_CURRCTRL 288 I2c_phy_3d_tx_pll_phby_ctrl = 0x13, // 3D_TX_PHY_PLLPHBYCTRL 289 I2c_phy_3d_tx_gmp_ctrl = 0x15, // 3D_TX_PHY_GMPCTRL 290 I2c_phy_3d_tx_msm_ctrl = 0x17, // 3D_TX_PHY_MSM_CTRL 291 I2c_phy_3d_tx_term = 0x19, // 3D_TX_PHY_TXTERM 292 }; 293 294 // PHY I2C register values. 295 296 enum Msm_ctrl_bits : uint16_t 297 { 298 Msm_ctrl_clock_output_select_fb = 1 << 3, // 3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK 299 }; 300 301 enum Clock_cal_ctrl_bits : uint16_t 302 { 303 Clock_cal_ctrl_override = 1 << 15, // 3D_TX_PHY_CKCALCTRL_OVERRIDE 304 }; 305 306 // Interrupt configuration bits, also for PHY I2C. 307 308 enum I2c_int_config0_bits : uint8_t 309 { 310 I2c_int_config0_done_polarity = 0x08, 311 I2c_int_config0_done_mask = 0x04, 312 }; 313 314 enum I2c_int_config1_bits : uint8_t 315 { 316 I2c_int_config1_nack_polarity = 0x80, 317 I2c_int_config1_nack_mask = 0x40, 318 I2c_int_config1_arb_polarity = 0x08, 319 I2c_int_config1_arb_mask = 0x04, 320 }; 321 322 // PHY configuration values. 323 324 enum Phy_config_bits : uint8_t 325 { 326 Phy_config_powerdown_disable = 0x80, // PHY_CONF0_PDZ_MASK 327 Phy_config_tmds = 0x40, // PHY_CONF0_ENTMDS_MASK 328 Phy_config_svsret = 0x20, // PHY_CONF0_SVSRET_MASK 329 Phy_config_gen2_powerdown = 0x10, // PHY_CONF0_GEN2_PDDQ_MASK 330 Phy_config_gen2_tx_power = 0x08, // PHY_CONF0_GEN2_TXPWRON_MASK 331 Phy_config_gen2_hotplug_detect_rx_sense = 0x04, // PHY_CONF0_GEN2_ENHPDRXSENSE_MASK 332 Phy_config_select_data_enable_polarity = 0x02, // PHY_CONF0_SELDATAENPOL_MASK 333 Phy_config_select_interface_control = 0x01, // PHY_CONF0_SELDIPIF_MASK 334 }; 335 336 enum Phy_test_bits : uint8_t 337 { 338 Phy_test0_clear_mask = 0x20, // PHY_TST0_TSTCLR_MASK 339 Phy_test0_enable_mask = 0x10, // PHY_TST0_TSTEN_MASK 340 Phy_test0_clock_mask = 0x01, // PHY_TST0_TSTCLK_MASK 341 }; 342 343 // PHY status and mask values. 344 345 enum Phy_status_bits : uint8_t 346 { 347 Phy_status_all = 0xf3, 348 Phy_status_rx_sense_all = 0xf0, 349 Phy_status_rx_sense3 = 0x80, // PHY_RX_SENSE3 350 Phy_status_rx_sense2 = 0x40, // PHY_RX_SENSE2 351 Phy_status_rx_sense1 = 0x20, // PHY_RX_SENSE1 352 Phy_status_rx_sense0 = 0x10, // PHY_RX_SENSE0 353 Phy_status_hotplug_detect = 0x02, // PHY_HPD 354 Phy_status_tx_phy_lock = 0x01, // PHY_TX_PHY_LOCK 355 Phy_status_none = 0, 356 }; 357 358 // PHY interrupt status and mask values. 359 360 enum Phy_int_status_bits : uint8_t 361 { 362 Phy_int_status_all = 0x3f, 363 Phy_int_status_rx_sense_all = 0x3c, 364 Phy_int_status_rx_sense3 = 0x20, // IH_PHY_STAT0_RX_SENSE3 365 Phy_int_status_rx_sense2 = 0x10, // IH_PHY_STAT0_RX_SENSE2 366 Phy_int_status_rx_sense1 = 0x08, // IH_PHY_STAT0_RX_SENSE1 367 Phy_int_status_rx_sense0 = 0x04, // IH_PHY_STAT0_RX_SENSE0 368 Phy_int_status_tx_phy_lock = 0x02, // IH_PHY_STAT0_TX_PHY_LOCK 369 Phy_int_status_hotplug_detect = 0x01, // IH_PHY_STAT0_HPD 370 Phy_int_status_none = 0, 371 }; 372 373 // PHY main register values. 374 375 enum Main_heac_phy_reset_bits : uint8_t 376 { 377 Main_heac_phy_reset_assert = 0x01, // MC_HEACPHY_RST_ASSERT 378 }; 379 380 enum Main_flow_control_bits : uint8_t 381 { 382 Main_flow_control_csc_active = 0x01, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH 383 Main_flow_control_csc_inactive = 0x00, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS 384 }; 385 386 enum Main_clock_disable_bits : uint8_t 387 { 388 Main_clock_disable_hdcp = 0x40, // MC_CLKDIS_HDCPCLK_DISABLE 389 Main_clock_disable_cec = 0x20, // MC_CLKDIS_CECCLK_DISABLE 390 Main_clock_disable_csc = 0x10, // MC_CLKDIS_CSCCLK_DISABLE 391 Main_clock_disable_audio = 0x08, // MC_CLKDIS_AUDCLK_DISABLE 392 Main_clock_disable_prep = 0x04, // MC_CLKDIS_PREPCLK_DISABLE 393 Main_clock_disable_tmds = 0x02, // MC_CLKDIS_TMDSCLK_DISABLE 394 Main_clock_disable_pixel = 0x01, // MC_CLKDIS_PIXELCLK_DISABLE 395 }; 396 397 enum Main_software_reset_bits : uint8_t 398 { 399 Main_software_reset_tmds = 0x02, // MC_SWRSTZ_TMDSSWRST_REQ 400 }; 401 402 // Frame composer values. 403 404 enum Fc_video_config_bits : uint8_t 405 { 406 Fc_video_config_hdcp_keepout_active = 0x80, // FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE 407 Fc_video_config_hdcp_keepout_inactive = 0x00, // FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE 408 Fc_video_config_vsync_active_high = 0x40, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH 409 Fc_video_config_vsync_active_low = 0x00, // FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW 410 Fc_video_config_hsync_active_high = 0x20, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH 411 Fc_video_config_hsync_active_low = 0x00, // FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW 412 Fc_video_config_data_enable_active_high = 0x10, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH 413 Fc_video_config_data_enable_active_low = 0x00, // FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW 414 Fc_video_config_hdmi_mode = 0x08, // FC_INVIDCONF_DVI_MODEZ_HDMI_MODE 415 Fc_video_config_dvi_mode = 0x00, // FC_INVIDCONF_DVI_MODEZ_DVI_MODE 416 Fc_video_config_osc_active_high = 0x02, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH 417 Fc_video_config_osc_active_low = 0x00, // FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW 418 Fc_video_config_interlaced = 0x01, // FC_INVIDCONF_IN_I_P_INTERLACED 419 Fc_video_config_progressive = 0x00, // FC_INVIDCONF_IN_I_P_PROGRESSIVE 420 }; 421 422 enum Fc_int_status2_bits : uint8_t 423 { 424 Fc_int_status2_overflow = 0x03, // FC_STAT2_OVERFLOW_MASK 425 Fc_int_status2_overflow_low = 0x02, // FC_STAT2_LOW_PRIORITY_OVERFLOW 426 Fc_int_status2_overflow_high = 0x01 // FC_STAT2_HIGH_PRIORITY_OVERFLOW, 427 }; 428 429 // Colour space conversion values. 430 431 enum Csc_config_bits : uint8_t 432 { 433 Csc_config_interpolation_mask = 0x30, // CSC_CFG_INTMODE_MASK 434 Csc_config_interpolation_disable = 0x00, // CSC_CFG_INTMODE_DISABLE 435 Csc_config_interpolation_form1 = 0x10, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 436 Csc_config_interpolation_form2 = 0x20, // CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 437 Csc_config_decimation_mask = 0x3, // CSC_CFG_DECMODE_MASK 438 Csc_config_decimation_disable = 0x0, // CSC_CFG_DECMODE_DISABLE 439 Csc_config_decimation_form1 = 0x1, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 440 Csc_config_decimation_form2 = 0x2, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 441 Csc_config_decimation_form3 = 0x3, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 442 }; 443 444 enum Csc_scale_bits : uint8_t 445 { 446 Csc_scale_colour_depth_mask = 0xf0, // CSC_SCALE_CSC_COLORDE_PTH_MASK 447 Csc_scale_colour_depth_24bpp = 0x00, // CSC_SCALE_CSC_COLORDE_PTH_24BPP 448 Csc_scale_colour_depth_30bpp = 0x50, // CSC_SCALE_CSC_COLORDE_PTH_30BPP 449 Csc_scale_colour_depth_36bpp = 0x60, // CSC_SCALE_CSC_COLORDE_PTH_36BPP 450 Csc_scale_colour_depth_48bpp = 0x70, // CSC_SCALE_CSC_COLORDE_PTH_48BPP 451 Csc_scale_mask = 0x03, // CSC_SCALE_CSCSCALE_MASK 452 }; 453 454 // HDCP register values. 455 456 enum Hdcp_config0_bits : uint8_t 457 { 458 Hdcp_config0_rxdetect_enable = 0x4, // A_HDCPCFG0_RXDETECT_ENABLE 459 }; 460 461 enum Hdcp_config1_bits : uint8_t 462 { 463 Hdcp_config1_encryption_disable = 0x2, // A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE 464 }; 465 466 enum Hdcp_video_polarity_bits : uint8_t 467 { 468 Hdcp_video_polarity_data_enable_active_high = 0x10, // A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH 469 }; 470 471 // Video sample register values. 472 473 enum Sample_video_config_bits : uint8_t 474 { 475 Sample_video_config_data_enable_active = 0x80, // TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE 476 Sample_video_config_mapping_mask = 0x1f, // TX_INVID0_VIDEO_MAPPING_MASK 477 }; 478 479 enum Sample_video_stuffing_bits : uint8_t 480 { 481 Sample_video_stuffing_bdb_data = 0x04, // TX_INSTUFFING_BDBDATA_STUFFING_ENABLE 482 Sample_video_stuffing_rcr_data = 0x02, // TX_INSTUFFING_RCRDATA_STUFFING_ENABLE 483 Sample_video_stuffing_gy_data = 0x01, // TX_INSTUFFING_GYDATA_STUFFING_ENABLE 484 }; 485 486 // Video packetizer register values. 487 488 enum Packet_stuffing_bits : uint8_t 489 { 490 Packet_stuffing_default_phase = 0x20, // VP_STUFF_IDEFAULT_PHASE_MASK 491 Packet_stuffing_ifix_pp_to_last = 0x10, // VP_STUFF_IFIX_PP_TO_LAST_MASK 492 Packet_stuffing_icx = 0x08, // VP_STUFF_ICX_GOTO_P0_ST_MASK 493 Packet_stuffing_ycc422 = 0x04, // VP_STUFF_YCC422_STUFFING_STUFFING_MODE 494 Packet_stuffing_pp = 0x02, // VP_STUFF_PP_STUFFING_STUFFING_MODE 495 Packet_stuffing_pr = 0x01, // VP_STUFF_PR_STUFFING_STUFFING_MODE 496 }; 497 498 enum Packet_config_bits : uint8_t 499 { 500 Packet_config_bypass_enable = 0x40, // VP_CONF_BYPASS_EN_ENABLE 501 Packet_config_pp_enable = 0x20, // VP_CONF_PP_EN_ENABLE 502 Packet_config_pr_enable = 0x10, // VP_CONF_PR_EN_ENABLE 503 Packet_config_ycc422_enable = 0x8, // VP_CONF_YCC422_EN_ENABLE 504 Packet_config_bypass_select_packetizer = 0x4, // VP_CONF_BYPASS_SELECT_VID_PACKETIZER 505 Packet_config_output_selector_mask = 0x3, // VP_CONF_OUTPUT_SELECTOR_MASK 506 Packet_config_output_selector_bypass = 0x3, // VP_CONF_OUTPUT_SELECTOR_BYPASS 507 Packet_config_output_selector_ycc422 = 0x1, // VP_CONF_OUTPUT_SELECTOR_YCC422 508 Packet_config_output_selector_pp = 0x0, // VP_CONF_OUTPUT_SELECTOR_PP 509 }; 510 511 enum Packet_remap_bits : uint8_t 512 { 513 Packet_remap_mask = 0x3, // VP_REMAP_MASK 514 Packet_remap_ycc422_24bit = 0x2, // VP_REMAP_YCC422_24bit 515 Packet_remap_ycc422_20bit = 0x1, // VP_REMAP_YCC422_20bit 516 Packet_remap_ycc422_16bit = 0x0, // VP_REMAP_YCC422_16bit 517 }; 518 519 enum Packet_pr_cd_bits : uint8_t 520 { 521 Packet_pr_cd_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK 522 Packet_pr_cd_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET 523 Packet_pr_cd_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK 524 Packet_pr_cd_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET 525 }; 526 527 528 529 // PHY capabilities. 530 531 static const Phy_capabilities phy_capabilities[] = { 532 // name gen svsret configure 533 {Config2_dwc_hdmi_tx_phy, "DWC_HDMI_TX_PHY", 1, false, false}, 534 {Config2_dwc_mhl_phy_heac, "DWC_MHL_PHY_HEAC", 2, true, true}, 535 {Config2_dwc_mhl_phy, "DWC_MHL_PHY", 2, true, true}, 536 {Config2_dwc_hdmi_3d_tx_phy_heac, "DWC_HDMI_3D_TX_PHY_HEAC", 2, false, true}, 537 {Config2_dwc_hdmi_3d_tx_phy, "DWC_HDMI_3D_TX_PHY", 2, false, true}, 538 {Config2_dwc_hdmi20_tx_phy, "DWC_HDMI20_TX_PHY", 2, true, true}, 539 {0, "Vendor PHY", 0, false, false}, 540 }; 541 542 543 544 // PHY configuration, adopting the Linux driver's tables of values. 545 546 static const struct Phy_mpll_config phy_mpll_config[] = { 547 // 8bpc 10bpc 12bpc 548 // pixelclock cpce gmp cpce gmp cpce gmp 549 { 45250000, { {0x01e0, 0x0000}, {0x21e1, 0x0000}, {0x41e2, 0x0000} } }, 550 { 92500000, { {0x0140, 0x0005}, {0x2141, 0x0005}, {0x4142, 0x0005} } }, 551 { 148500000, { {0x00a0, 0x000a}, {0x20a1, 0x000a}, {0x40a2, 0x000a} } }, 552 { 216000000, { {0x00a0, 0x000a}, {0x2001, 0x000f}, {0x4002, 0x000f} } }, 553 { ~0UL, { {0x0000, 0x0000}, {0x0000, 0x0000}, {0x0000, 0x0000} } } 554 }; 555 556 static const struct Phy_curr_ctrl phy_curr_ctrl[] = { 557 // pixelclock 8bpc 10bpc 12bpc 558 { 54000000, {0x091c, 0x091c, 0x06dc} }, 559 { 58400000, {0x091c, 0x06dc, 0x06dc} }, 560 { 72000000, {0x06dc, 0x06dc, 0x091c} }, 561 { 74250000, {0x06dc, 0x0b5c, 0x091c} }, 562 { 118800000, {0x091c, 0x091c, 0x06dc} }, 563 { 216000000, {0x06dc, 0x0b5c, 0x091c} }, 564 { ~0UL, {0x0000, 0x0000, 0x0000} } 565 }; 566 567 static const struct Phy_config phy_config[] = { 568 // pixelclock symbol term vlevel 569 { 216000000, 0x800d, 0x0005, 0x01ad}, 570 { ~0UL, 0x0000, 0x0000, 0x0000} 571 }; 572 573 574 575 // Initialise the HDMI peripheral. 576 577 Hdmi_jz4780_chip::Hdmi_jz4780_chip(l4_addr_t start, l4_addr_t end, 578 l4_cap_idx_t irq, 579 struct Jz4740_lcd_panel *panel) 580 : _start(start), _end(end), _irq(irq), _panel(panel) 581 { 582 // 8-bit registers with 2-bit address shifting. 583 584 _regs = new Hw::Mmio_register_block<8>(start, 2); 585 586 // Initialise I2C state for DDC. 587 588 _segment_read = false; 589 _device_register = 0; 590 591 // Initialise I2C state for PHY initialisation. 592 593 _phy_device_register = 0; 594 595 // Initialise identifying details and capabilities of the hardware. 596 597 get_identification(); 598 599 // Reset interrupts to a minimal, enabled state. 600 601 irq_init(); 602 603 // Set up DDC and PHY communication. 604 605 i2c_init(I2c_software_reset, I2c_divider, I2c_int_config0, I2c_int_config1, 606 I2c_int_status, I2c_int_mask); 607 i2c_init(I2c_phy_software_reset, I2c_phy_divider, I2c_phy_int_config0, I2c_phy_int_config1, 608 I2c_phy_int_status, I2c_phy_int_mask); 609 610 // Enable PHY interrupts. 611 612 phy_irq_init(); 613 } 614 615 // Pixel clock frequency calculation. 616 617 unsigned long Hdmi_jz4780_chip::get_pixelclock() 618 { 619 return _pixelclock; 620 621 /* Calculated frequency, which may not be the actual pixelclock frequency... 622 623 return (_panel->line_start + _panel->width + _panel->line_end + _panel->hsync) * 624 (_panel->frame_start + _panel->height + _panel->frame_end + _panel->vsync) * 625 _panel->frame_rate; 626 */ 627 } 628 629 630 631 // Update a register by enabling/setting or disabling/clearing the given bits. 632 633 void Hdmi_jz4780_chip::reg_update(uint32_t reg, uint32_t bits, bool enable) 634 { 635 if (enable) 636 _regs[reg] = _regs[reg] | bits; 637 else 638 _regs[reg] = _regs[reg] & ~bits; 639 } 640 641 // Update a field. The bits must be shifted to coincide with the mask. 642 643 void Hdmi_jz4780_chip::reg_update_field(uint32_t reg, uint32_t mask, uint32_t bits) 644 { 645 _regs[reg] = (_regs[reg] & ~(mask)) | (bits & mask); 646 } 647 648 void Hdmi_jz4780_chip::reg_fill_field(uint32_t reg, uint32_t mask) 649 { 650 _regs[reg] = _regs[reg] | mask; 651 } 652 653 654 655 // Chipset querying. 656 657 void Hdmi_jz4780_chip::get_identification() 658 { 659 _version = (_regs[Design_id] << 8) | _regs[Revision_id]; 660 _phy_type = _regs[Config_id2]; 661 662 // Initialise a member to any matching capabilities or leave it as the "null" 663 // entry. 664 665 _phy_def = phy_capabilities; 666 667 while (_phy_def->gen && (_phy_def->type != _phy_type)) 668 _phy_def++; 669 } 670 671 void Hdmi_jz4780_chip::get_version(uint8_t *major, uint16_t *minor) 672 { 673 *major = (_version >> 12) & 0xfff; 674 *minor = _version & 0xfff; 675 } 676 677 void Hdmi_jz4780_chip::get_phy_capabilities(const struct Phy_capabilities **phy_def) 678 { 679 *phy_def = _phy_def; 680 } 681 682 683 684 // Initialisation. 685 686 void Hdmi_jz4780_chip::irq_init() 687 { 688 // Disable interrupts. 689 690 _regs[Int_mask] = _regs[Int_mask] | (Int_mask_wakeup | Int_mask_all); 691 692 // Mask all interrupts. 693 694 _regs[Fc_int_mask0] = 0xff; 695 _regs[Fc_int_mask1] = 0xff; 696 _regs[Fc_int_mask2] = 0xff; 697 _regs[As_int_mask] = 0xff; 698 _regs[Phy_int_mask] = 0xff; 699 _regs[I2c_int_mask] = 0xff; 700 _regs[I2c_phy_int_mask] = 0xff; 701 _regs[Cec_int_mask] = 0xff; 702 _regs[Vp_int_mask] = 0xff; 703 _regs[Ahb_dma_audio_int_mask] = 0xff; 704 705 // Enable interrupts. 706 707 _regs[Int_mask] = _regs[Int_mask] & ~(Int_mask_wakeup | Int_mask_all); 708 } 709 710 void Hdmi_jz4780_chip::phy_irq_init() 711 { 712 // Set PHY interrupt polarities. 713 714 _regs[Phy_polarity] = Phy_status_all; 715 716 // Enable/unmask second-level interrupts. 717 718 _regs[Phy_mask] = _regs[Phy_mask] & ~(Phy_status_all); 719 720 // Clear pending interrupts. 721 722 _regs[Phy_int_status] = Phy_int_status_all; 723 724 // Enable/unmask interrupts. 725 726 _regs[Phy_int_mask] = _regs[Phy_int_mask] & ~(Phy_int_status_all); 727 } 728 729 730 731 // I2C support. 732 733 void Hdmi_jz4780_chip::i2c_init(uint32_t reset, uint32_t divider, 734 uint32_t config0, uint32_t config1, 735 uint32_t status, uint32_t mask) 736 { 737 // Software reset. 738 739 _regs[reset] = 0; 740 741 // Standard mode (100kHz). 742 743 _regs[divider] = 0; 744 745 // Set interrupt polarities. 746 747 _regs[config0] = I2c_int_config0_done_polarity; 748 _regs[config1] = I2c_int_config1_nack_polarity | I2c_int_config1_arb_polarity; 749 750 // Clear and mask/mute interrupts. 751 752 _regs[status] = I2c_int_status_done | I2c_int_status_error; 753 _regs[mask] = I2c_int_status_done | I2c_int_status_error; 754 } 755 756 long Hdmi_jz4780_chip::i2c_wait(uint32_t status) 757 { 758 long err; 759 uint8_t int_status; 760 l4_msgtag_t tag; 761 762 do 763 { 764 tag = l4_irq_receive(_irq, L4_IPC_NEVER); 765 766 err = l4_ipc_error(tag, l4_utcb()); 767 if (err) 768 return err; 769 770 int_status = _regs[status]; 771 772 // Test for an error condition. 773 774 if (int_status & I2c_int_status_error) 775 return -L4_EIO; 776 777 // Acknowledge the interrupt. 778 779 _regs[status] = int_status; 780 781 } while (!(int_status & I2c_int_status_done)); 782 783 return L4_EOK; 784 } 785 786 int Hdmi_jz4780_chip::i2c_read(uint8_t *buf, unsigned int length) 787 { 788 unsigned int i; 789 long err; 790 791 // Unmask interrupts. 792 793 _regs[I2c_int_mask] = 0; 794 795 for (i = 0; i < length; i++) 796 { 797 // Increment the device register. 798 799 _regs[I2c_register] = _device_register++; 800 _regs[I2c_operation] = _segment_read ? I2c_operation_segment_read 801 : I2c_operation_read; 802 803 // Wait and then read. 804 805 err = i2c_wait(I2c_int_status); 806 if (err) 807 break; 808 809 buf[i] = _regs[I2c_data_in]; 810 } 811 812 // Mask interrupts again. 813 814 _regs[I2c_int_mask] = I2c_int_status_done | I2c_int_status_error; 815 816 return i; 817 } 818 819 int Hdmi_jz4780_chip::i2c_phy_write(uint8_t address, uint16_t value) 820 { 821 i2c_phy_set_address(address); 822 return i2c_phy_write(&value, 1); 823 } 824 825 int Hdmi_jz4780_chip::i2c_phy_write(uint16_t *buf, unsigned int length) 826 { 827 unsigned int i; 828 long err; 829 830 // Unmask interrupts. 831 832 _regs[I2c_phy_int_mask] = 0; 833 834 for (i = 0; i < length; i++) 835 { 836 // Increment the device register. 837 838 _regs[I2c_phy_register] = _device_register++; 839 _regs[I2c_phy_operation] = I2c_operation_write; 840 841 // Write and then wait. 842 843 _regs[I2c_phy_data_out1] = (buf[i] >> 8) & 0xff; 844 _regs[I2c_phy_data_out0] = buf[i] & 0xff; 845 846 err = i2c_wait(I2c_phy_int_status); 847 if (err) 848 break; 849 } 850 851 // Mask interrupts again. 852 853 _regs[I2c_phy_int_mask] = I2c_int_status_done | I2c_int_status_error; 854 855 return i; 856 } 857 858 void Hdmi_jz4780_chip::i2c_set_address(uint8_t address) 859 { 860 _regs[I2c_device_address] = address; 861 _segment_read = false; 862 i2c_set_register(0); 863 } 864 865 void Hdmi_jz4780_chip::i2c_phy_set_address(uint8_t address) 866 { 867 // The Linux drivers seem to set the clear field when changing the PHY device 868 // address, presumably because some manual says so. 869 870 _regs[Phy_test0] = _regs[Phy_test0] | Phy_test0_clear_mask; 871 _regs[I2c_phy_device_address] = address; 872 _regs[Phy_test0] = _regs[Phy_test0] & ~Phy_test0_clear_mask; 873 874 i2c_phy_set_register(0); 875 } 876 877 void Hdmi_jz4780_chip::i2c_set_segment(uint8_t segment) 878 { 879 _regs[I2c_segment_address] = 0x30; 880 _regs[I2c_segment_pointer] = segment; 881 _segment_read = true; 882 i2c_set_register(0); 883 } 884 885 void Hdmi_jz4780_chip::i2c_set_register(uint8_t device_register) 886 { 887 _device_register = device_register; 888 } 889 890 void Hdmi_jz4780_chip::i2c_phy_set_register(uint8_t device_register) 891 { 892 _phy_device_register = device_register; 893 } 894 895 896 897 // PHY operations. 898 899 void Hdmi_jz4780_chip::phy_enable_powerdown(bool enable) 900 { 901 reg_update(Phy_config, Phy_config_powerdown_disable, !enable); 902 } 903 904 void Hdmi_jz4780_chip::phy_enable_tmds(bool enable) 905 { 906 reg_update(Phy_config, Phy_config_tmds, enable); 907 } 908 909 void Hdmi_jz4780_chip::phy_enable_svsret(bool enable) 910 { 911 reg_update(Phy_config, Phy_config_svsret, enable); 912 } 913 914 void Hdmi_jz4780_chip::phy_enable_gen2_powerdown(bool enable) 915 { 916 reg_update(Phy_config, Phy_config_gen2_powerdown, enable); 917 } 918 919 void Hdmi_jz4780_chip::phy_enable_gen2_tx_power(bool enable) 920 { 921 reg_update(Phy_config, Phy_config_gen2_tx_power, enable); 922 } 923 924 void Hdmi_jz4780_chip::phy_enable_interface(bool enable) 925 { 926 reg_update(Phy_config, Phy_config_select_data_enable_polarity, enable); 927 reg_update(Phy_config, Phy_config_select_interface_control, !enable); 928 } 929 930 // Configure the PHY. Various things not supported by the JZ4780 PHY are ignored 931 // such as the TDMS clock ratio (dependent on HDMI 2 and content scrambling). 932 933 long Hdmi_jz4780_chip::phy_configure() 934 { 935 long err; 936 937 phy_power_off(); 938 939 if (_phy_def->svsret) 940 phy_enable_svsret(true); 941 942 phy_reset(); 943 944 _regs[Main_heac_phy_reset] = Main_heac_phy_reset_assert; 945 946 i2c_phy_set_address(I2c_phy_device_phy_gen2); 947 948 if (_phy_def->configure) 949 { 950 err = phy_configure_specific(); 951 if (err) 952 return err; 953 } 954 955 // NOTE: TMDS clock delay here in Linux driver. 956 957 phy_power_on(); 958 959 return L4_EOK; 960 } 961 962 // Configure for the JZ4780 specifically. 963 964 long Hdmi_jz4780_chip::phy_configure_specific() 965 { 966 const struct Phy_mpll_config *m = phy_mpll_config; 967 const struct Phy_curr_ctrl *c = phy_curr_ctrl; 968 const struct Phy_config *p = phy_config; 969 unsigned long pixelclock = get_pixelclock(); 970 971 // Find MPLL, CURR_CTRL and PHY configuration settings appropriate for the 972 // pixel clock frequency. 973 974 while (m->pixelclock && (pixelclock > m->pixelclock)) 975 m++; 976 977 while (c->pixelclock && (pixelclock > c->pixelclock)) 978 c++; 979 980 while (p->pixelclock && (pixelclock > p->pixelclock)) 981 p++; 982 983 if (!m->pixelclock || !c->pixelclock || !p->pixelclock) 984 return -L4_EINVAL; 985 986 // Using values for 8bpc from the tables. 987 988 // Initialise MPLL. 989 990 i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, m->res[Phy_resolution_8bpc].cpce); 991 i2c_phy_write(I2c_phy_3d_tx_gmp_ctrl, m->res[Phy_resolution_8bpc].gmp); 992 993 // Initialise CURRCTRL. 994 995 i2c_phy_write(I2c_phy_3d_tx_cpce_ctrl, c->curr[Phy_resolution_8bpc]); 996 997 // Initialise PHY_CONFIG. 998 999 i2c_phy_write(I2c_phy_3d_tx_pll_phby_ctrl, 0); 1000 i2c_phy_write(I2c_phy_3d_tx_msm_ctrl, Msm_ctrl_clock_output_select_fb); 1001 1002 i2c_phy_write(I2c_phy_3d_tx_term, p->term); 1003 i2c_phy_write(I2c_phy_3d_tx_clock_symbol_ctrl, p->symbol); 1004 i2c_phy_write(I2c_phy_3d_tx_vlevel_ctrl, p->vlevel); 1005 1006 // Override and disable clock termination. 1007 1008 i2c_phy_write(I2c_phy_3d_tx_clock_cal_ctrl, Clock_cal_ctrl_override); 1009 1010 return L4_EOK; 1011 } 1012 1013 long Hdmi_jz4780_chip::phy_init() 1014 { 1015 long err; 1016 int i; 1017 1018 // Initialisation repeated for HDMI PHY specification reasons. 1019 1020 for (i = 0; i < 2; i++) 1021 { 1022 phy_enable_interface(true); 1023 err = phy_configure(); 1024 if (err) 1025 return err; 1026 } 1027 1028 return L4_EOK; 1029 } 1030 1031 void Hdmi_jz4780_chip::phy_reset() 1032 { 1033 _regs[Main_reset] = 1; 1034 _regs[Main_reset] = 0; 1035 } 1036 1037 void Hdmi_jz4780_chip::phy_power_off() 1038 { 1039 if (_phy_def && (_phy_def->gen == 1)) 1040 { 1041 phy_enable_tmds(false); 1042 phy_enable_powerdown(true); 1043 return; 1044 } 1045 1046 phy_enable_gen2_tx_power(false); 1047 1048 wait_for_tx_phy_lock(0); 1049 1050 phy_enable_gen2_powerdown(true); 1051 } 1052 1053 void Hdmi_jz4780_chip::phy_power_on() 1054 { 1055 if (_phy_def && (_phy_def->gen == 1)) 1056 { 1057 phy_enable_powerdown(false); 1058 phy_enable_tmds(false); 1059 phy_enable_tmds(true); 1060 return; 1061 } 1062 1063 phy_enable_gen2_tx_power(true); 1064 phy_enable_gen2_powerdown(false); 1065 1066 wait_for_tx_phy_lock(1); 1067 } 1068 1069 1070 1071 // Hotplug detection. 1072 1073 bool Hdmi_jz4780_chip::connected() 1074 { 1075 return (_regs[Phy_status] & Phy_status_hotplug_detect) != 0; 1076 } 1077 1078 long Hdmi_jz4780_chip::wait_for_connection() 1079 { 1080 return wait_for_phy_irq(Phy_int_status_hotplug_detect, Phy_status_hotplug_detect, 1081 Phy_status_hotplug_detect); 1082 } 1083 1084 // General PHY interrupt handling. 1085 1086 long Hdmi_jz4780_chip::wait_for_phy_irq(uint32_t int_status_flags, 1087 uint32_t status_flags, 1088 uint32_t status_values) 1089 { 1090 long err; 1091 uint8_t int_status, status; 1092 uint8_t status_unchanged = ~(status_values) & status_flags; 1093 l4_msgtag_t tag; 1094 1095 do 1096 { 1097 tag = l4_irq_receive(_irq, L4_IPC_NEVER); 1098 1099 err = l4_ipc_error(tag, l4_utcb()); 1100 if (err) 1101 return err; 1102 1103 // Obtain the details. 1104 1105 int_status = _regs[Phy_int_status]; 1106 status = _regs[Phy_status]; 1107 1108 // Acknowledge the interrupt. 1109 1110 _regs[Phy_int_status] = int_status_flags; 1111 1112 // Continue without a handled event. 1113 // An event is handled when detected and when the status differs from 1114 // the unchanged state. 1115 1116 } while (!((int_status & int_status_flags) && 1117 ((status & status_flags) ^ status_unchanged))); 1118 1119 return L4_EOK; 1120 } 1121 1122 // Wait for TX_PHY_LOCK to become high or low. 1123 1124 long Hdmi_jz4780_chip::wait_for_tx_phy_lock(int level) 1125 { 1126 if (!!(_regs[Phy_status] & Phy_status_tx_phy_lock) == level) 1127 return L4_EOK; 1128 1129 return wait_for_phy_irq(Phy_int_status_tx_phy_lock, Phy_status_tx_phy_lock, 1130 level ? Phy_status_tx_phy_lock : Phy_status_none); 1131 } 1132 1133 1134 1135 // Output setup operations. 1136 1137 long Hdmi_jz4780_chip::enable(unsigned long pixelclock) 1138 { 1139 _pixelclock = pixelclock; 1140 1141 // Disable frame composer overflow interrupts. 1142 1143 enable_overflow_irq(false); 1144 1145 // NOTE: Here, CEA modes are normally detected and thus the output encoding. 1146 // NOTE: Instead, a fixed RGB output encoding and format is used. 1147 // NOTE: Meanwhile, the input encoding and format will also be fixed to a RGB 1148 // NOTE: representation. 1149 1150 // _bits_per_channel = 8; 1151 // _data_enable_polarity = true; 1152 1153 // HDMI initialisation "step B.1": video frame initialisation. 1154 1155 frame_init(); 1156 1157 // HDMI initialisation "step B.2": PHY initialisation. 1158 1159 long err = phy_init(); 1160 if (err) 1161 return err; 1162 1163 // HDMI initialisation "step B.3": video signal initialisation. 1164 1165 data_path_init(); 1166 1167 // With audio, various clock updates are needed. 1168 1169 // NOTE: DVI mode is being assumed for now, for simplicity. 1170 1171 // In non-DVI mode, the AVI, vendor-specific infoframe and regular infoframe 1172 // are set up. 1173 1174 packet_init(); 1175 csc_init(); 1176 sample_init(); 1177 hdcp_init(); 1178 1179 // Enable frame composer overflow interrupts. 1180 1181 enable_overflow_irq(true); 1182 1183 return L4_EOK; 1184 } 1185 1186 void Hdmi_jz4780_chip::enable_overflow_irq(bool enable) 1187 { 1188 if (!enable) 1189 reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable); 1190 1191 // Apparent workaround required. 1192 1193 else 1194 { 1195 uint8_t config = _regs[Fc_video_config]; 1196 1197 _regs[Main_software_reset] = ~(Main_software_reset_tmds); 1198 1199 for (int i = 0; i < 4; i++) 1200 _regs[Fc_video_config] = config; 1201 } 1202 } 1203 1204 void Hdmi_jz4780_chip::frame_init() 1205 { 1206 // Initialise the video configuration. This is rather like the initialisation 1207 // of the LCD controller. The sync and data enable polarities are set up, plus 1208 // extras like HDCP, DVI mode, progressive/interlace. 1209 // NOTE: Here, the JZ4740-specific configuration is used to store the picture 1210 // NOTE: properties, but a neutral structure should be adopted. 1211 1212 uint8_t config = 0; 1213 1214 config |= (_panel->config & Jz4740_lcd_hsync_negative) 1215 ? Fc_video_config_hsync_active_low 1216 : Fc_video_config_hsync_active_high; 1217 1218 config |= (_panel->config & Jz4740_lcd_vsync_negative) 1219 ? Fc_video_config_vsync_active_low 1220 : Fc_video_config_vsync_active_high; 1221 1222 config |= (_panel->config & Jz4740_lcd_de_negative) 1223 ? Fc_video_config_data_enable_active_low 1224 : Fc_video_config_data_enable_active_high; 1225 1226 // NOTE: Only supporting DVI mode so far. 1227 1228 config |= Fc_video_config_dvi_mode; 1229 1230 // NOTE: Not supporting HDCP. 1231 1232 config |= Fc_video_config_hdcp_keepout_inactive; 1233 1234 // NOTE: Only supporting progressive scan so far. 1235 1236 config |= Fc_video_config_progressive; 1237 config |= Fc_video_config_osc_active_low; 1238 1239 _regs[Fc_video_config] = config; 1240 1241 // Then, the frame characteristics (visible area, sync pulse) are set. Indeed, 1242 // the frame area details should be practically the same as those used by the 1243 // LCD controller. 1244 1245 uint16_t hblank = _panel->line_start + _panel->line_end + _panel->hsync, 1246 vblank = _panel->frame_start + _panel->frame_end + _panel->vsync, 1247 hsync_delay = _panel->line_end, 1248 vsync_delay = _panel->frame_end, 1249 hsync_width = _panel->hsync, 1250 vsync_height = _panel->vsync; 1251 1252 _regs[Fc_horizontal_active_width1] = (_panel->width >> 8) & 0xff; 1253 _regs[Fc_horizontal_active_width0] = _panel->width & 0xff; 1254 1255 _regs[Fc_horizontal_blank_width1] = (hblank >> 8) & 0xff; 1256 _regs[Fc_horizontal_blank_width0] = hblank & 0xff; 1257 1258 _regs[Fc_vertical_active_height1] = (_panel->height >> 8) & 0xff; 1259 _regs[Fc_vertical_active_height0] = _panel->height & 0xff; 1260 1261 _regs[Fc_vertical_blank_height] = vblank & 0xff; 1262 1263 _regs[Fc_hsync_delay1] = (hsync_delay >> 8) & 0xff; 1264 _regs[Fc_hsync_delay0] = hsync_delay & 0xff; 1265 1266 _regs[Fc_vsync_delay] = vsync_delay & 0xff; 1267 1268 _regs[Fc_hsync_width1] = (hsync_width >> 8) & 0xff; 1269 _regs[Fc_hsync_width0] = hsync_width & 0xff; 1270 1271 _regs[Fc_vsync_height] = vsync_height & 0xff; 1272 } 1273 1274 void Hdmi_jz4780_chip::data_path_init() 1275 { 1276 // Initialise the path of the video data. Here, the elements of the data 1277 // stream are defined such as the control period duration, data channel 1278 // characteristics, pixel and TMDS clocks, and the involvement of colour space 1279 // conversion. 1280 1281 // Control period minimum duration. 1282 1283 _regs[Fc_control_duration] = 12; 1284 _regs[Fc_ex_control_duration] = 32; 1285 _regs[Fc_ex_control_space] = 1; 1286 1287 // Set to fill TMDS data channels. 1288 1289 _regs[Fc_channel0_preamble] = 0x0b; 1290 _regs[Fc_channel1_preamble] = 0x16; 1291 _regs[Fc_channel2_preamble] = 0x21; 1292 1293 // Apparent two-stage clock activation. 1294 1295 uint8_t clock_disable = Main_clock_disable_hdcp | 1296 Main_clock_disable_csc | 1297 Main_clock_disable_audio | 1298 Main_clock_disable_prep | 1299 Main_clock_disable_tmds; 1300 1301 // Activate the pixel clock. 1302 1303 _regs[Main_clock_disable] = clock_disable; 1304 1305 // Then activate the TMDS clock. 1306 1307 clock_disable &= ~(Main_clock_disable_tmds); 1308 _regs[Main_clock_disable] = clock_disable; 1309 1310 // NOTE: Bypass colour space conversion for now. 1311 1312 _regs[Main_flow_control] = Main_flow_control_csc_inactive; 1313 } 1314 1315 void Hdmi_jz4780_chip::packet_init() 1316 { 1317 // Initialise the video packet details. 1318 // NOTE: With 24bpp RGB output only for now, no pixel repetition. 1319 1320 int colour_depth = 4; 1321 1322 _regs[Packet_pr_cd] = 1323 ((colour_depth << Packet_pr_cd_depth_offset) & 1324 Packet_pr_cd_depth_mask); 1325 1326 _regs[Packet_remap] = Packet_remap_ycc422_16bit; 1327 1328 reg_fill_field(Packet_stuffing, Packet_stuffing_pr | 1329 Packet_stuffing_default_phase | 1330 Packet_stuffing_pp | 1331 Packet_stuffing_ycc422); 1332 1333 // Disable pixel repeater. 1334 1335 reg_update_field(Packet_config, Packet_config_bypass_enable | 1336 Packet_config_pr_enable | 1337 Packet_config_pp_enable | 1338 Packet_config_ycc422_enable | 1339 Packet_config_bypass_select_packetizer | 1340 Packet_config_output_selector_mask, 1341 Packet_config_bypass_enable | 1342 Packet_config_bypass_select_packetizer | 1343 Packet_config_output_selector_bypass); 1344 } 1345 1346 void Hdmi_jz4780_chip::csc_init() 1347 { 1348 // Initialise the colour space conversion details. 1349 // NOTE: No conversion will be done yet (see data_path_init). 1350 1351 _regs[Csc_config] = Csc_config_interpolation_disable | 1352 Csc_config_decimation_disable; 1353 1354 // NOTE: Use 8bpc (24bpp) for now. 1355 1356 reg_update_field(Csc_scale, Csc_scale_colour_depth_mask, Csc_scale_colour_depth_24bpp); 1357 1358 // NOTE: Coefficients should be set here. 1359 } 1360 1361 void Hdmi_jz4780_chip::sample_init() 1362 { 1363 // Initialise the mapping of video input data. 1364 // NOTE: With 24bpp RGB input only for now. 1365 1366 int colour_format = 0x01; 1367 1368 // Data enable inactive. 1369 1370 _regs[Sample_video_config] = (colour_format & Sample_video_config_mapping_mask); 1371 1372 // Transmission stuffing when data enable is inactive. 1373 1374 _regs[Sample_video_stuffing] = Sample_video_stuffing_bdb_data | 1375 Sample_video_stuffing_rcr_data | 1376 Sample_video_stuffing_gy_data; 1377 1378 _regs[Sample_gy_data0] = 0; 1379 _regs[Sample_gy_data1] = 0; 1380 _regs[Sample_rcr_data0] = 0; 1381 _regs[Sample_rcr_data1] = 0; 1382 _regs[Sample_bcb_data0] = 0; 1383 _regs[Sample_bcb_data1] = 0; 1384 } 1385 1386 void Hdmi_jz4780_chip::hdcp_init() 1387 { 1388 // Initialise HDCP registers, mostly turning things off. 1389 1390 reg_update(Hdcp_config0, Hdcp_config0_rxdetect_enable, false); 1391 1392 reg_update(Hdcp_video_polarity, 1393 Hdcp_video_polarity_data_enable_active_high, 1394 !(_panel->config & Jz4740_lcd_de_negative)); 1395 1396 reg_update(Hdcp_config1, Hdcp_config1_encryption_disable, true); 1397 } 1398 1399 1400 1401 // C language interface functions. 1402 1403 void *jz4780_hdmi_init(l4_addr_t start, l4_addr_t end, l4_cap_idx_t irq, 1404 struct Jz4740_lcd_panel *panel) 1405 { 1406 return (void *) new Hdmi_jz4780_chip(start, end, irq, panel); 1407 } 1408 1409 void jz4780_hdmi_get_version(void *hdmi, uint8_t *major, uint16_t *minor) 1410 { 1411 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_version(major, minor); 1412 } 1413 1414 void jz4780_hdmi_get_phy_capabilities(void *hdmi, const struct Phy_capabilities **phy_def) 1415 { 1416 static_cast<Hdmi_jz4780_chip *>(hdmi)->get_phy_capabilities(phy_def); 1417 } 1418 1419 int jz4780_hdmi_i2c_read(void *hdmi, uint8_t *buf, unsigned int length) 1420 { 1421 return static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_read(buf, length); 1422 } 1423 1424 void jz4780_hdmi_i2c_set_address(void *hdmi, uint8_t address) 1425 { 1426 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_address(address); 1427 } 1428 1429 void jz4780_hdmi_i2c_set_segment(void *hdmi, uint8_t segment) 1430 { 1431 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_segment(segment); 1432 } 1433 1434 void jz4780_hdmi_i2c_set_register(void *hdmi, uint8_t device_register) 1435 { 1436 static_cast<Hdmi_jz4780_chip *>(hdmi)->i2c_set_register(device_register); 1437 } 1438 1439 int jz4780_hdmi_connected(void *hdmi) 1440 { 1441 return (int) static_cast<Hdmi_jz4780_chip *>(hdmi)->connected(); 1442 } 1443 1444 long jz4780_hdmi_wait_for_connection(void *hdmi) 1445 { 1446 return static_cast<Hdmi_jz4780_chip *>(hdmi)->wait_for_connection(); 1447 } 1448 1449 long jz4780_hdmi_enable(void *hdmi, unsigned long pixelclock) 1450 { 1451 return static_cast<Hdmi_jz4780_chip *>(hdmi)->enable(pixelclock); 1452 }