1 /* 2 * DMA support for the X1600. 3 * 4 * Copyright (C) 2021, 2023, 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/dma-x1600.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/ipc.h> 26 #include <l4/sys/irq.h> 27 #include <l4/sys/rcv_endpoint.h> 28 #include <l4/util/util.h> 29 30 #include <pthread.h> 31 #include <pthread-l4.h> 32 33 #include <stdio.h> 34 35 36 37 enum Global_regs 38 { 39 Dma_control = 0x1000, // DMAC 40 Dma_irq_pending = 0x1004, // DIRQP 41 }; 42 43 enum Channel_regs 44 { 45 Dma_source = 0x00, // DSA 46 Dma_destination = 0x04, // DTA 47 Dma_transfer_count = 0x08, // DTC 48 Dma_request_source = 0x0c, // DRT 49 Dma_control_status = 0x10, // DCS 50 Dma_command = 0x14, // DCM 51 Dma_descriptor_address = 0x18, // DDA 52 Dma_stride = 0x1c, // DSD 53 }; 54 55 enum Dma_control_bits : unsigned 56 { 57 Dma_fast_msc_transfer = 0x80000000, // FMSC 58 Dma_fast_ssi_transfer = 0x40000000, // FSSI 59 Dma_fast_tssi_transfer = 0x20000000, // FTSSI 60 Dma_fast_uart_transfer = 0x10000000, // FUART 61 Dma_fast_aic_transfer = 0x08000000, // FAIC 62 Dma_control_trans_halted = 0x00000008, // HLT 63 Dma_control_address_error = 0x00000004, // AR 64 Dma_control_enable = 0x00000001, // DMAE 65 }; 66 67 enum Dma_transfer_count_bits : unsigned 68 { 69 Dma_transfer_count_mask = 0x00ffffff, 70 }; 71 72 enum Dma_request_source_bits : unsigned 73 { 74 Dma_request_type_mask = 0x0000003f, 75 }; 76 77 enum Dma_control_status_bits : unsigned 78 { 79 Dma_no_descriptor_transfer = 0x80000000, 80 Dma_8word_descriptor = 0x40000000, 81 Dma_copy_offset_mask = 0x0000ff00, 82 Dma_address_error = 0x00000010, 83 Dma_trans_completed = 0x00000008, 84 Dma_trans_halted = 0x00000004, 85 Dma_channel_enable = 0x00000001, 86 87 Dma_copy_offset_shift = 8, 88 }; 89 90 enum Dma_command_bits : unsigned 91 { 92 Dma_source_address_increment = 0x800000, 93 Dma_source_address_no_increment = 0x000000, 94 Dma_destination_address_increment = 0x400000, 95 Dma_destination_address_no_increment = 0x000000, 96 97 Dma_source_address_increment_wrap = 0x200000, 98 Dma_destination_address_increment_wrap = 0x100000, 99 Dma_recommended_data_unit_size_mask = 0x0f0000, 100 Dma_source_port_width_mask = 0x00c000, 101 Dma_destination_port_width_mask = 0x003000, 102 Dma_transfer_unit_size_mask = 0x000f00, 103 104 Dma_trans_unit_size_32_bit = 0x000000, 105 Dma_trans_unit_size_8_bit = 0x000100, 106 Dma_trans_unit_size_16_bit = 0x000200, 107 Dma_trans_unit_size_16_byte = 0x000300, 108 Dma_trans_unit_size_32_byte = 0x000400, 109 Dma_trans_unit_size_64_byte = 0x000500, 110 Dma_trans_unit_size_128_byte = 0x000600, 111 Dma_trans_unit_size_autonomous = 0x000700, 112 Dma_trans_unit_size_external = 0x000800, 113 114 Dma_source_address_compare_index = 0x000080, 115 Dma_destination_address_compare_index = 0x000040, 116 Dma_stride_enable = 0x000004, 117 Dma_transfer_irq_enable = 0x000002, 118 Dma_descriptor_link_enable = 0x000001, 119 120 Dma_recommended_data_unit_size_shift = 16, 121 Dma_source_port_width_shift = 14, 122 Dma_destination_port_width_shift = 12, 123 Dma_transfer_unit_size_shift = 8, 124 }; 125 126 enum Dma_port_width_values : unsigned 127 { 128 Dma_port_width_32_bit = 0, 129 Dma_port_width_8_bit = 1, 130 Dma_port_width_16_bit = 2, 131 }; 132 133 134 135 // Initialise a channel. 136 137 Dma_x1600_channel::Dma_x1600_channel(Dma_x1600_chip *chip, uint8_t channel, 138 l4_addr_t start, l4_cap_idx_t irq) 139 : _chip(chip), _channel(channel), _irq(irq) 140 { 141 _regs = new Hw::Mmio_register_block<32>(start); 142 143 // Initialise the transfer count. 144 145 _regs[Dma_transfer_count] = 0; 146 } 147 148 // Return the closest interval length greater than or equal to the number of 149 // units given encoded in the request detection interval length field of the 150 // control/status register. 151 152 uint32_t 153 Dma_x1600_channel::encode_req_detect_int_length(uint8_t units) 154 { 155 static uint8_t lengths[] = {0, 1, 2, 3, 4, 8, 16, 32, 64, 128}; 156 int i; 157 158 if (!units) 159 return 0; 160 161 for (i = 0; i <= 9; i++) 162 { 163 if (lengths[i] >= units) 164 break; 165 } 166 167 return i << Dma_recommended_data_unit_size_shift; 168 } 169 170 // Encode the appropriate source port width for the given request type. 171 172 uint32_t 173 Dma_x1600_channel::encode_source_port_width(uint8_t width) 174 { 175 switch (width) 176 { 177 case 1: 178 return Dma_port_width_8_bit << Dma_source_port_width_shift; 179 180 case 2: 181 return Dma_port_width_16_bit << Dma_source_port_width_shift; 182 183 default: 184 return Dma_port_width_32_bit << Dma_source_port_width_shift; 185 } 186 } 187 188 // Encode the appropriate destination port width for the given request type. 189 190 uint32_t 191 Dma_x1600_channel::encode_destination_port_width(uint8_t width) 192 { 193 switch (width) 194 { 195 case 1: 196 return Dma_port_width_8_bit << Dma_destination_port_width_shift; 197 198 case 2: 199 return Dma_port_width_16_bit << Dma_destination_port_width_shift; 200 201 default: 202 return Dma_port_width_32_bit << Dma_destination_port_width_shift; 203 } 204 } 205 206 // Encode the transfer unit size. 207 // NOTE: This does not handle the external case. 208 209 uint32_t 210 Dma_x1600_channel::encode_transfer_unit_size(uint8_t size) 211 { 212 switch (size) 213 { 214 case 0: 215 return Dma_trans_unit_size_autonomous; 216 217 case 1: 218 return Dma_trans_unit_size_8_bit; 219 220 case 2: 221 return Dma_trans_unit_size_16_bit; 222 223 case 16: 224 return Dma_trans_unit_size_16_byte; 225 226 case 32: 227 return Dma_trans_unit_size_32_byte; 228 229 case 64: 230 return Dma_trans_unit_size_64_byte; 231 232 case 128: 233 return Dma_trans_unit_size_128_byte; 234 235 default: 236 return Dma_trans_unit_size_32_bit; 237 } 238 } 239 240 // Transfer data between memory locations, returning the number of units that 241 // should have been transferred. 242 243 unsigned int 244 Dma_x1600_channel::transfer(uint32_t source, uint32_t destination, 245 unsigned int count, 246 bool source_increment, bool destination_increment, 247 uint8_t source_width, uint8_t destination_width, 248 uint8_t transfer_unit_size, 249 enum Dma_x1600_request_type type) 250 { 251 printf("transfer:%s%s%s%s\n", error() ? " error" : "", 252 halted() ? " halted" : "", 253 completed() ? " completed" : "", 254 _regs[Dma_transfer_count] ? " count" : ""); 255 256 // Ensure an absence of address error and halt conditions globally and in this channel. 257 258 if (error() || halted()) 259 return 0; 260 261 // Ensure a zero transfer count for this channel. 262 263 if (_regs[Dma_transfer_count]) 264 return 0; 265 266 // Disable the channel. 267 268 _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_channel_enable; 269 270 // Set addresses. 271 272 _regs[Dma_source] = source; 273 _regs[Dma_destination] = destination; 274 275 // Set transfer count to the number of units. 276 277 unsigned int units = count < Dma_transfer_count_mask ? count : Dma_transfer_count_mask; 278 279 _regs[Dma_transfer_count] = units; 280 281 // Set auto-request for memory-to-memory transfers. Otherwise, set the 282 // indicated request type. 283 284 _regs[Dma_request_source] = type; 285 286 // For a descriptor, the actual fields would be populated instead of the 287 // command register, descriptor transfer would be indicated in the control/ 288 // status register along with the appropriate descriptor size indicator. 289 290 /* NOTE: To be considered... 291 * request detection interval length (for autonomous mode) 292 */ 293 294 _regs[Dma_command] = (source_increment ? Dma_source_address_increment : Dma_source_address_no_increment) | 295 (destination_increment ? Dma_destination_address_increment : Dma_destination_address_no_increment) | 296 encode_source_port_width(source_width) | 297 encode_destination_port_width(destination_width) | 298 encode_transfer_unit_size(transfer_unit_size) | 299 Dma_transfer_irq_enable; 300 301 // For a descriptor, the descriptor address would be set and the doorbell 302 // register field for the channel set. 303 304 // Enable the channel (and peripheral). 305 306 _regs[Dma_control_status] = Dma_no_descriptor_transfer | 307 Dma_channel_enable; 308 309 // Return the number of units to transfer. 310 311 return units; 312 } 313 314 // Wait for a transfer to end, returning the number of units remaining to be 315 // transferred. 316 317 unsigned int 318 Dma_x1600_channel::wait() 319 { 320 // An interrupt will occur upon completion, the completion flag will be set 321 // and the transfer count will be zero. 322 323 unsigned int remaining = 0; 324 325 do 326 { 327 if (!wait_for_irq(1000000)) 328 printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); 329 else 330 { 331 printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); 332 remaining = _regs[Dma_transfer_count]; 333 ack_irq(); 334 break; 335 } 336 } 337 while (!error() && !halted() && !completed()); 338 339 // Reset the channel status. 340 341 _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_channel_enable | 342 Dma_trans_completed | Dma_address_error | 343 Dma_trans_halted); 344 _regs[Dma_transfer_count] = 0; 345 346 return remaining; 347 } 348 349 // Wait indefinitely for an interrupt request, returning true if one was delivered. 350 351 bool 352 Dma_x1600_channel::wait_for_irq() 353 { 354 if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) 355 return false; 356 357 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && _chip->have_interrupt(_channel); 358 } 359 360 // Wait up to the given timeout (in microseconds) for an interrupt request, 361 // returning true if one was delivered. 362 363 bool 364 Dma_x1600_channel::wait_for_irq(unsigned int timeout) 365 { 366 if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) 367 return false; 368 369 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))) && _chip->have_interrupt(_channel); 370 } 371 372 // Acknowledge an interrupt condition. 373 374 void 375 Dma_x1600_channel::ack_irq() 376 { 377 _chip->ack_irq(_channel); 378 } 379 380 // Return whether a transfer has completed. 381 382 bool 383 Dma_x1600_channel::completed() 384 { 385 return _regs[Dma_control_status] & Dma_trans_completed ? true : false; 386 } 387 388 // Return whether an address error condition has arisen. 389 390 bool 391 Dma_x1600_channel::error() 392 { 393 return _chip->error() || (_regs[Dma_control_status] & Dma_address_error ? true : false); 394 } 395 396 // Return whether a transfer has halted. 397 398 bool 399 Dma_x1600_channel::halted() 400 { 401 return _chip->halted() || (_regs[Dma_control_status] & Dma_trans_halted ? true : false); 402 } 403 404 405 406 // Initialise the I2C controller. 407 408 Dma_x1600_chip::Dma_x1600_chip(l4_addr_t start, l4_addr_t end, 409 Cpm_x1600_chip *cpm) 410 : _start(start), _end(end), _cpm(cpm) 411 { 412 _regs = new Hw::Mmio_register_block<32>(start); 413 } 414 415 // Enable the peripheral. 416 417 void 418 Dma_x1600_chip::enable() 419 { 420 // Make sure that the DMA clock is available. 421 422 _cpm->start_clock(Clock_dma); 423 424 _regs[Dma_control] = Dma_control_enable; 425 while (!(_regs[Dma_control] & Dma_control_enable)); 426 } 427 428 // Disable the channel. 429 430 void 431 Dma_x1600_chip::disable() 432 { 433 _regs[Dma_control] = 0; 434 while (_regs[Dma_control] & Dma_control_enable); 435 } 436 437 // Obtain a channel object. 438 439 Dma_x1600_channel * 440 Dma_x1600_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) 441 { 442 if (channel < 32) 443 return new Dma_x1600_channel(this, channel, _start + 0x20 * channel, irq); 444 else 445 throw -L4_EINVAL; 446 } 447 448 // Return whether an interrupt is pending on the given channel. 449 450 bool 451 Dma_x1600_chip::have_interrupt(uint8_t channel) 452 { 453 return _regs[Dma_irq_pending] & (1UL << channel) ? true : false; 454 } 455 456 // Acknowledge an interrupt condition on the given channel. 457 458 void 459 Dma_x1600_chip::ack_irq(uint8_t channel) 460 { 461 _regs[Dma_irq_pending] = _regs[Dma_irq_pending] & ~(1UL << channel); 462 } 463 464 // Return whether an address error condition has arisen. 465 466 bool 467 Dma_x1600_chip::error() 468 { 469 return _regs[Dma_control] & Dma_control_address_error ? true : false; 470 } 471 472 // Return whether a transfer has halted. 473 474 bool 475 Dma_x1600_chip::halted() 476 { 477 return _regs[Dma_control] & Dma_control_trans_halted ? true : false; 478 } 479 480 481 482 // C language interface functions. 483 484 void *x1600_dma_init(l4_addr_t start, l4_addr_t end, void *cpm) 485 { 486 return (void *) new Dma_x1600_chip(start, end, static_cast<Cpm_x1600_chip *>(cpm)); 487 } 488 489 void x1600_dma_disable(void *dma_chip) 490 { 491 static_cast<Dma_x1600_chip *>(dma_chip)->disable(); 492 } 493 494 void x1600_dma_enable(void *dma_chip) 495 { 496 static_cast<Dma_x1600_chip *>(dma_chip)->enable(); 497 } 498 499 void *x1600_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq) 500 { 501 return static_cast<Dma_x1600_chip *>(dma)->get_channel(channel, irq); 502 } 503 504 unsigned int x1600_dma_transfer(void *dma_channel, 505 uint32_t source, uint32_t destination, 506 unsigned int count, 507 int source_increment, int destination_increment, 508 uint8_t source_width, uint8_t destination_width, 509 uint8_t transfer_unit_size, 510 enum Dma_x1600_request_type type) 511 { 512 return static_cast<Dma_x1600_channel *>(dma_channel)->transfer(source, 513 destination, count, source_increment, destination_increment, source_width, 514 destination_width, transfer_unit_size, type); 515 } 516 517 unsigned int x1600_dma_wait(void *dma_channel) 518 { 519 return static_cast<Dma_x1600_channel *>(dma_channel)->wait(); 520 }