1 /* 2 * MSC (MMC/SD controller) peripheral support. 3 * 4 * Copyright (C) 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/hw_mmio_register_block.h> 23 #include <l4/sys/irq.h> 24 #include <l4/sys/rcv_endpoint.h> 25 #include <l4/util/util.h> 26 27 #include <pthread.h> 28 #include <pthread-l4.h> 29 30 #include <math.h> 31 #include <stdio.h> 32 33 #include "msc-common.h" 34 #include "msc-defs.h" 35 36 37 38 // Command frame: 39 // byte: start (1), direction (1), command (6) 40 // 4 bytes: argument 41 // byte: CRC (7), end (1) 42 43 // IO_RW_DIRECT argument: 44 // Argument MSB to LSB: R/W (1), function number (3), read after write flag (1), 45 // stuff (1), register address (17), stuff (1), 46 // write data or stuff (8) 47 // 0x88000c08: W, function = 0, read after write, register address = 6 (CCCR), 48 // data = 8 (reset) 49 50 const uint32_t Io_rw_direct_reset = 0x88000c08; 51 52 // (IO_)SEND_OP_COND argument and default voltage range expected in R3, R4: 53 // Argument MSB to LSB: stuff (8), voltage range (16), reserved (8) 54 // 0x00ff8000: voltage range 2.7 - 3.6V 55 56 const uint32_t Ocr_default_voltage_range = 0x00ff8000; 57 58 // SEND_IF_COND argument and default voltage range expected in R7: 59 // Argument MSB to LSB: stuff (20), voltage supplied (4), check (8) 60 // 0x000001aa: voltage range 2.7 - 3.6V, check = 0b10101010 61 62 const uint32_t If_cond_default_voltage_range = 0x000001aa; 63 64 65 66 // Utilities. 67 68 static enum Command_data_control_bits 69 encode_bus_width(uint8_t width) 70 { 71 switch (width) 72 { 73 case 4: return Cdc_bus_width_4bit; 74 case 1: return Cdc_bus_width_1bit; 75 default: return Cdc_bus_width_1bit; 76 } 77 } 78 79 80 81 // Channel abstraction. 82 83 Msc_channel::Msc_channel(l4_addr_t msc_start, l4_addr_t addr, l4_cap_idx_t irq, 84 Cpm_chip *cpm, enum Clock_identifiers clock) 85 : _msc_start(msc_start), _irq(irq), _cpm(cpm), _clock(clock) 86 { 87 _regs = new Hw::Mmio_register_block<32>(addr); 88 } 89 90 Msc_channel::~Msc_channel() 91 { 92 } 93 94 // Utility methods. 95 // NOTE: Also defined in the CPM abstraction, should be consolidated. 96 97 uint32_t 98 Msc_channel::get_field(uint32_t reg, uint32_t mask, uint8_t shift) 99 { 100 return (_regs[reg] & (mask << shift)) >> shift; 101 } 102 103 void 104 Msc_channel::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) 105 { 106 _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); 107 } 108 109 bool 110 Msc_channel::set_clock_frequency(uint64_t frequency) 111 { 112 uint64_t division = _cpm->get_frequency(_clock) / frequency; 113 double divider = ceil(log2(division)); 114 115 if ((divider < 0) || (divider > Clock_rate_field_mask)) 116 return false; 117 118 set_field(Msc_clock_rate, Clock_rate_field_mask, Clock_rate_field_shift, 119 (uint32_t) divider); 120 121 return true; 122 } 123 124 void 125 Msc_channel::reset() 126 { 127 _regs[Msc_control] = _regs[Msc_control] | Control_reset; 128 129 while (_regs[Msc_status] & Status_resetting); 130 } 131 132 void 133 Msc_channel::start_clock() 134 { 135 set_field(Msc_control, Control_clock_control_field_mask, 136 Control_clock_control_field_shift, Control_clock_control_start); 137 138 while (!(_regs[Msc_status] & Status_clock_enabled)); 139 } 140 141 void 142 Msc_channel::stop_clock() 143 { 144 set_field(Msc_control, Control_clock_control_field_mask, 145 Control_clock_control_field_shift, Control_clock_control_stop); 146 147 while (_regs[Msc_status] & Status_clock_enabled); 148 } 149 150 void 151 Msc_channel::ack_irq(uint32_t flags) 152 { 153 // Clear the flags by setting them. 154 155 _regs[Msc_interrupt_flag] = _regs[Msc_interrupt_flag] | flags; 156 } 157 158 void 159 Msc_channel::unmask_irq(uint32_t flags) 160 { 161 ack_irq(flags); 162 163 if (_regs[Msc_interrupt_mask] & flags) 164 _regs[Msc_interrupt_mask] = _regs[Msc_interrupt_mask] & ~flags; 165 } 166 167 bool 168 Msc_channel::have_dma_enable_in_command() 169 { 170 return false; 171 } 172 173 bool 174 Msc_channel::have_dma_selection() 175 { 176 return true; 177 } 178 179 bool 180 Msc_channel::command_will_write(uint8_t index) 181 { 182 // NOTE: Probably incomplete coverage. 183 184 switch (index) 185 { 186 case Command_write_dat_until_stop: return true; 187 case Command_write_block: return true; 188 case Command_write_multiple_block: return true; 189 case Command_program_cid: return true; 190 case Command_program_csd: return true; 191 case Command_lock_unlock: return true; 192 default: return false; 193 } 194 } 195 196 bool 197 Msc_channel::app_command_will_write(uint8_t index) 198 { 199 // NOTE: Probably incomplete coverage. 200 201 (void) index; 202 203 return false; 204 } 205 206 bool 207 Msc_channel::command_with_data(uint8_t index) 208 { 209 // NOTE: Probably incomplete coverage. 210 211 switch (index) 212 { 213 case Command_read_dat_until_stop: return true; 214 case Command_read_single_block: return true; 215 case Command_read_multiple_block: return true; 216 case Command_write_dat_until_stop: return true; 217 case Command_write_block: return true; 218 case Command_write_multiple_block: return true; 219 case Command_program_cid: return true; 220 case Command_program_csd: return true; 221 case Command_lock_unlock: return true; 222 default: return false; 223 } 224 } 225 226 bool 227 Msc_channel::app_command_with_data(uint8_t index) 228 { 229 // NOTE: Probably incomplete coverage. 230 231 switch (index) 232 { 233 case App_command_sd_status: return true; 234 case App_command_send_num_wr_blocks: return true; 235 case App_command_send_scr: return true; 236 default: return false; 237 } 238 } 239 240 bool 241 Msc_channel::command_uses_busy(uint8_t index) 242 { 243 // NOTE: Probably incomplete coverage. 244 245 switch (index) 246 { 247 case Command_select_deselect_card: return true; 248 case Command_stop_transmission: return true; 249 default: return false; 250 } 251 } 252 253 bool 254 Msc_channel::app_command_uses_busy(uint8_t index) 255 { 256 // NOTE: Probably incomplete coverage. 257 258 (void) index; 259 260 return false; 261 } 262 263 uint8_t 264 Msc_channel::get_response_format(uint8_t index) 265 { 266 // NOTE: Probably incomplete coverage. 267 268 switch (index) 269 { 270 // Common commands without response. 271 272 case Command_go_idle_state: return 0; 273 case Command_set_dsr: return 0; 274 case Command_go_inactive_state: return 0; 275 276 // Common commands with response. 277 278 case Command_send_op_cond: return 3; 279 case Command_all_send_cid: return 2; 280 case Command_send_csd: return 2; 281 case Command_send_cid: return 2; 282 283 // SDIO only. 284 285 case Command_io_send_op_cond: return 4; 286 case Command_io_rw_direct: return 5; 287 288 // SDMEM only. 289 290 case Command_send_relative_addr: return 6; 291 case Command_send_if_cond: return 7; 292 293 // All other commands. 294 295 default: return 1; 296 } 297 } 298 299 uint8_t 300 Msc_channel::get_app_response_format(uint8_t index) 301 { 302 // NOTE: Probably incomplete coverage. 303 304 switch (index) 305 { 306 // SDMEM only. 307 308 case App_command_sd_send_op_cond: return 3; 309 310 // All other commands. 311 312 default: return 1; 313 } 314 } 315 316 // Read a response directly from the FIFO. 317 318 void 319 Msc_channel::read_response(uint16_t *buffer, uint8_t units) 320 { 321 uint8_t unit = units; 322 323 while (unit > 0) 324 { 325 uint32_t data = _regs[Msc_response_fifo]; 326 327 // Ignore the upper byte of the last unit in small transfers since it is the 328 // lower byte from the previous unit not shifted out of the register. 329 330 unit--; 331 332 if ((unit == 0) && (units == 3)) 333 buffer[unit] = (data & 0xff) << 8; 334 else 335 buffer[unit] = data; 336 } 337 } 338 339 // Send an application-specific command. 340 341 bool 342 Msc_channel::send_app_command(uint8_t index, uint32_t arg) 343 { 344 if (!send_command(Command_app_cmd, _cards[_card].rca << 16)) 345 return false; 346 347 return send_command(index, arg, get_app_response_format(index), 348 app_command_with_data(index), 349 app_command_will_write(index), 350 app_command_uses_busy(index)); 351 } 352 353 // Send a common MMC/SD command. 354 355 bool 356 Msc_channel::send_command(uint8_t index, uint32_t arg) 357 { 358 return send_command(index, arg, get_response_format(index), 359 command_with_data(index), 360 command_will_write(index), 361 command_uses_busy(index)); 362 } 363 364 // Initiate a command having the given index and using the given argument, 365 // employing the specified response format and involving a data transfer if 366 // indicated. 367 368 bool 369 Msc_channel::send_command(uint8_t index, uint32_t arg, uint8_t response_format, 370 bool data, bool write, bool busy) 371 { 372 stop_clock(); 373 374 // Enable DMA for data transfers for JZ4780, X1600 and others that have a 375 // channel-level control selecting special or conventional DMA. 376 377 if (have_dma_selection()) 378 _regs[Msc_dma_control] = (data ? Dma_select_common_dma | Dma_enable : Dma_disable); 379 380 // Set the command index and argument. 381 382 _regs[Msc_command_index] = index; 383 _regs[Msc_command_argument] = arg; 384 385 // Configure the response format and data bus width. 386 387 set_field(Msc_command_data_control, Cdc_response_format_field_mask, 388 Cdc_response_format_field_shift, response_format); 389 390 // NOTE: May need to set the SD bus width. 391 392 set_field(Msc_command_data_control, Cdc_bus_width_field_mask, 393 Cdc_bus_width_field_shift, 394 encode_bus_width(_cards[_card].bus_width)); 395 396 set_field(Msc_command_data_control, Cdc_recv_fifo_level_field_mask, 397 Cdc_recv_fifo_level_field_shift, Cdc_fifo_level_16); 398 399 set_field(Msc_command_data_control, Cdc_trans_fifo_level_field_mask, 400 Cdc_trans_fifo_level_field_shift, Cdc_fifo_level_16); 401 402 // Set and clear control bits appropriate to the command. 403 404 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] | 405 (busy ? Cdc_expect_busy : Cdc_do_not_expect_busy) | 406 (data ? Cdc_data_with_command : Cdc_no_data_with_command) | 407 (write ? Cdc_write_operation : Cdc_read_operation); 408 409 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] & 410 ~((busy ? Cdc_do_not_expect_busy : Cdc_expect_busy) | 411 (data ? Cdc_no_data_with_command : Cdc_data_with_command) | 412 (write ? Cdc_read_operation : Cdc_write_operation) | 413 Cdc_stream_block | Cdc_init_sequence); 414 415 // Pre-JZ4780 SoCs enable DMA in the command/data register. 416 417 if (have_dma_enable_in_command()) 418 set_field(Msc_command_data_control, Cdc_dma_field_mask, Cdc_dma_field_shift, 419 data ? Cdc_dma_enable : Cdc_dma_disable); 420 421 // Unmask interrupts, start the clock, then initiate the command. 422 423 uint32_t flags = Int_end_command_response | Int_response_timeout; 424 425 unmask_irq(flags); 426 start_clock(); 427 428 _regs[Msc_control] = _regs[Msc_control] | Control_start_operation; 429 430 // Wait for command completion. 431 432 if (!wait_for_irq(flags)) 433 return false; 434 435 // Determine whether a timeout occurred. 436 437 bool have_response = !((_regs[Msc_interrupt_flag] & Int_response_timeout) || 438 (_regs[Msc_status] & Status_response_crc_error) || 439 (_regs[Msc_status] & Status_timeout_response)); 440 441 // Acknowledge the response interrupts and return the status. 442 443 ack_irq(flags); 444 return have_response; 445 } 446 447 // Wait indefinitely for an interrupt request, returning true if one was delivered. 448 449 bool 450 Msc_channel::wait_for_irq(uint32_t flags) 451 { 452 if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) 453 return false; 454 455 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && 456 (_regs[Msc_interrupt_flag] & flags); 457 } 458 459 // Wait up to the given timeout (in microseconds) for an interrupt request, 460 // returning true if one was delivered. 461 462 bool 463 Msc_channel::wait_for_irq(uint32_t flags, unsigned int timeout) 464 { 465 if (l4_error(l4_rcv_ep_bind_thread(_irq, pthread_l4_cap(pthread_self()), 0))) 466 return false; 467 468 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, 469 l4util_micros2l4to(timeout)))) && 470 (_regs[Msc_interrupt_flag] & flags); 471 } 472 473 474 475 // Check the voltage range of the SD card, potentially establishing that it is 476 // a high capacity card. Return false if the voltage range is incompatible. 477 478 bool 479 Msc_channel::check_sd() 480 { 481 struct R7 r7; 482 483 // Send an interface condition command. 484 // A card may not respond to this command. 485 486 if (!send_command(Command_send_if_cond, If_cond_default_voltage_range)) 487 return true; 488 489 read_response((uint16_t *) &r7, Response_size_R7); 490 491 // Reject any card not supporting the default voltage range. 492 493 if (r7.check_voltage.raw != If_cond_default_voltage_range) 494 return false; 495 496 return true; 497 } 498 499 // Check the voltage range of the SDIO card, inactivating it if incompatible. 500 501 void 502 Msc_channel::init_sdio() 503 { 504 struct R4 r4; 505 uint32_t ocr = 0; 506 507 // Reset any SDIO card or IO unit in a combined memory/IO card. 508 // A non-SDIO card may not respond to this command. 509 510 if (!send_command(Command_io_rw_direct, Io_rw_direct_reset)) 511 return; 512 513 // Attempt to assert the operating conditions. 514 515 do 516 { 517 // Obtain OCR (operating conditions register) values for any IO card. 518 // Without a response, the card may have inactivated itself due to voltage 519 // range incompatibility reasons. 520 521 if (!send_command(Command_io_send_op_cond, ocr)) 522 return; 523 524 read_response((uint16_t *) &r4, Response_size_R4); 525 526 // Finish if no IO functions provided. 527 // NOTE: Should only need to check this the first time. 528 529 if (r4.number_io_functions == 0) 530 return; 531 532 if (r4.ocr != Ocr_default_voltage_range) 533 { 534 ocr = Ocr_default_voltage_range; 535 continue; 536 } 537 } 538 while (!r4.ready); 539 } 540 541 void 542 Msc_channel::init_sdmem() 543 { 544 struct R3 r3; 545 546 // Incorporate the HCS bit into the OCR for SDMEM. 547 548 uint32_t ocr = Ocr_high_capacity_storage; 549 550 do 551 { 552 if (!send_app_command(App_command_sd_send_op_cond, ocr)) 553 return; 554 555 read_response((uint16_t *) &r3, Response_size_R3); 556 557 if (r3.ocr != Ocr_default_voltage_range) 558 { 559 ocr = Ocr_default_voltage_range | Ocr_high_capacity_storage; 560 continue; 561 } 562 } 563 while (!(r3.ocr & Ocr_card_powered_up)); 564 } 565 566 void 567 Msc_channel::init_mmc() 568 { 569 // Obtain OCR (operating conditions register) values for each card using 570 // send_op_cond command variants without argument, or assert operating 571 // conditions with argument to avoid handling card responses. Where responses 572 // are solicited, the host must determine a suitable argument and reissue the 573 // command. 574 575 struct R3 r3; 576 uint32_t ocr = 0; 577 578 do 579 { 580 if (!send_command(Command_send_op_cond, ocr)) 581 return; 582 583 read_response((uint16_t *) &r3, Response_size_R3); 584 585 if (r3.ocr != Ocr_default_voltage_range) 586 { 587 ocr = Ocr_default_voltage_range; 588 continue; 589 } 590 } 591 while (!(r3.ocr & Ocr_card_powered_up)); 592 } 593 594 void 595 Msc_channel::identify_cards() 596 { 597 struct R2 r2; 598 struct R6 r6; 599 600 _num_cards = 0; 601 602 while (send_command(Command_all_send_cid, 0)) 603 { 604 read_response((uint16_t *) &r2, Response_size_R2); 605 606 _cards[_num_cards].cid = r2.payload.cid; 607 608 printf("card: %d\n", _num_cards); 609 printf("date: %d %d\n", r2.payload.cid.month, r2.payload.cid.year); 610 printf("serial: %d\n", r2.payload.cid.serial); 611 printf("revision: %d\n", r2.payload.cid.revision); 612 printf("name: %c%c%c%c%c\n", r2.payload.cid.name[4], r2.payload.cid.name[3], 613 r2.payload.cid.name[2], r2.payload.cid.name[1], 614 r2.payload.cid.name[0]); 615 printf("oem: %d\n", r2.payload.cid.oem); 616 printf("manufacturer: %d\n", r2.payload.cid.manufacturer); 617 618 // Try and obtain a card-issued address. 619 620 if (send_command(Command_send_relative_addr, 0)) 621 { 622 read_response((uint16_t *) &r6, Response_size_R6); 623 _cards[_num_cards].rca = r6.rca; 624 } 625 626 // Try and assign an address. 627 // Employ 1-based relative addressing. 628 629 else if (send_command(Command_set_relative_addr, _num_cards + 1)) 630 _cards[_num_cards].rca = _num_cards + 1; 631 632 // Otherwise, stop identification. 633 634 else 635 return; 636 637 // Set the default bus width to be determined. 638 639 _cards[_num_cards].bus_width = 0; 640 641 _num_cards++; 642 } 643 } 644 645 void 646 Msc_channel::query_cards() 647 { 648 struct R2 r2; 649 struct R3 r3; 650 uint8_t card; 651 652 for (card = 0; card < _num_cards; card++) 653 { 654 // Employ 1-based relative addressing. 655 656 if (!send_command(Command_send_csd, _cards[card].rca << 16)) 657 return; 658 659 read_response((uint16_t *) &r2, Response_size_R2); 660 661 _cards[card].csd = r2.payload.csd; 662 663 struct CSD *csd = &_cards[card].csd; 664 665 printf("card: %d\n", card); 666 printf("csd: %d\n", csd->csd); 667 printf("copy: %s\n", csd->copy ? "copied" : "original"); 668 printf("card command classes: %03x\n", csd->card_command_classes); 669 printf("device (size multiplier): %d %d\n", csd->device_size + 1, 670 1 << (csd->device_size_multiplier + 2)); 671 printf("device size: %d\n", (1 << csd->read_blocklen) * 672 (csd->device_size + 1) * 673 (1 << (csd->device_size_multiplier + 2))); 674 printf("transfer speed: %d MHz\n", csd->tran_speed == 0x32 ? 25 : 50); 675 printf("format group: %d %d\n", csd->format, r2.payload.csd.format_group); 676 printf("write time factor: %d\n", 1 << csd->write_time_factor); 677 printf("write protect (temp perm): %s %s\n", csd->temp_write_prot ? "yes" : "no", 678 csd->perm_write_prot ? "yes" : "no"); 679 printf("write protect group (enable size): %s %d\n", csd->write_prot_group_enable ? "yes" : "no", 680 csd->write_prot_group_size + 1); 681 printf("write block (partial length): %s %d\n", csd->write_block_partial ? "yes" : "no", 682 1 << csd->write_blocklen); 683 printf("read block (partial length): %s %d\n", csd->read_block_partial ? "yes" : "no", 684 1 << csd->read_blocklen); 685 printf("erase: sector single: %d %s\n", csd->erase_sector_size + 1, 686 csd->erase_single_block_enable ? "yes" : "no"); 687 printf("misalign: read write: %s %s\n", csd->read_block_misalign ? "yes" : "no", 688 csd->write_block_misalign ? "yes" : "no"); 689 printf("max read current (min max): %d %d\n", csd->max_read_current_min, 690 csd->max_read_current_max); 691 printf("max write current (min max): %d %d\n", csd->max_write_current_min, 692 csd->max_write_current_max); 693 printf("read access time (1 2): %d %d\n", csd->data_read_access_time_1, 694 csd->data_read_access_time_2); 695 printf("DSR: %s\n", csd->dsr_implemented ? "yes" : "no"); 696 697 // Query the OCR again now that we can associate it with a specific card. 698 699 if (!send_app_command(App_command_read_ocr, 0)) 700 return; 701 702 read_response((uint16_t *) &r3, Response_size_R3); 703 704 _cards[card].ocr = r3.ocr; 705 } 706 } 707 708 709 710 // Enable the controller and identify cards. 711 712 void 713 Msc_channel::enable() 714 { 715 // NOTE: X1600 and other recent SoCs only. 716 717 _regs[Msc_low_power_mode] = _regs[Msc_low_power_mode] & ~Low_power_mode_enable; 718 719 stop_clock(); 720 reset(); 721 722 // Slow the clock for initialisation. 723 // NOTE: Should produce an error. 724 725 if (!set_clock_frequency(400000)) 726 return; 727 728 send_command(Command_go_idle_state, 0); 729 730 if (check_sd()) 731 { 732 init_sdio(); 733 init_sdmem(); 734 } 735 736 init_mmc(); 737 identify_cards(); 738 query_cards(); 739 740 // Initially, no card is selected. 741 742 _card = -1; 743 } 744 745 // Obtain the card details. 746 747 struct msc_card * 748 Msc_channel::get_cards() 749 { 750 return _cards; 751 } 752 753 // Return the number of active cards. 754 755 uint8_t 756 Msc_channel::num_cards() 757 { 758 return _num_cards; 759 } 760 761 // Receive data from the selected card. 762 763 uint32_t 764 Msc_channel::recv_data(struct dma_region *region, uint32_t count) 765 { 766 if (count > region->size) 767 return 0; 768 769 uint32_t flags = Int_data_transfer_done; 770 771 unmask_irq(flags); 772 773 uint32_t to_transfer = transfer(_msc_start + Msc_recv_data_fifo, region->paddr, true, count); 774 775 wait_for_irq(flags); 776 ack_irq(flags); 777 778 if (!to_transfer || 779 (_regs[Msc_status] & Status_read_crc_error) || 780 (_regs[Msc_status] & Status_timeout_read)) 781 return 0; 782 783 return to_transfer; 784 } 785 786 // Send data to the selected card. 787 788 uint32_t 789 Msc_channel::send_data(struct dma_region *region, uint32_t count) 790 { 791 if (count > region->size) 792 return 0; 793 794 uint32_t flags = Int_data_transfer_done; 795 796 unmask_irq(flags); 797 798 uint32_t to_transfer = transfer(region->paddr, _msc_start + Msc_trans_data_fifo, false, count); 799 800 wait_for_irq(flags); 801 ack_irq(flags); 802 803 if (!to_transfer || 804 (_regs[Msc_status] & Status_write_crc_error_data) || 805 (_regs[Msc_status] & Status_write_crc_error_no_status)) 806 return 0; 807 808 return to_transfer; 809 } 810 811 // Read data from the indicated card into a memory region. 812 813 uint32_t 814 Msc_channel::read(uint8_t card, struct dma_region *region, 815 uint32_t address, uint32_t count) 816 { 817 uint32_t block_size = 1 << _cards[card].csd.read_blocklen; 818 819 // Obtain the block address from the byte address and the number of blocks 820 // from the byte count. 821 822 // NOTE: Rejecting addresses and counts that are not multiples of the block 823 // NOTE: size. Should produce an error. 824 825 if ((address % block_size) || (count % block_size)) 826 return 0; 827 828 return read_blocks(card, region, address / block_size, count / block_size); 829 } 830 831 // Read blocks from the indicated card into a memory region. 832 833 uint32_t 834 Msc_channel::read_blocks(uint8_t card, struct dma_region *region, 835 uint32_t block_address, uint32_t block_count) 836 { 837 uint32_t block_size = 1 << _cards[card].csd.read_blocklen; 838 struct R1 r1; 839 840 // Select the requested card. 841 842 if (_card != card) 843 { 844 // Choose an appropriate clock frequency for the card. 845 // NOTE: Should produce an error. 846 847 if (!set_clock_frequency(_cards[card].csd.tran_speed == 0x32 ? 848 25000000 : 50000000)) 849 return 0; 850 851 if (!send_command(Command_select_deselect_card, _cards[card].rca << 16)) 852 return 0; 853 854 read_response((uint16_t *) &r1, Response_size_R1); 855 856 if (r1.status & R1_status_error_mask) 857 return 0; 858 859 _card = card; 860 } 861 862 // NOTE: SMEM cards should allow bus width setting with the SCR register 863 // NOTE: describing the permitted values. 864 // NOTE: SDIO cards have their bus width set in CCCR via CMD52. 865 866 if (!_cards[card].bus_width) 867 { 868 if (send_app_command(App_command_set_bus_width, Bus_width_4bit)) 869 _cards[card].bus_width = 4; 870 else 871 _cards[card].bus_width = 1; 872 } 873 874 if (!send_command(Command_set_blocklen, block_size)) 875 return 0; 876 877 read_response((uint16_t *) &r1, Response_size_R1); 878 879 if (r1.status & R1_status_error_mask) 880 return 0; 881 882 // NOTE: Consider issuing a predefined block count command to any multiple 883 // NOTE: block operation, at least for cards that support it. 884 885 // Apply block count and size properties to the issued command. 886 887 _regs[Msc_block_count] = block_count; 888 _regs[Msc_block_length] = block_size; 889 890 // Where CCS = 0, byte addressing is used. Otherwise, block addressing is used. 891 892 uint32_t address; 893 894 if (_cards[card].ocr & Ocr_high_capacity_storage) 895 address = block_address; 896 else 897 address = block_address * block_size; 898 899 if (!send_command(block_count == 1 ? Command_read_single_block 900 : Command_read_multiple_block, address)) 901 return 0; 902 903 read_response((uint16_t *) &r1, Response_size_R1); 904 905 if (r1.status & R1_status_error_mask) 906 return 0; 907 908 // NOTE: Use Msc_block_success_count instead. 909 910 uint32_t transferred = recv_data(region, block_size * block_count); 911 912 if (block_count > 1) 913 send_command(Command_stop_transmission, 0); 914 915 return transferred; 916 } 917 918 919 920 // Peripheral abstraction. 921 922 Msc_chip::Msc_chip(l4_addr_t msc_start, l4_addr_t start, l4_addr_t end, 923 Cpm_chip *cpm) 924 : _msc_start(msc_start), _start(start), _end(end), _cpm(cpm) 925 { 926 }