1 /* 2 * Common clock functionality. 3 * 4 * Copyright (C) 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #pragma once 23 24 #ifdef __cplusplus 25 26 #include <l4/devices/hw_register_block.h> 27 #include <l4/devices/cpm.h> 28 #include <l4/sys/types.h> 29 #include <stdint.h> 30 31 /* Forward declaration. */ 32 33 class Clock_base; 34 35 36 37 /* Register access type. */ 38 39 class Cpm_regs 40 { 41 Hw::Register_block<32> _regs; 42 43 protected: 44 Clock_base **_clocks; 45 46 public: 47 uint32_t exclk_freq; 48 49 explicit Cpm_regs(l4_addr_t addr, Clock_base *clocks[], 50 uint32_t exclk_freq); 51 52 // Utility methods. 53 54 uint32_t get_field(uint32_t reg, uint32_t mask, uint8_t shift); 55 void set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value); 56 57 Clock_base *get_clock(int num); 58 }; 59 60 61 62 // Register field abstraction. 63 64 class Field 65 { 66 uint32_t reg; 67 uint32_t mask; 68 uint8_t bit; 69 bool defined; 70 71 public: 72 explicit Field() 73 : defined(false) 74 { 75 } 76 77 explicit Field(uint32_t reg, uint32_t mask, uint32_t bit) 78 : reg(reg), mask(mask), bit(bit), defined(true) 79 { 80 } 81 82 uint32_t get_field(Cpm_regs ®s); 83 void set_field(Cpm_regs ®s, uint32_t value); 84 bool is_defined() { return defined; } 85 86 // Undefined field object. 87 88 static Field undefined; 89 }; 90 91 92 93 // Clock sources. 94 95 class Mux 96 { 97 int _num_inputs; 98 enum Clock_identifiers *_inputs, _input; 99 100 public: 101 explicit Mux(int num_inputs, enum Clock_identifiers inputs[]) 102 : _num_inputs(num_inputs), _inputs(inputs) 103 { 104 } 105 106 explicit Mux(enum Clock_identifiers input) 107 : _num_inputs(1), _inputs(&_input) 108 { 109 _input = input; 110 } 111 112 explicit Mux() 113 : _num_inputs(0), _inputs(NULL) 114 { 115 } 116 117 int get_number() { return _num_inputs; } 118 enum Clock_identifiers get_input(int num); 119 }; 120 121 122 123 // Controllable clock source. 124 125 class Source 126 { 127 Mux _inputs; 128 Field _source; 129 130 public: 131 explicit Source(Mux inputs, Field source) 132 : _inputs(inputs), _source(source) 133 { 134 } 135 136 explicit Source(Mux inputs) 137 : _inputs(inputs) 138 { 139 } 140 141 explicit Source() 142 { 143 } 144 145 int get_number() { return _inputs.get_number(); } 146 enum Clock_identifiers get_input(int num) { return _inputs.get_input(num); } 147 148 // Clock source. 149 150 uint8_t get_source(Cpm_regs ®s); 151 void set_source(Cpm_regs ®s, uint8_t source); 152 153 // Clock source frequency. 154 155 uint32_t get_frequency(Cpm_regs ®s); 156 157 // Undefined source object. 158 159 static Source undefined; 160 }; 161 162 163 164 // Common clock control. 165 166 class Control_base 167 { 168 public: 169 virtual ~Control_base(); 170 171 virtual void change_disable(Cpm_regs ®s); 172 virtual void change_enable(Cpm_regs ®s); 173 174 virtual void wait_busy(Cpm_regs ®s) = 0; 175 virtual int have_clock(Cpm_regs ®s) = 0; 176 virtual void start_clock(Cpm_regs ®s) = 0; 177 virtual void stop_clock(Cpm_regs ®s) = 0; 178 }; 179 180 181 182 // Clock control. 183 184 class Control : public Control_base 185 { 186 Field _gate, _change_enable, _busy; 187 188 public: 189 explicit Control(Field gate, 190 Field change_enable = Field::undefined, 191 Field busy = Field::undefined) 192 : _gate(gate), _change_enable(change_enable), _busy(busy) 193 { 194 } 195 196 explicit Control() 197 : _gate(Field::undefined), _change_enable(Field::undefined), 198 _busy(Field::undefined) 199 { 200 } 201 202 // Clock control. 203 204 void change_disable(Cpm_regs ®s); 205 void change_enable(Cpm_regs ®s); 206 207 void wait_busy(Cpm_regs ®s); 208 int have_clock(Cpm_regs ®s); 209 void start_clock(Cpm_regs ®s); 210 void stop_clock(Cpm_regs ®s); 211 212 // Undefined control. 213 214 static Control undefined; 215 }; 216 217 218 219 // PLL control. 220 221 class Control_pll : public Control_base 222 { 223 Field _enable, _stable, _bypass; 224 225 // PLL_specific control. 226 227 int have_pll(Cpm_regs ®s); 228 int pll_enabled(Cpm_regs ®s); 229 230 public: 231 explicit Control_pll(Field enable, Field stable, Field bypass) 232 : _enable(enable), _stable(stable), _bypass(bypass) 233 { 234 } 235 236 // Clock control. 237 238 int pll_bypassed(Cpm_regs ®s); 239 240 void wait_busy(Cpm_regs ®s); 241 int have_clock(Cpm_regs ®s); 242 void start_clock(Cpm_regs ®s); 243 void stop_clock(Cpm_regs ®s); 244 }; 245 246 247 248 // Frequency transformation. 249 250 class Divider_base 251 { 252 public: 253 virtual ~Divider_base(); 254 255 // Output frequency. 256 257 virtual uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency) = 0; 258 }; 259 260 261 262 // Simple divider for regular clocks. 263 264 class Divider : public Divider_base 265 { 266 Field _divider; 267 268 public: 269 explicit Divider(Field divider) 270 : _divider(divider) 271 { 272 } 273 274 explicit Divider() 275 : _divider(Field::undefined) 276 { 277 } 278 279 // Clock divider. 280 281 uint32_t get_divider(Cpm_regs ®s); 282 void set_divider(Cpm_regs ®s, uint32_t divider); 283 284 // Output frequency. 285 286 uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); 287 288 // Undefined divider. 289 290 static Divider undefined; 291 }; 292 293 294 295 // Divider for PLLs. 296 297 class Divider_pll : public Divider_base 298 { 299 Field _multiplier, _input_divider, _output_divider0, _output_divider1; 300 301 public: 302 explicit Divider_pll(Field multiplier, Field input_divider, 303 Field output_divider0, Field output_divider1) 304 : _multiplier(multiplier), _input_divider(input_divider), 305 _output_divider0(output_divider0), _output_divider1(output_divider1) 306 { 307 } 308 309 // General frequency modifiers. 310 311 uint32_t get_multiplier(Cpm_regs ®s); 312 void set_multiplier(Cpm_regs ®s, uint32_t multiplier); 313 uint32_t get_input_divider(Cpm_regs ®s); 314 void set_input_divider(Cpm_regs ®s, uint32_t divider); 315 uint32_t get_output_divider(Cpm_regs ®s); 316 void set_output_divider(Cpm_regs ®s, uint32_t divider); 317 318 // Output frequency. 319 320 uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); 321 322 // Other operations. 323 324 void set_parameters(Cpm_regs ®s, uint32_t multiplier, 325 uint32_t in_divider, uint32_t out_divider); 326 }; 327 328 329 330 // Divider for I2S clocks. 331 332 class Divider_i2s : public Divider_base 333 { 334 Field _multiplier, _divider_N, _divider_D; 335 336 public: 337 explicit Divider_i2s(Field multiplier, Field divider_N, 338 Field divider_D) 339 : _multiplier(multiplier), _divider_N(divider_N), 340 _divider_D(divider_D) 341 { 342 } 343 344 // General frequency modifiers. 345 346 uint32_t get_multiplier(Cpm_regs ®s); 347 uint32_t get_divider_N(Cpm_regs ®s); 348 uint32_t get_divider_D(Cpm_regs ®s); 349 350 // Output frequency. 351 352 uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); 353 354 // Other operations. 355 356 void set_parameters(Cpm_regs ®s, uint32_t multiplier, 357 uint32_t divider_N, uint32_t divider_D); 358 }; 359 360 361 362 // Common clock abstraction. 363 364 class Clock_base 365 { 366 public: 367 virtual ~Clock_base(); 368 369 // Clock control. 370 371 virtual int have_clock(Cpm_regs ®s) = 0; 372 virtual void start_clock(Cpm_regs ®s) = 0; 373 virtual void stop_clock(Cpm_regs ®s) = 0; 374 375 // Output frequency. 376 377 virtual uint32_t get_frequency(Cpm_regs ®s) = 0; 378 }; 379 380 381 382 // Null (absent or undefined) clock abstraction. 383 384 class Clock_null : public Clock_base 385 { 386 public: 387 388 // Clock control. 389 390 int have_clock(Cpm_regs ®s); 391 void start_clock(Cpm_regs ®s); 392 void stop_clock(Cpm_regs ®s); 393 394 // Output frequency. 395 396 uint32_t get_frequency(Cpm_regs ®s); 397 }; 398 399 400 401 // Passive (root or input) clock without any source of its own. 402 403 class Clock_passive : public Clock_base 404 { 405 public: 406 407 // Clock control. 408 409 virtual int have_clock(Cpm_regs ®s); 410 virtual void start_clock(Cpm_regs ®s); 411 virtual void stop_clock(Cpm_regs ®s); 412 413 // Output frequency. 414 415 uint32_t get_frequency(Cpm_regs ®s); 416 }; 417 418 419 420 // An actively managed clock with source. 421 422 class Clock_active : public Clock_base 423 { 424 protected: 425 Source _source; 426 427 virtual Control_base &_get_control() = 0; 428 429 public: 430 explicit Clock_active(Source source) 431 : _source(source) 432 { 433 } 434 435 explicit Clock_active() 436 : _source(Source::undefined) 437 { 438 } 439 440 virtual ~Clock_active(); 441 442 // Clock control. 443 444 virtual int have_clock(Cpm_regs ®s); 445 virtual void start_clock(Cpm_regs ®s); 446 virtual void stop_clock(Cpm_regs ®s); 447 448 // Clock source. 449 450 virtual uint8_t get_source(Cpm_regs ®s); 451 virtual void set_source(Cpm_regs ®s, uint8_t source); 452 453 // Clock source frequency. 454 455 virtual uint32_t get_source_frequency(Cpm_regs ®s); 456 457 // Output frequency. 458 459 virtual uint32_t get_frequency(Cpm_regs ®s); 460 }; 461 462 463 464 // Divided clock interface. 465 466 class Clock_divided : public Clock_active 467 { 468 protected: 469 virtual Divider_base &_get_divider() = 0; 470 471 public: 472 explicit Clock_divided(Source source) 473 : Clock_active(source) 474 { 475 } 476 477 virtual ~Clock_divided(); 478 479 // Output frequency. 480 481 uint32_t get_frequency(Cpm_regs ®s); 482 }; 483 484 485 486 // PLL description. 487 488 class Pll : public Clock_divided 489 { 490 // Value storage. 491 492 Control_pll _control; 493 Divider_pll _divider; 494 495 virtual Control_base &_get_control() { return _control; } 496 virtual Divider_base &_get_divider() { return _divider; } 497 498 public: 499 explicit Pll(Source source, Control_pll control, Divider_pll divider) 500 : Clock_divided(source), _control(control), _divider(divider) 501 { 502 } 503 504 virtual ~Pll(); 505 506 // General frequency modifiers. 507 508 uint32_t get_multiplier(Cpm_regs ®s); 509 void set_multiplier(Cpm_regs ®s, uint32_t multiplier); 510 uint32_t get_input_divider(Cpm_regs ®s); 511 void set_input_divider(Cpm_regs ®s, uint32_t divider); 512 uint32_t get_output_divider(Cpm_regs ®s); 513 void set_output_divider(Cpm_regs ®s, uint32_t divider); 514 515 // Output frequency. 516 517 uint32_t get_frequency(Cpm_regs ®s); 518 519 // Other operations. 520 521 void set_parameters(Cpm_regs ®s, uint32_t multiplier, 522 uint32_t in_divider, uint32_t out_divider); 523 }; 524 525 526 527 // Clock description. 528 529 class Clock : public Clock_divided 530 { 531 // Value storage. 532 533 Control _control; 534 Divider _divider; 535 536 virtual Control_base &_get_control() { return _control; } 537 virtual Divider_base &_get_divider() { return _divider; } 538 539 public: 540 explicit Clock(Source source, 541 Control control = Control::undefined, 542 Divider divider = Divider::undefined) 543 : Clock_divided(source), _control(control), _divider(divider) 544 { 545 } 546 547 // Clock divider. 548 549 uint32_t get_divider(Cpm_regs ®s); 550 void set_divider(Cpm_regs ®s, uint32_t divider); 551 }; 552 553 554 555 // I2S clock description. 556 557 class Clock_divided_i2s : public Clock_divided 558 { 559 // Value storage. 560 561 Control _control; 562 Divider_i2s _divider; 563 564 virtual Control_base &_get_control() { return _control; } 565 virtual Divider_base &_get_divider() { return _divider; } 566 567 public: 568 explicit Clock_divided_i2s(Source source, Control control, Divider_i2s divider) 569 : Clock_divided(source), _control(control), _divider(divider) 570 { 571 } 572 }; 573 574 #endif /* __cplusplus */