1 /* 2 * U-Boot and jz4740 LCD controller definitions. 3 * 4 * Copyright (C) 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * Copyright (C) 2005-2007, Ingenic Semiconductor Inc. 6 * Copyright (C) 2009 Qi Hardware Inc. 7 * Author: Xiangfu Liu <xiangfu@sharism.cc> 8 * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> 9 * Copyright (C) 2015, 2016, 2017, 2018 Paul Boddie <paul@boddie.org.uk> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 24 * Boston, MA 02110-1301, USA 25 */ 26 27 #ifndef __JZLCD_H__ 28 #define __JZLCD_H__ 29 30 #include <stdint.h> 31 32 /* Framebuffer characteristics. */ 33 34 struct jzfb_info { 35 uint32_t cfg; /* panel mode and pin usage etc. */ 36 uint32_t w; /* display width in pixels */ 37 uint32_t h; /* display height in pixels */ 38 uint32_t bpp; /* bits per pixel */ 39 uint32_t fclk; /* frame clock */ 40 uint32_t hsw; /* hsync width, in pixel clock */ 41 uint32_t vsw; /* vsync width, in line count */ 42 uint32_t elw; /* end of line, in pixel clock */ 43 uint32_t blw; /* begin of line, in pixel clock */ 44 uint32_t efw; /* end of frame, in line count */ 45 uint32_t bfw; /* begin of frame, in line count */ 46 }; 47 48 /* LCD controller stucture for jz4740. */ 49 50 struct jz_fb_dma_descriptor { 51 struct jz_fb_dma_descriptor *fdadr; /* frame descriptor address register */ 52 uint32_t fsadr; /* frame source address register */ 53 uint32_t fidr; /* frame identifier register */ 54 uint32_t ldcmd; /* command register */ 55 }; 56 57 /* Display characteristics and memory resources. */ 58 59 typedef struct vidinfo { 60 struct jzfb_info *jz_fb; /* framebuffer and panel properties */ 61 void *lcd; /* address of LCD controller registers */ 62 } vidinfo_t; 63 64 65 66 /* Public functions. */ 67 68 uint32_t jz4740_lcd_get_aligned_size(vidinfo_t *vid); 69 uint32_t jz4740_lcd_get_descriptors_size(vidinfo_t *vid); 70 uint32_t jz4740_lcd_get_line_size(vidinfo_t *vid); 71 uint32_t jz4740_lcd_get_screen_size(vidinfo_t *vid); 72 uint32_t jz4740_lcd_get_pixel_clock(vidinfo_t *vid); 73 74 void jz4740_lcd_set_base(vidinfo_t *vid, void *lcd_base); 75 76 void jz4740_lcd_ctrl_init( 77 struct jz_fb_dma_descriptor *desc_vaddr, 78 struct jz_fb_dma_descriptor *desc_paddr, 79 void *fb_vaddr, void *fb_paddr, 80 vidinfo_t *vid); 81 82 void jz4740_lcd_hw_init(vidinfo_t *vid); 83 void jz4740_lcd_set_bpp(uint8_t bpp, vidinfo_t *vid); 84 void jz4740_lcd_enable(vidinfo_t *vid); 85 void jz4740_lcd_disable(vidinfo_t *vid); 86 void jz4740_lcd_quick_disable(vidinfo_t *vid); 87 88 89 90 /* Alignment/rounding macros. */ 91 92 #define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) 93 #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) 94 95 /* Display device mode select (LCD_CFG.MODE). */ 96 97 #define MODE_MASK 0x0f 98 #define MODE_TFT_GEN 0x00 99 #define MODE_TFT_SHARP 0x01 100 #define MODE_TFT_CASIO 0x02 101 #define MODE_TFT_SAMSUNG 0x03 102 #define MODE_CCIR656_NONINT 0x04 103 #define MODE_CCIR656_INT 0x05 104 #define MODE_STN_COLOR_SINGLE 0x08 105 #define MODE_STN_MONO_SINGLE 0x09 106 #define MODE_STN_COLOR_DUAL 0x0a 107 #define MODE_STN_MONO_DUAL 0x0b 108 #define MODE_8BIT_SERIAL_TFT 0x0c 109 110 /* 16-bit or 18-bit TFT panel selection (LCD_CFG.18/16). */ 111 112 #define MODE_TFT_18BIT (1<<7) 113 114 /* STN pin utilisation (LCD_CFG.PDW). */ 115 116 #define STN_DAT_PIN1 (0x00 << 4) 117 #define STN_DAT_PIN2 (0x01 << 4) 118 #define STN_DAT_PIN4 (0x02 << 4) 119 #define STN_DAT_PIN8 (0x03 << 4) 120 #define STN_DAT_PINMASK STN_DAT_PIN8 121 122 /* Pin reset states (LCD_CFG). */ 123 124 #define STFT_PSHI (1 << 15) 125 #define STFT_CLSHI (1 << 14) 126 #define STFT_SPLHI (1 << 13) 127 #define STFT_REVHI (1 << 12) 128 129 /* Sync direction (LCD_CFG.SYNDIR). */ 130 131 #define SYNC_MASTER (0 << 16) 132 #define SYNC_SLAVE (1 << 16) 133 134 /* Data enable polarity (LCD_CFG.DEP). */ 135 136 #define DE_P (0 << 9) 137 #define DE_N (1 << 9) 138 139 /* Pixel clock polarity (LCD_CFG.PCP). */ 140 141 #define PCLK_P (0 << 10) 142 #define PCLK_N (1 << 10) 143 144 /* Horizontal sync polarity (LCD_CFG.HSP). */ 145 146 #define HSYNC_P (0 << 11) 147 #define HSYNC_N (1 << 11) 148 149 /* Vertical sync polarity (LCD_CFG.VSP). */ 150 151 #define VSYNC_P (0 << 8) 152 #define VSYNC_N (1 << 8) 153 154 /* Inverse output data (LCD_CFG.INVDAT). */ 155 156 #define DATA_NORMAL (0 << 17) 157 #define DATA_INVERSE (1 << 17) 158 159 /* Register offsets. */ 160 161 #define LCD_CFG 0x00 /* LCD Configure Register */ 162 #define LCD_VSYNC 0x04 /* Vertical Synchronize Register */ 163 #define LCD_HSYNC 0x08 /* Horizontal Synchronize Register */ 164 #define LCD_VAT 0x0c /* Virtual Area Setting Register */ 165 #define LCD_DAH 0x10 /* Display Area Horizontal Start/End Point */ 166 #define LCD_DAV 0x14 /* Display Area Vertical Start/End Point */ 167 #define LCD_PS 0x18 /* PS Signal Setting */ 168 #define LCD_CLS 0x1c /* CLS Signal Setting */ 169 #define LCD_SPL 0x20 /* SPL Signal Setting */ 170 #define LCD_REV 0x24 /* REV Signal Setting */ 171 #define LCD_CTRL 0x30 /* LCD Control Register */ 172 #define LCD_STATE 0x34 /* LCD Status Register */ 173 #define LCD_IID 0x38 /* Interrupt ID Register */ 174 #define LCD_DA0 0x40 /* Descriptor Address Register 0 */ 175 #define LCD_SA0 0x44 /* Source Address Register 0 */ 176 #define LCD_FID0 0x48 /* Frame ID Register 0 */ 177 #define LCD_CMD0 0x4c /* DMA Command Register 0 */ 178 #define LCD_DA1 0x50 /* Descriptor Address Register 1 */ 179 #define LCD_SA1 0x54 /* Source Address Register 1 */ 180 #define LCD_FID1 0x58 /* Frame ID Register 1 */ 181 #define LCD_CMD1 0x5c /* DMA Command Register 1 */ 182 183 /* Burst length selection (LCD_CTRL.BST). */ 184 185 #define LCD_CTRL_BST_MASK (0x03 << 28) 186 #define LCD_CTRL_BST_4 (0 << 28) /* 4-word */ 187 #define LCD_CTRL_BST_8 (1 << 28) /* 8-word */ 188 #define LCD_CTRL_BST_16 (2 << 28) /* 16-word */ 189 190 /* RGB mode (LCD_CTRL.RGB). */ 191 192 #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */ 193 #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */ 194 195 /* Output FIFO underrun protection (LCD_CTRL.OFUP). */ 196 197 #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */ 198 199 /* STN FRC algorithm selection (LCD_CTRL.FRC). */ 200 201 #define LCD_CTRL_FRC_16 (0 << 24) /* 16 grayscale */ 202 #define LCD_CTRL_FRC_4 (1 << 24) /* 4 grayscale */ 203 #define LCD_CTRL_FRC_2 (2 << 24) /* 2 grayscale */ 204 #define LCD_CTRL_FRC_MASK (0x03 << 24) 205 206 /* Load palette delay counter (LCD_CTRL.PDD) */ 207 208 #define LCD_CTRL_PDD_MASK (0xff << 16) 209 210 #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */ 211 #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */ 212 #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */ 213 #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */ 214 #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */ 215 #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */ 216 #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */ 217 #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */ 218 #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */ 219 #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */ 220 #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */ 221 222 /* Bits per pixel (LCD_CTRL.BPP). */ 223 224 #define LCD_CTRL_BPP_1 0 /* 1 bpp */ 225 #define LCD_CTRL_BPP_2 1 /* 2 bpp */ 226 #define LCD_CTRL_BPP_4 2 /* 4 bpp */ 227 #define LCD_CTRL_BPP_8 3 /* 8 bpp */ 228 #define LCD_CTRL_BPP_16 4 /* 15/16 bpp */ 229 #define LCD_CTRL_BPP_18_24 5 /* 18/24/32 bpp */ 230 #define LCD_CTRL_BPP_MASK 0x07 231 232 /* Palette buffer (LCD_CMDx.PAL). */ 233 234 #define LCD_CMD_PAL (1 << 28) 235 236 #endif /* __JZLCD_H__ */