1 /* 2 * GPIO driver for Ingenic X1600. 3 * (See below for additional copyright and licensing notices.) 4 * 5 * Copyright (C) 2017, 2023 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 * 22 * 23 * Subject to other copyrights, being derived from the bcm2835.cc and 24 * omap.cc GPIO driver implementations. 25 * 26 * This file is part of TUD:OS and distributed under the terms of the 27 * GNU General Public License 2. 28 * Please see the COPYING-GPL-2 file for details. 29 */ 30 31 #include <l4/sys/icu.h> 32 #include <l4/util/util.h> 33 #include <l4/devices/hw_mmio_register_block.h> 34 35 #include "gpio-x1600.h" 36 37 /* 38 GPIO register offsets (x in A..D). 39 40 Register summary: 41 42 PxINT 0 (function/GPIO) 1 (interrupt) 43 PxMSK 0 (function) 1 (GPIO) 0 (IRQ enable)/1 (IRQ disable) 44 PxPAT1 0 (function 0/1) 1 (function 2/3) 0 (output) 1 (input) 0 (level trigger) 1 (edge trigger) 45 PxPAT0 0 (function 0) 0 (function 2) 0 (output value 0) 0 (low level) 0 (falling edge) 46 1 (function 1) 1 (function 3) 1 (output value 1) 1 (high level) 1 (rising edge) 47 */ 48 49 enum Regs 50 { 51 Pin_level = 0x000, // PxPINL (read-only) 52 53 Port_int = 0x010, // PxINT 54 Port_int_set = 0x014, // PxINTS 55 Port_int_clear = 0x018, // PxINTC 56 57 Irq_mask = 0x020, // PxMSK (for PxINT == 1) 58 Irq_mask_set = 0x024, // PxMSKS 59 Irq_mask_clear = 0x028, // PxMSKC 60 Port_gpio = 0x020, // PxMSK (for PxINT == 0) 61 Port_gpio_set = 0x024, // PxMSKS 62 Port_gpio_clear = 0x028, // PxMSKC 63 64 Port_trigger = 0x030, // PxPAT1 (for PxINT == 1) 65 Port_trigger_set = 0x034, // PxPAT1S 66 Port_trigger_clear = 0x038, // PxPAT1C 67 Port_dir = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 1) 68 Port_dir_set = 0x034, // PxPAT1S 69 Port_dir_clear = 0x038, // PxPAT1C 70 Port_group1 = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 0) 71 Port_group1_set = 0x034, // PxPAT1S 72 Port_group1_clear = 0x038, // PxPAT1C 73 74 Port_level = 0x040, // PxPAT0 (for PxINT == 1) 75 Port_level_set = 0x044, // PxPAT0S 76 Port_level_clear = 0x048, // PxPAT0C 77 Port_data = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 1, PxPAT1 == 0) 78 Port_data_set = 0x044, // PxPAT0S 79 Port_data_clear = 0x048, // PxPAT0C 80 Port_group0 = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 0) 81 Port_group0_set = 0x044, // PxPAT0S 82 Port_group0_clear = 0x048, // PxPAT0C 83 84 Irq_flag = 0x050, // PxFLG (read-only) 85 Irq_flag_clear = 0x058, // PxFLGC 86 87 // Only the following registers differ from the JZ4780. The dual-edge 88 // registers being added to the X1600, with the pull-up/down registers being 89 // relocated. 90 91 Pull_edge = 0x070, // PxEDG 92 Pull_edge_set = 0x074, // PxEDGS 93 Pull_edge_clear = 0x078, // PxEDGC 94 95 Pull_disable = 0x080, // PxPE 96 Pull_disable_set = 0x084, // PxPES 97 Pull_disable_clear = 0x088, // PxPEC 98 99 // The shadow port Z is available at offset 0x700 and supports the INTS, INTC, 100 // MSKS, MSKC, PAT1S, PAT1C, PAT0S, PAT0C registers, along with the following. 101 102 Shadow_transfer = 0x0f0, // PzGID2LD 103 }; 104 105 106 107 // IRQ control for each GPIO pin. 108 109 Gpio_x1600_irq_pin::Gpio_x1600_irq_pin(unsigned pin, Hw::Register_block<32> const ®s) 110 : _pin(pin), _regs(regs) 111 {} 112 113 void 114 Gpio_x1600_irq_pin::write_reg_pin(unsigned reg) 115 { 116 // Write the pin bit to the register, setting or clearing the pin 117 // depending on the register chosen. 118 119 _regs[reg] = _pin_bit(_pin); 120 } 121 122 void Gpio_x1600_irq_pin::do_mask() 123 { 124 // Set the interrupt bit in the PxIM register. 125 126 write_reg_pin(Irq_mask_set); 127 } 128 129 void Gpio_x1600_irq_pin::do_unmask() 130 { 131 // Clear the interrupt bit in the PxIM register, first also clearing the 132 // flag bit in the PxFLG register to allow interrupts to be delivered. 133 134 write_reg_pin(Irq_flag_clear); 135 write_reg_pin(Irq_mask_clear); 136 } 137 138 bool Gpio_x1600_irq_pin::do_set_mode(unsigned mode) 139 { 140 // Standard comment found for this method: 141 // this operation touches multiple mmio registers and is thus 142 // not atomic, that's why we first mask the IRQ and if it was 143 // enabled we unmask it after we have changed the mode 144 145 /* NOTE: The X1600 provides a special port Z that allows changes to be made 146 and then committed atomically using PzGID2LD. This is not currently 147 used. */ 148 149 if (enabled()) 150 do_mask(); 151 152 // Do the PxINT, PxPAT1 and PxPAT0 configuration. 153 154 switch(mode) 155 { 156 case L4_IRQ_F_LEVEL_HIGH: 157 write_reg_pin(Port_int_set); 158 write_reg_pin(Port_trigger_clear); 159 write_reg_pin(Port_level_set); 160 break; 161 case L4_IRQ_F_LEVEL_LOW: 162 write_reg_pin(Port_int_set); 163 write_reg_pin(Port_trigger_clear); 164 write_reg_pin(Port_level_clear); 165 break; 166 case L4_IRQ_F_POS_EDGE: 167 write_reg_pin(Port_int_set); 168 write_reg_pin(Port_trigger_set); 169 write_reg_pin(Port_level_set); 170 break; 171 case L4_IRQ_F_NEG_EDGE: 172 write_reg_pin(Port_int_set); 173 write_reg_pin(Port_trigger_set); 174 write_reg_pin(Port_level_clear); 175 break; 176 177 default: 178 return false; 179 } 180 181 if (enabled()) 182 do_unmask(); 183 184 return true; 185 } 186 187 int Gpio_x1600_irq_pin::clear() 188 { 189 // Obtain the flag status for the pin, clearing it if set. 190 191 l4_uint32_t e = _regs[Irq_flag] & (1UL << _pin); 192 if (e) 193 _regs[Irq_flag_clear] = e; 194 195 return (e >> _pin); 196 } 197 198 bool Gpio_x1600_irq_pin::enabled() 199 { 200 return true; 201 } 202 203 204 205 // Initialise the GPIO controller. 206 207 Gpio_x1600_chip::Gpio_x1600_chip(l4_addr_t start, l4_addr_t end, 208 unsigned nr_pins, 209 l4_uint32_t pull_ups, l4_uint32_t pull_downs) 210 : _start(start), _end(end), 211 _nr_pins(nr_pins), 212 _pull_ups(pull_ups), _pull_downs(pull_downs) 213 { 214 _regs = new Hw::Mmio_register_block<32>(_start); 215 } 216 217 // Return the value of a pin. 218 219 int 220 Gpio_x1600_chip::get(unsigned pin) 221 { 222 if (pin >= _nr_pins) 223 throw -L4_EINVAL; 224 225 l4_uint32_t val = _regs[Pin_level]; 226 return (val >> _pin_shift(pin)) & 1; 227 } 228 229 // Return multiple pin values. 230 231 unsigned 232 Gpio_x1600_chip::multi_get(unsigned offset) 233 { 234 _reg_offset_check(offset); 235 return _regs[Pin_level]; 236 } 237 238 // Set the value of a pin. 239 240 void 241 Gpio_x1600_chip::set(unsigned pin, int value) 242 { 243 if (pin >= _nr_pins) 244 throw -L4_EINVAL; 245 246 l4_uint32_t reg_set = value ? Port_data_set : Port_data_clear; 247 _regs[reg_set] = _pin_bit(pin); 248 } 249 250 // Set multiple pin values. 251 252 void 253 Gpio_x1600_chip::multi_set(Pin_slice const &mask, unsigned data) 254 { 255 _reg_offset_check(mask.offset); 256 if (mask.mask & data) 257 _regs[Port_data_set] = (mask.mask & data); 258 if (mask.mask & ~data) 259 _regs[Port_data_clear] = (mask.mask & ~data); 260 } 261 262 // Set a pin up with the given mode and value (if appropriate). 263 264 void 265 Gpio_x1600_chip::setup(unsigned pin, unsigned mode, int value) 266 { 267 if (pin >= _nr_pins) 268 throw -L4_EINVAL; 269 270 config(pin, mode); 271 272 if (mode == Output) 273 set(pin, value); 274 } 275 276 // Configuration of a pin using the generic input/output/IRQ mode. 277 278 void 279 Gpio_x1600_chip::config(unsigned pin, unsigned mode) 280 { 281 switch (mode) 282 { 283 case Input: 284 _regs[Port_int_clear] = _pin_bit(pin); 285 _regs[Port_gpio_set] = _pin_bit(pin); 286 _regs[Port_dir_set] = _pin_bit(pin); 287 break; 288 case Output: 289 _regs[Port_int_clear] = _pin_bit(pin); 290 _regs[Port_gpio_set] = _pin_bit(pin); 291 _regs[Port_dir_clear] = _pin_bit(pin); 292 break; 293 case Irq: 294 _regs[Port_int_set] = _pin_bit(pin); 295 // Other details depend on the actual trigger mode. 296 break; 297 default: 298 break; 299 } 300 } 301 302 // Pull-up/down configuration for a pin. 303 304 void 305 Gpio_x1600_chip::config_pull(unsigned pin, unsigned mode) 306 { 307 if (pin >= _nr_pins) 308 throw -L4_EINVAL; 309 310 switch (mode) 311 { 312 case Pull_none: 313 _regs[Pull_disable_set] = _pin_bit(pin); 314 break; 315 case Pull_down: 316 if (_pin_bit(pin) & _pull_downs) 317 _regs[Pull_disable_clear] = _pin_bit(pin); 318 break; 319 case Pull_up: 320 if (_pin_bit(pin) & _pull_ups) 321 _regs[Pull_disable_clear] = _pin_bit(pin); 322 break; 323 default: 324 // Invalid pull-up/down mode for pin. 325 throw -L4_EINVAL; 326 } 327 } 328 329 // Pin function configuration. 330 331 void 332 Gpio_x1600_chip::config_pad(unsigned pin, unsigned func, unsigned value) 333 { 334 if (pin >= _nr_pins) 335 throw -L4_EINVAL; 336 337 if (value > 3) 338 throw -L4_EINVAL; 339 340 switch (func) 341 { 342 // Support two different outputs. 343 344 case Hw::Gpio_chip::Function_gpio: 345 _regs[Port_int_clear] = _pin_bit(pin); 346 _regs[Port_gpio_set] = _pin_bit(pin); 347 _regs[value & 1 ? Port_data_set : Port_data_clear] = _pin_bit(pin); 348 break; 349 350 // Support four different device functions. 351 352 case Hw::Gpio_chip::Function_alt: 353 _regs[Port_int_clear] = _pin_bit(pin); 354 _regs[Port_gpio_clear] = _pin_bit(pin); 355 _regs[value & 2 ? Port_group1_set : Port_group1_clear] = _pin_bit(pin); 356 _regs[value & 1 ? Port_group0_set : Port_group0_clear] = _pin_bit(pin); 357 break; 358 default: 359 throw -L4_EINVAL; 360 } 361 } 362 363 // Obtain a pin's configuration from a register in the supplied value. 364 365 void 366 Gpio_x1600_chip::config_get(unsigned pin, unsigned reg, unsigned *value) 367 { 368 if (pin >= _nr_pins) 369 throw -L4_EINVAL; 370 371 *value = (_regs[reg] >> _pin_shift(pin)) & 1; 372 } 373 374 // Return function and function-specific configuration for a pin. 375 376 void 377 Gpio_x1600_chip::config_pad_get(unsigned pin, unsigned *func, unsigned *value) 378 { 379 unsigned direction, gpio, group0, group1, interrupt, level, trigger; 380 381 config_get(pin, Port_int, &interrupt); 382 383 if (interrupt) 384 { 385 config_get(pin, Port_trigger, &trigger); 386 config_get(pin, Port_level, &level); 387 388 *func = Hw::Gpio_chip::Function_irq; 389 *value = (trigger ? (level ? L4_IRQ_F_POS_EDGE : L4_IRQ_F_NEG_EDGE) 390 : (level ? L4_IRQ_F_LEVEL_HIGH : L4_IRQ_F_LEVEL_LOW)); 391 return; 392 } 393 394 config_get(pin, Port_gpio, &gpio); 395 396 if (gpio) 397 { 398 config_get(pin, Port_dir, &direction); 399 400 *func = Hw::Gpio_chip::Function_gpio; 401 *value = direction ? Input : Output; 402 return; 403 } 404 405 *func = Hw::Gpio_chip::Function_alt; 406 407 config_get(pin, Port_group0, &group0); 408 config_get(pin, Port_group1, &group1); 409 410 *value = (group1 << 1) | group0; 411 } 412 413 // Obtain an IRQ abstraction for a pin. 414 415 Hw::Gpio_irq_pin * 416 Gpio_x1600_chip::get_irq(unsigned pin) 417 { 418 if (pin >= _nr_pins) 419 throw -L4_EINVAL; 420 421 return new Gpio_x1600_irq_pin(pin, _regs); 422 } 423 424 // Pin function configuration for multiple pins. 425 426 void 427 Gpio_x1600_chip::multi_config_pad(Pin_slice const &mask, unsigned func, unsigned val) 428 { 429 unsigned m = mask.mask; 430 for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1) 431 if (m & 1) 432 config_pad(pin, func, val); 433 } 434 435 // Set up multiple pins with the given mode. 436 437 void 438 Gpio_x1600_chip::multi_setup(Pin_slice const &mask, unsigned mode, unsigned outvalues) 439 { 440 unsigned m = mask.mask; 441 for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1, outvalues >>= 1) 442 if (m & 1) 443 setup(pin, mode, outvalues & 1); 444 } 445 446 447 448 // C language interface functions. 449 450 void *x1600_gpio_init(l4_addr_t start, l4_addr_t end, unsigned pins, 451 l4_uint32_t pull_ups, l4_uint32_t pull_downs) 452 { 453 return (void *) new Gpio_x1600_chip(start, end, pins, pull_ups, pull_downs); 454 } 455 456 void x1600_gpio_setup(void *gpio, unsigned pin, unsigned mode, int value) 457 { 458 static_cast<Gpio_x1600_chip *>(gpio)->setup(pin, mode, value); 459 } 460 461 void x1600_gpio_config_pull(void *gpio, unsigned pin, unsigned mode) 462 { 463 static_cast<Gpio_x1600_chip *>(gpio)->config_pull(pin, mode); 464 } 465 466 void x1600_gpio_config_pad(void *gpio, unsigned pin, unsigned func, unsigned value) 467 { 468 static_cast<Gpio_x1600_chip *>(gpio)->config_pad(pin, func, value); 469 } 470 471 void x1600_gpio_config_get(void *gpio, unsigned pin, unsigned reg, unsigned *value) 472 { 473 static_cast<Gpio_x1600_chip *>(gpio)->config_get(pin, reg, value); 474 } 475 476 void x1600_gpio_config_pad_get(void *gpio, unsigned pin, unsigned *func, unsigned *value) 477 { 478 static_cast<Gpio_x1600_chip *>(gpio)->config_pad_get(pin, func, value); 479 } 480 481 void x1600_gpio_multi_setup(void *gpio, Pin_slice const *mask, unsigned mode, unsigned outvalues) 482 { 483 static_cast<Gpio_x1600_chip *>(gpio)->multi_setup(*mask, mode, outvalues); 484 } 485 486 void x1600_gpio_multi_config_pad(void *gpio, Pin_slice const *mask, unsigned func, unsigned value) 487 { 488 static_cast<Gpio_x1600_chip *>(gpio)->multi_config_pad(*mask, func, value); 489 } 490 491 void x1600_gpio_multi_set(void *gpio, Pin_slice const *mask, unsigned data) 492 { 493 static_cast<Gpio_x1600_chip *>(gpio)->multi_set(*mask, data); 494 } 495 496 unsigned x1600_gpio_multi_get(void *gpio, unsigned offset) 497 { 498 return static_cast<Gpio_x1600_chip *>(gpio)->multi_get(offset); 499 } 500 501 int x1600_gpio_get(void *gpio, unsigned pin) 502 { 503 return static_cast<Gpio_x1600_chip *>(gpio)->get(pin); 504 } 505 506 void x1600_gpio_set(void *gpio, unsigned pin, int value) 507 { 508 static_cast<Gpio_x1600_chip *>(gpio)->set(pin, value); 509 } 510 511 void *x1600_gpio_get_irq(void *gpio, unsigned pin) 512 { 513 return (void *) static_cast<Gpio_x1600_chip *>(gpio)->get_irq(pin); 514 } 515 516 bool x1600_gpio_irq_set_mode(void *gpio_irq, unsigned mode) 517 { 518 return static_cast<Hw::Gpio_irq_pin *>(gpio_irq)->do_set_mode(mode); 519 }