1 /* 2 * MSC (MMC/SD controller) peripheral support. 3 * 4 * Copyright (C) 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/hw_mmio_register_block.h> 23 #include <l4/sys/irq.h> 24 #include <l4/util/util.h> 25 26 #include <math.h> 27 #include <stdio.h> 28 29 #include "msc-common.h" 30 #include "msc-defs.h" 31 32 33 34 // Command frame: 35 // byte: start (1), direction (1), command (6) 36 // 4 bytes: argument 37 // byte: CRC (7), end (1) 38 39 // IO_RW_DIRECT argument: 40 // Argument MSB to LSB: R/W (1), function number (3), read after write flag (1), 41 // stuff (1), register address (17), stuff (1), 42 // write data or stuff (8) 43 // 0x88000c08: W, function = 0, read after write, register address = 6 (CCCR), 44 // data = 8 (reset) 45 46 const uint32_t Io_rw_direct_reset = 0x88000c08; 47 48 // (IO_)SEND_OP_COND argument and default voltage range expected in R3, R4: 49 // Argument MSB to LSB: stuff (8), voltage range (16), reserved (8) 50 // 0x00ff8000: voltage range 2.7 - 3.6V 51 52 const uint32_t Ocr_default_voltage_range = 0x00ff8000; 53 54 // SEND_IF_COND argument and default voltage range expected in R7: 55 // Argument MSB to LSB: stuff (20), voltage supplied (4), check (8) 56 // 0x000001aa: voltage range 2.7 - 3.6V, check = 0b10101010 57 58 const uint32_t If_cond_default_voltage_range = 0x000001aa; 59 60 61 62 // Utilities. 63 64 static enum Command_data_control_bits 65 encode_bus_width(uint8_t width) 66 { 67 switch (width) 68 { 69 case 4: return Cdc_bus_width_4bit; 70 case 1: return Cdc_bus_width_1bit; 71 default: return Cdc_bus_width_1bit; 72 } 73 } 74 75 76 77 // Channel abstraction. 78 79 Msc_channel::Msc_channel(l4_addr_t msc_start, l4_addr_t addr, l4_cap_idx_t irq, 80 Cpm_chip *cpm, enum Clock_identifiers clock) 81 : _msc_start(msc_start), _irq(irq), _cpm(cpm), _clock(clock) 82 { 83 _regs = new Hw::Mmio_register_block<32>(addr); 84 } 85 86 Msc_channel::~Msc_channel() 87 { 88 } 89 90 // Utility methods. 91 // NOTE: Also defined in the CPM abstraction, should be consolidated. 92 93 uint32_t 94 Msc_channel::get_field(uint32_t reg, uint32_t mask, uint8_t shift) 95 { 96 return (_regs[reg] & (mask << shift)) >> shift; 97 } 98 99 void 100 Msc_channel::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) 101 { 102 _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); 103 } 104 105 bool 106 Msc_channel::set_clock_frequency(uint64_t frequency) 107 { 108 uint64_t division = _cpm->get_frequency(_clock) / frequency; 109 double divider = ceil(log2(division)); 110 111 if ((divider < 0) || (divider > Clock_rate_field_mask)) 112 return false; 113 114 set_field(Msc_clock_rate, Clock_rate_field_mask, Clock_rate_field_shift, 115 (uint32_t) divider); 116 117 return true; 118 } 119 120 void 121 Msc_channel::reset() 122 { 123 _regs[Msc_control] = _regs[Msc_control] | Control_reset; 124 125 while (_regs[Msc_status] & Status_resetting); 126 } 127 128 void 129 Msc_channel::start_clock() 130 { 131 set_field(Msc_control, Control_clock_control_field_mask, 132 Control_clock_control_field_shift, Control_clock_control_start); 133 134 while (!(_regs[Msc_status] & Status_clock_enabled)); 135 } 136 137 void 138 Msc_channel::stop_clock() 139 { 140 set_field(Msc_control, Control_clock_control_field_mask, 141 Control_clock_control_field_shift, Control_clock_control_stop); 142 143 while (_regs[Msc_status] & Status_clock_enabled); 144 } 145 146 void 147 Msc_channel::ack_irq(uint32_t flags) 148 { 149 // Clear the flags by setting them. 150 151 _regs[Msc_interrupt_flag] = _regs[Msc_interrupt_flag] | flags; 152 } 153 154 void 155 Msc_channel::unmask_irq(uint32_t flags) 156 { 157 ack_irq(flags); 158 159 if (_regs[Msc_interrupt_mask] & flags) 160 _regs[Msc_interrupt_mask] = _regs[Msc_interrupt_mask] & ~flags; 161 } 162 163 bool 164 Msc_channel::have_dma_enable_in_command() 165 { 166 return false; 167 } 168 169 bool 170 Msc_channel::have_dma_selection() 171 { 172 return true; 173 } 174 175 bool 176 Msc_channel::command_will_write(uint8_t index) 177 { 178 // NOTE: Probably incomplete coverage. 179 180 switch (index) 181 { 182 case Command_write_dat_until_stop: return true; 183 case Command_write_block: return true; 184 case Command_write_multiple_block: return true; 185 case Command_program_cid: return true; 186 case Command_program_csd: return true; 187 case Command_lock_unlock: return true; 188 default: return false; 189 } 190 } 191 192 bool 193 Msc_channel::app_command_will_write(uint8_t index) 194 { 195 // NOTE: Probably incomplete coverage. 196 197 (void) index; 198 199 return false; 200 } 201 202 bool 203 Msc_channel::command_with_data(uint8_t index) 204 { 205 // NOTE: Probably incomplete coverage. 206 207 switch (index) 208 { 209 case Command_read_dat_until_stop: return true; 210 case Command_read_single_block: return true; 211 case Command_read_multiple_block: return true; 212 case Command_write_dat_until_stop: return true; 213 case Command_write_block: return true; 214 case Command_write_multiple_block: return true; 215 case Command_program_cid: return true; 216 case Command_program_csd: return true; 217 case Command_lock_unlock: return true; 218 default: return false; 219 } 220 } 221 222 bool 223 Msc_channel::app_command_with_data(uint8_t index) 224 { 225 // NOTE: Probably incomplete coverage. 226 227 switch (index) 228 { 229 case App_command_sd_status: return true; 230 case App_command_send_num_wr_blocks: return true; 231 case App_command_send_scr: return true; 232 default: return false; 233 } 234 } 235 236 bool 237 Msc_channel::command_uses_busy(uint8_t index) 238 { 239 // NOTE: Probably incomplete coverage. 240 241 switch (index) 242 { 243 case Command_select_deselect_card: return true; 244 case Command_stop_transmission: return true; 245 default: return false; 246 } 247 } 248 249 bool 250 Msc_channel::app_command_uses_busy(uint8_t index) 251 { 252 // NOTE: Probably incomplete coverage. 253 254 (void) index; 255 256 return false; 257 } 258 259 uint8_t 260 Msc_channel::get_response_format(uint8_t index) 261 { 262 // NOTE: Probably incomplete coverage. 263 264 switch (index) 265 { 266 // Common commands without response. 267 268 case Command_go_idle_state: return 0; 269 case Command_set_dsr: return 0; 270 case Command_go_inactive_state: return 0; 271 272 // Common commands with response. 273 274 case Command_send_op_cond: return 3; 275 case Command_all_send_cid: return 2; 276 case Command_send_csd: return 2; 277 case Command_send_cid: return 2; 278 279 // SDIO only. 280 281 case Command_io_send_op_cond: return 4; 282 case Command_io_rw_direct: return 5; 283 284 // SDMEM only. 285 286 case Command_send_relative_addr: return 6; 287 case Command_send_if_cond: return 7; 288 289 // All other commands. 290 291 default: return 1; 292 } 293 } 294 295 uint8_t 296 Msc_channel::get_app_response_format(uint8_t index) 297 { 298 // NOTE: Probably incomplete coverage. 299 300 switch (index) 301 { 302 // SDMEM only. 303 304 case App_command_sd_send_op_cond: return 3; 305 306 // All other commands. 307 308 default: return 1; 309 } 310 } 311 312 // Read a response directly from the FIFO. 313 314 void 315 Msc_channel::read_response(uint16_t *buffer, uint8_t units) 316 { 317 uint8_t unit = units; 318 319 while (unit > 0) 320 { 321 uint32_t data = _regs[Msc_response_fifo]; 322 323 // Ignore the upper byte of the last unit in small transfers since it is the 324 // lower byte from the previous unit not shifted out of the register. 325 326 unit--; 327 328 if ((unit == 0) && (units == 3)) 329 buffer[unit] = (data & 0xff) << 8; 330 else 331 buffer[unit] = data; 332 } 333 } 334 335 // Send an application-specific command. 336 337 bool 338 Msc_channel::send_app_command(uint8_t index, uint32_t arg) 339 { 340 if (!send_command(Command_app_cmd, _cards[_card].rca << 16)) 341 return false; 342 343 return send_command(index, arg, get_app_response_format(index), 344 app_command_with_data(index), 345 app_command_will_write(index), 346 app_command_uses_busy(index)); 347 } 348 349 // Send a common MMC/SD command. 350 351 bool 352 Msc_channel::send_command(uint8_t index, uint32_t arg) 353 { 354 return send_command(index, arg, get_response_format(index), 355 command_with_data(index), 356 command_will_write(index), 357 command_uses_busy(index)); 358 } 359 360 // Initiate a command having the given index and using the given argument, 361 // employing the specified response format and involving a data transfer if 362 // indicated. 363 364 bool 365 Msc_channel::send_command(uint8_t index, uint32_t arg, uint8_t response_format, 366 bool data, bool write, bool busy) 367 { 368 stop_clock(); 369 370 // Enable DMA for data transfers for JZ4780, X1600 and others that have a 371 // channel-level control selecting special or conventional DMA. 372 373 if (have_dma_selection()) 374 _regs[Msc_dma_control] = (data ? Dma_select_common_dma | Dma_enable : Dma_disable); 375 376 // Set the command index and argument. 377 378 _regs[Msc_command_index] = index; 379 _regs[Msc_command_argument] = arg; 380 381 // Configure the response format and data bus width. 382 383 set_field(Msc_command_data_control, Cdc_response_format_field_mask, 384 Cdc_response_format_field_shift, response_format); 385 386 // NOTE: May need to set the SD bus width. 387 388 set_field(Msc_command_data_control, Cdc_bus_width_field_mask, 389 Cdc_bus_width_field_shift, 390 encode_bus_width(_cards[_card].bus_width)); 391 392 set_field(Msc_command_data_control, Cdc_recv_fifo_level_field_mask, 393 Cdc_recv_fifo_level_field_shift, Cdc_fifo_level_16); 394 395 set_field(Msc_command_data_control, Cdc_trans_fifo_level_field_mask, 396 Cdc_trans_fifo_level_field_shift, Cdc_fifo_level_16); 397 398 // Set and clear control bits appropriate to the command. 399 400 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] | 401 (busy ? Cdc_expect_busy : Cdc_do_not_expect_busy) | 402 (data ? Cdc_data_with_command : Cdc_no_data_with_command) | 403 (write ? Cdc_write_operation : Cdc_read_operation); 404 405 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] & 406 ~((busy ? Cdc_do_not_expect_busy : Cdc_expect_busy) | 407 (data ? Cdc_no_data_with_command : Cdc_data_with_command) | 408 (write ? Cdc_read_operation : Cdc_write_operation) | 409 Cdc_stream_block | Cdc_init_sequence); 410 411 // Pre-JZ4780 SoCs enable DMA in the command/data register. 412 413 if (have_dma_enable_in_command()) 414 set_field(Msc_command_data_control, Cdc_dma_field_mask, Cdc_dma_field_shift, 415 data ? Cdc_dma_enable : Cdc_dma_disable); 416 417 // Unmask interrupts, start the clock, then initiate the command. 418 419 uint32_t flags = Int_end_command_response | Int_response_timeout; 420 421 unmask_irq(flags); 422 start_clock(); 423 424 _regs[Msc_control] = _regs[Msc_control] | Control_start_operation; 425 426 // Wait for command completion. 427 428 if (!wait_for_irq(flags)) 429 return false; 430 431 // Determine whether a timeout occurred. 432 433 bool have_response = !((_regs[Msc_interrupt_flag] & Int_response_timeout) || 434 (_regs[Msc_status] & Status_response_crc_error) || 435 (_regs[Msc_status] & Status_timeout_response)); 436 437 // Acknowledge the response interrupts and return the status. 438 439 ack_irq(flags); 440 return have_response; 441 } 442 443 // Wait indefinitely for an interrupt request, returning true if one was delivered. 444 445 bool 446 Msc_channel::wait_for_irq(uint32_t flags) 447 { 448 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && 449 (_regs[Msc_interrupt_flag] & flags); 450 } 451 452 // Wait up to the given timeout (in microseconds) for an interrupt request, 453 // returning true if one was delivered. 454 455 bool 456 Msc_channel::wait_for_irq(uint32_t flags, unsigned int timeout) 457 { 458 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, 459 l4util_micros2l4to(timeout)))) && 460 (_regs[Msc_interrupt_flag] & flags); 461 } 462 463 464 465 // Check the voltage range of the SD card, potentially establishing that it is 466 // a high capacity card. Return false if the voltage range is incompatible. 467 468 bool 469 Msc_channel::check_sd() 470 { 471 struct R7 r7; 472 473 // Send an interface condition command. 474 // A card may not respond to this command. 475 476 if (!send_command(Command_send_if_cond, If_cond_default_voltage_range)) 477 return true; 478 479 read_response((uint16_t *) &r7, Response_size_R7); 480 481 // Reject any card not supporting the default voltage range. 482 483 if (r7.check_voltage.raw != If_cond_default_voltage_range) 484 return false; 485 486 return true; 487 } 488 489 // Check the voltage range of the SDIO card, inactivating it if incompatible. 490 491 void 492 Msc_channel::init_sdio() 493 { 494 struct R4 r4; 495 uint32_t ocr = 0; 496 497 // Reset any SDIO card or IO unit in a combined memory/IO card. 498 // A non-SDIO card may not respond to this command. 499 500 if (!send_command(Command_io_rw_direct, Io_rw_direct_reset)) 501 return; 502 503 // Attempt to assert the operating conditions. 504 505 do 506 { 507 // Obtain OCR (operating conditions register) values for any IO card. 508 // Without a response, the card may have inactivated itself due to voltage 509 // range incompatibility reasons. 510 511 if (!send_command(Command_io_send_op_cond, ocr)) 512 return; 513 514 read_response((uint16_t *) &r4, Response_size_R4); 515 516 // Finish if no IO functions provided. 517 // NOTE: Should only need to check this the first time. 518 519 if (r4.number_io_functions == 0) 520 return; 521 522 if (r4.ocr != Ocr_default_voltage_range) 523 { 524 ocr = Ocr_default_voltage_range; 525 continue; 526 } 527 } 528 while (!r4.ready); 529 } 530 531 void 532 Msc_channel::init_sdmem() 533 { 534 struct R3 r3; 535 536 // Incorporate the HCS bit into the OCR for SDMEM. 537 538 uint32_t ocr = Ocr_high_capacity_storage; 539 540 do 541 { 542 if (!send_app_command(App_command_sd_send_op_cond, ocr)) 543 return; 544 545 read_response((uint16_t *) &r3, Response_size_R3); 546 547 if (r3.ocr != Ocr_default_voltage_range) 548 { 549 ocr = Ocr_default_voltage_range | Ocr_high_capacity_storage; 550 continue; 551 } 552 } 553 while (!(r3.ocr & Ocr_card_powered_up)); 554 } 555 556 void 557 Msc_channel::init_mmc() 558 { 559 // Obtain OCR (operating conditions register) values for each card using 560 // send_op_cond command variants without argument, or assert operating 561 // conditions with argument to avoid handling card responses. Where responses 562 // are solicited, the host must determine a suitable argument and reissue the 563 // command. 564 565 struct R3 r3; 566 uint32_t ocr = 0; 567 568 do 569 { 570 if (!send_command(Command_send_op_cond, ocr)) 571 return; 572 573 read_response((uint16_t *) &r3, Response_size_R3); 574 575 if (r3.ocr != Ocr_default_voltage_range) 576 { 577 ocr = Ocr_default_voltage_range; 578 continue; 579 } 580 } 581 while (!(r3.ocr & Ocr_card_powered_up)); 582 } 583 584 void 585 Msc_channel::identify_cards() 586 { 587 struct R2 r2; 588 struct R6 r6; 589 590 _num_cards = 0; 591 592 while (send_command(Command_all_send_cid, 0)) 593 { 594 read_response((uint16_t *) &r2, Response_size_R2); 595 596 _cards[_num_cards].cid = r2.payload.cid; 597 598 printf("card: %d\n", _num_cards); 599 printf("date: %d %d\n", r2.payload.cid.month, r2.payload.cid.year); 600 printf("serial: %d\n", r2.payload.cid.serial); 601 printf("revision: %d\n", r2.payload.cid.revision); 602 printf("name: %c%c%c%c%c\n", r2.payload.cid.name[4], r2.payload.cid.name[3], 603 r2.payload.cid.name[2], r2.payload.cid.name[1], 604 r2.payload.cid.name[0]); 605 printf("oem: %d\n", r2.payload.cid.oem); 606 printf("manufacturer: %d\n", r2.payload.cid.manufacturer); 607 608 // Try and obtain a card-issued address. 609 610 if (send_command(Command_send_relative_addr, 0)) 611 { 612 read_response((uint16_t *) &r6, Response_size_R6); 613 _cards[_num_cards].rca = r6.rca; 614 } 615 616 // Try and assign an address. 617 // Employ 1-based relative addressing. 618 619 else if (send_command(Command_set_relative_addr, _num_cards + 1)) 620 _cards[_num_cards].rca = _num_cards + 1; 621 622 // Otherwise, stop identification. 623 624 else 625 return; 626 627 // Set the default bus width to be determined. 628 629 _cards[_num_cards].bus_width = 0; 630 631 _num_cards++; 632 } 633 } 634 635 void 636 Msc_channel::query_cards() 637 { 638 struct R2 r2; 639 struct R3 r3; 640 uint8_t card; 641 642 for (card = 0; card < _num_cards; card++) 643 { 644 // Employ 1-based relative addressing. 645 646 if (!send_command(Command_send_csd, _cards[card].rca << 16)) 647 return; 648 649 read_response((uint16_t *) &r2, Response_size_R2); 650 651 _cards[card].csd = r2.payload.csd; 652 653 struct CSD *csd = &_cards[card].csd; 654 655 printf("card: %d\n", card); 656 printf("csd: %d\n", csd->csd); 657 printf("copy: %s\n", csd->copy ? "copied" : "original"); 658 printf("card command classes: %03x\n", csd->card_command_classes); 659 printf("device (size multiplier): %d %d\n", csd->device_size + 1, 660 1 << (csd->device_size_multiplier + 2)); 661 printf("device size: %d\n", (1 << csd->read_blocklen) * 662 (csd->device_size + 1) * 663 (1 << (csd->device_size_multiplier + 2))); 664 printf("transfer speed: %d MHz\n", csd->tran_speed == 0x32 ? 25 : 50); 665 printf("format group: %d %d\n", csd->format, r2.payload.csd.format_group); 666 printf("write time factor: %d\n", 1 << csd->write_time_factor); 667 printf("write protect (temp perm): %s %s\n", csd->temp_write_prot ? "yes" : "no", 668 csd->perm_write_prot ? "yes" : "no"); 669 printf("write protect group (enable size): %s %d\n", csd->write_prot_group_enable ? "yes" : "no", 670 csd->write_prot_group_size + 1); 671 printf("write block (partial length): %s %d\n", csd->write_block_partial ? "yes" : "no", 672 1 << csd->write_blocklen); 673 printf("read block (partial length): %s %d\n", csd->read_block_partial ? "yes" : "no", 674 1 << csd->read_blocklen); 675 printf("erase: sector single: %d %s\n", csd->erase_sector_size + 1, 676 csd->erase_single_block_enable ? "yes" : "no"); 677 printf("misalign: read write: %s %s\n", csd->read_block_misalign ? "yes" : "no", 678 csd->write_block_misalign ? "yes" : "no"); 679 printf("max read current (min max): %d %d\n", csd->max_read_current_min, 680 csd->max_read_current_max); 681 printf("max write current (min max): %d %d\n", csd->max_write_current_min, 682 csd->max_write_current_max); 683 printf("read access time (1 2): %d %d\n", csd->data_read_access_time_1, 684 csd->data_read_access_time_2); 685 printf("DSR: %s\n", csd->dsr_implemented ? "yes" : "no"); 686 687 // Query the OCR again now that we can associate it with a specific card. 688 689 if (!send_app_command(App_command_read_ocr, 0)) 690 return; 691 692 read_response((uint16_t *) &r3, Response_size_R3); 693 694 _cards[card].ocr = r3.ocr; 695 } 696 } 697 698 699 700 // Enable the controller and identify cards. 701 702 void 703 Msc_channel::enable() 704 { 705 // NOTE: X1600 and other recent SoCs only. 706 707 _regs[Msc_low_power_mode] = _regs[Msc_low_power_mode] & ~Low_power_mode_enable; 708 709 stop_clock(); 710 reset(); 711 712 // Slow the clock for initialisation. 713 // NOTE: Should produce an error. 714 715 if (!set_clock_frequency(400000)) 716 return; 717 718 send_command(Command_go_idle_state, 0); 719 720 if (check_sd()) 721 { 722 init_sdio(); 723 init_sdmem(); 724 } 725 726 init_mmc(); 727 identify_cards(); 728 query_cards(); 729 730 // Initially, no card is selected. 731 732 _card = -1; 733 } 734 735 // Obtain the card details. 736 737 struct msc_card * 738 Msc_channel::get_cards() 739 { 740 return _cards; 741 } 742 743 // Return the number of active cards. 744 745 uint8_t 746 Msc_channel::num_cards() 747 { 748 return _num_cards; 749 } 750 751 // Receive data from the selected card. 752 753 uint32_t 754 Msc_channel::recv_data(struct dma_region *region, uint32_t count) 755 { 756 if (count > region->size) 757 return 0; 758 759 uint32_t flags = Int_data_transfer_done; 760 761 unmask_irq(flags); 762 763 uint32_t to_transfer = transfer(_msc_start + Msc_recv_data_fifo, region->paddr, true, count); 764 765 wait_for_irq(flags); 766 ack_irq(flags); 767 768 if (!to_transfer || 769 (_regs[Msc_status] & Status_read_crc_error) || 770 (_regs[Msc_status] & Status_timeout_read)) 771 return 0; 772 773 return to_transfer; 774 } 775 776 // Send data to the selected card. 777 778 uint32_t 779 Msc_channel::send_data(struct dma_region *region, uint32_t count) 780 { 781 if (count > region->size) 782 return 0; 783 784 uint32_t flags = Int_data_transfer_done; 785 786 unmask_irq(flags); 787 788 uint32_t to_transfer = transfer(region->paddr, _msc_start + Msc_trans_data_fifo, false, count); 789 790 wait_for_irq(flags); 791 ack_irq(flags); 792 793 if (!to_transfer || 794 (_regs[Msc_status] & Status_write_crc_error_data) || 795 (_regs[Msc_status] & Status_write_crc_error_no_status)) 796 return 0; 797 798 return to_transfer; 799 } 800 801 // Read blocks from the indicated card into a memory region. 802 803 uint32_t 804 Msc_channel::read_blocks(uint8_t card, struct dma_region *region, 805 uint32_t block_address, uint32_t block_count) 806 { 807 uint32_t block_size = 1 << _cards[card].csd.read_blocklen; 808 struct R1 r1; 809 810 // Select the requested card. 811 812 if (_card != card) 813 { 814 // Choose an appropriate clock frequency for the card. 815 // NOTE: Should produce an error. 816 817 if (!set_clock_frequency(_cards[card].csd.tran_speed == 0x32 ? 818 25000000 : 50000000)) 819 return 0; 820 821 if (!send_command(Command_select_deselect_card, _cards[card].rca << 16)) 822 return 0; 823 824 read_response((uint16_t *) &r1, Response_size_R1); 825 826 if (r1.status & R1_status_error_mask) 827 return 0; 828 829 _card = card; 830 } 831 832 // NOTE: SMEM cards should allow bus width setting with the SCR register 833 // NOTE: describing the permitted values. 834 // NOTE: SDIO cards have their bus width set in CCCR via CMD52. 835 836 if (!_cards[card].bus_width) 837 { 838 if (send_app_command(App_command_set_bus_width, Bus_width_4bit)) 839 _cards[card].bus_width = 4; 840 else 841 _cards[card].bus_width = 1; 842 } 843 844 if (!send_command(Command_set_blocklen, block_size)) 845 return 0; 846 847 read_response((uint16_t *) &r1, Response_size_R1); 848 849 if (r1.status & R1_status_error_mask) 850 return 0; 851 852 // NOTE: Consider issuing a predefined block count command to any multiple 853 // NOTE: block operation, at least for cards that support it. 854 855 // Apply block count and size properties to the issued command. 856 857 _regs[Msc_block_count] = block_count; 858 _regs[Msc_block_length] = block_size; 859 860 // Where CCS = 0, byte addressing is used. Otherwise, block addressing is used. 861 862 uint32_t address; 863 864 if (_cards[card].ocr & Ocr_high_capacity_storage) 865 address = block_address; 866 else 867 address = block_address * block_size; 868 869 if (!send_command(block_count == 1 ? Command_read_single_block 870 : Command_read_multiple_block, address)) 871 return 0; 872 873 read_response((uint16_t *) &r1, Response_size_R1); 874 875 if (r1.status & R1_status_error_mask) 876 return 0; 877 878 // NOTE: Use Msc_block_success_count instead. 879 880 uint32_t transferred = recv_data(region, block_size * block_count); 881 882 if (block_count > 1) 883 send_command(Command_stop_transmission, 0); 884 885 return transferred; 886 } 887 888 889 890 // Peripheral abstraction. 891 892 Msc_chip::Msc_chip(l4_addr_t msc_start, l4_addr_t start, l4_addr_t end, 893 Cpm_chip *cpm) 894 : _msc_start(msc_start), _start(start), _end(end), _cpm(cpm) 895 { 896 }