1 /* 2 * GPIO driver for Ingenic X1600. 3 * (See below for additional copyright and licensing notices.) 4 * 5 * Copyright (C) 2017, 2023 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 * 22 * 23 * Subject to other copyrights, being derived from the bcm2835.cc and 24 * omap.cc GPIO driver implementations. 25 * 26 * This file is part of TUD:OS and distributed under the terms of the 27 * GNU General Public License 2. 28 * Please see the COPYING-GPL-2 file for details. 29 */ 30 31 #include <l4/sys/icu.h> 32 #include <l4/util/util.h> 33 #include <l4/devices/hw_mmio_register_block.h> 34 35 #include "gpio-x1600.h" 36 37 /* 38 GPIO register offsets (x in A..D). 39 40 Register summary: 41 42 PxINT 0 (function/GPIO) 1 (interrupt) 43 PxMSK 0 (function) 1 (GPIO) 0 (IRQ enable)/1 (IRQ disable) 44 PxPAT1 0 (function 0/1) 1 (function 2/3) 0 (output) 1 (input) 0 (level trigger) 1 (edge trigger) 45 PxPAT0 0 (function 0) 0 (function 2) 0 (output value 0) 0 (low level) 0 (falling edge) 46 1 (function 1) 1 (function 3) 1 (output value 1) 1 (high level) 1 (rising edge) 47 */ 48 49 enum Regs 50 { 51 Pin_level = 0x000, // PxPINL (read-only) 52 53 Port_int = 0x010, // PxINT 54 Port_int_set = 0x014, // PxINTS 55 Port_int_clear = 0x018, // PxINTC 56 57 Irq_mask = 0x020, // PxMSK (for PxINT == 1) 58 Irq_mask_set = 0x024, // PxMSKS 59 Irq_mask_clear = 0x028, // PxMSKC 60 Port_gpio = 0x020, // PxMSK (for PxINT == 0) 61 Port_gpio_set = 0x024, // PxMSKS 62 Port_gpio_clear = 0x028, // PxMSKC 63 64 Port_trigger = 0x030, // PxPAT1 (for PxINT == 1) 65 Port_trigger_set = 0x034, // PxPAT1S 66 Port_trigger_clear = 0x038, // PxPAT1C 67 Port_dir = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 1) 68 Port_dir_set = 0x034, // PxPAT1S 69 Port_dir_clear = 0x038, // PxPAT1C 70 Port_group1 = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 0) 71 Port_group1_set = 0x034, // PxPAT1S 72 Port_group1_clear = 0x038, // PxPAT1C 73 74 Port_level = 0x040, // PxPAT0 (for PxINT == 1) 75 Port_level_set = 0x044, // PxPAT0S 76 Port_level_clear = 0x048, // PxPAT0C 77 Port_data = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 1, PxPAT1 == 0) 78 Port_data_set = 0x044, // PxPAT0S 79 Port_data_clear = 0x048, // PxPAT0C 80 Port_group0 = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 0) 81 Port_group0_set = 0x044, // PxPAT0S 82 Port_group0_clear = 0x048, // PxPAT0C 83 84 Irq_flag = 0x050, // PxFLG (read-only) 85 Irq_flag_clear = 0x058, // PxFLGC 86 87 // Only the following registers differ from the JZ4780. The dual-edge 88 // registers being added to the X1600, with the pull-up/down registers being 89 // relocated and their sense changed from disable to enable. 90 91 Pull_edge = 0x070, // PxEDG 92 Pull_edge_set = 0x074, // PxEDGS 93 Pull_edge_clear = 0x078, // PxEDGC 94 95 Pull_enable = 0x080, // PxPE 96 Pull_enable_set = 0x084, // PxPES 97 Pull_enable_clear = 0x088, // PxPEC 98 99 // The shadow port Z is available at offset 0x700 and supports the INTS, INTC, 100 // MSKS, MSKC, PAT1S, PAT1C, PAT0S, PAT0C registers, along with the following. 101 102 Shadow_transfer = 0x0f0, // PzGID2LD 103 }; 104 105 106 107 // IRQ control for each GPIO pin. 108 109 Gpio_x1600_irq_pin::Gpio_x1600_irq_pin(unsigned pin, Hw::Register_block<32> const ®s, 110 Hw::Register_block<32> const &shadow_regs, 111 uint8_t port_number) 112 : _pin(pin), _regs(regs), _shadow_regs(shadow_regs), _port_number(port_number), 113 _shadow(true) 114 {} 115 116 Gpio_x1600_irq_pin::Gpio_x1600_irq_pin(unsigned pin, Hw::Register_block<32> const ®s) 117 : _pin(pin), _regs(regs), _shadow(false) 118 {} 119 120 void 121 Gpio_x1600_irq_pin::write_reg_pin(unsigned reg) 122 { 123 // Write the pin bit to the register, setting or clearing the pin 124 // depending on the register chosen. 125 126 if (_shadow) 127 _shadow_regs[reg] = _pin_bit(_pin); 128 else 129 _regs[reg] = _pin_bit(_pin); 130 } 131 132 void Gpio_x1600_irq_pin::do_mask() 133 { 134 // Set the interrupt bit in the PxIM register. 135 136 write_reg_pin(Irq_mask_set); 137 } 138 139 void Gpio_x1600_irq_pin::do_unmask() 140 { 141 // Clear the interrupt bit in the PxIM register, first also clearing the 142 // flag bit in the PxFLG register to allow interrupts to be delivered. 143 144 write_reg_pin(Irq_flag_clear); 145 write_reg_pin(Irq_mask_clear); 146 } 147 148 bool Gpio_x1600_irq_pin::do_set_mode(unsigned mode) 149 { 150 // Standard comment found for this method: 151 // this operation touches multiple mmio registers and is thus 152 // not atomic, that's why we first mask the IRQ and if it was 153 // enabled we unmask it after we have changed the mode 154 155 // The X1600 provides a special port Z that allows changes to be made and then 156 // committed atomically using PzGID2LD. 157 158 if (!_shadow && enabled()) 159 do_mask(); 160 161 // Do the PxINT, PxPAT1 and PxPAT0 configuration. 162 163 switch(mode) 164 { 165 case L4_IRQ_F_LEVEL_HIGH: 166 write_reg_pin(Port_int_set); 167 write_reg_pin(Port_trigger_clear); 168 write_reg_pin(Port_level_set); 169 break; 170 case L4_IRQ_F_LEVEL_LOW: 171 write_reg_pin(Port_int_set); 172 write_reg_pin(Port_trigger_clear); 173 write_reg_pin(Port_level_clear); 174 break; 175 case L4_IRQ_F_POS_EDGE: 176 write_reg_pin(Port_int_set); 177 write_reg_pin(Port_trigger_set); 178 write_reg_pin(Port_level_set); 179 break; 180 case L4_IRQ_F_NEG_EDGE: 181 write_reg_pin(Port_int_set); 182 write_reg_pin(Port_trigger_set); 183 write_reg_pin(Port_level_clear); 184 break; 185 186 default: 187 return false; 188 } 189 190 if (_shadow) 191 _shadow_regs[Shadow_transfer] = _port_number; 192 else if (enabled()) 193 do_unmask(); 194 195 return true; 196 } 197 198 int Gpio_x1600_irq_pin::clear() 199 { 200 // Obtain the flag status for the pin, clearing it if set. 201 202 l4_uint32_t e = _regs[Irq_flag] & (1UL << _pin); 203 if (e) 204 _regs[Irq_flag_clear] = e; 205 206 return (e >> _pin); 207 } 208 209 bool Gpio_x1600_irq_pin::enabled() 210 { 211 return true; 212 } 213 214 215 216 // Initialise the GPIO controller. 217 218 Gpio_x1600_chip::Gpio_x1600_chip(l4_addr_t start, l4_addr_t end, 219 unsigned nr_pins, 220 l4_uint32_t pull_ups, l4_uint32_t pull_downs, 221 l4_addr_t shadow_start, l4_addr_t shadow_end, 222 uint8_t port_number) 223 : _start(start), _end(end), 224 _nr_pins(nr_pins), 225 _pull_ups(pull_ups), _pull_downs(pull_downs), 226 _shadow_start(shadow_start), _shadow_end(shadow_end), 227 _port_number(port_number) 228 { 229 _regs = new Hw::Mmio_register_block<32>(_start); 230 231 if (_shadow_start) 232 { 233 _shadow_regs = new Hw::Mmio_register_block<32>(_shadow_start); 234 _shadow = true; 235 } 236 else 237 _shadow = false; 238 } 239 240 void 241 Gpio_x1600_chip::write_reg_pin(unsigned reg, unsigned pin) 242 { 243 // Write the pin bit to the register, setting or clearing the pin 244 // depending on the register chosen. 245 246 if (_shadow) 247 _shadow_regs[reg] = _pin_bit(pin); 248 else 249 _regs[reg] = _pin_bit(pin); 250 } 251 252 // Return the value of a pin. 253 254 int 255 Gpio_x1600_chip::get(unsigned pin) 256 { 257 if (pin >= _nr_pins) 258 throw -L4_EINVAL; 259 260 l4_uint32_t val = _regs[Pin_level]; 261 return (val >> _pin_shift(pin)) & 1; 262 } 263 264 // Return multiple pin values. 265 266 unsigned 267 Gpio_x1600_chip::multi_get(unsigned offset) 268 { 269 _reg_offset_check(offset); 270 return _regs[Pin_level]; 271 } 272 273 // Set the value of a pin. 274 275 void 276 Gpio_x1600_chip::set(unsigned pin, int value) 277 { 278 if (pin >= _nr_pins) 279 throw -L4_EINVAL; 280 281 l4_uint32_t reg_set = value ? Port_data_set : Port_data_clear; 282 _regs[reg_set] = _pin_bit(pin); 283 } 284 285 // Set multiple pin values. 286 287 void 288 Gpio_x1600_chip::multi_set(Pin_slice const &mask, unsigned data) 289 { 290 _reg_offset_check(mask.offset); 291 if (mask.mask & data) 292 _regs[Port_data_set] = (mask.mask & data); 293 if (mask.mask & ~data) 294 _regs[Port_data_clear] = (mask.mask & ~data); 295 } 296 297 // Set a pin up with the given mode and value (if appropriate). 298 299 void 300 Gpio_x1600_chip::setup(unsigned pin, unsigned mode, int value) 301 { 302 if (pin >= _nr_pins) 303 throw -L4_EINVAL; 304 305 config(pin, mode); 306 307 if (mode == Output) 308 set(pin, value); 309 } 310 311 // Configuration of a pin using the generic input/output/IRQ mode. 312 313 void 314 Gpio_x1600_chip::config(unsigned pin, unsigned mode) 315 { 316 switch (mode) 317 { 318 case Input: 319 write_reg_pin(Port_int_clear, pin); 320 write_reg_pin(Port_gpio_set, pin); 321 write_reg_pin(Port_dir_set, pin); 322 break; 323 case Output: 324 write_reg_pin(Port_int_clear, pin); 325 write_reg_pin(Port_gpio_set, pin); 326 write_reg_pin(Port_dir_clear, pin); 327 break; 328 case Irq: 329 write_reg_pin(Port_int_set, pin); 330 // Other details depend on the actual trigger mode. 331 break; 332 default: 333 break; 334 } 335 336 if (_shadow) 337 _shadow_regs[Shadow_transfer] = _port_number; 338 } 339 340 // Pull-up/down configuration for a pin. 341 342 void 343 Gpio_x1600_chip::config_pull(unsigned pin, unsigned mode) 344 { 345 if (pin >= _nr_pins) 346 throw -L4_EINVAL; 347 348 switch (mode) 349 { 350 case Pull_none: 351 _regs[Pull_enable_clear] = _pin_bit(pin); 352 break; 353 case Pull_down: 354 if (_pin_bit(pin) & _pull_downs) 355 _regs[Pull_enable_set] = _pin_bit(pin); 356 break; 357 case Pull_up: 358 if (_pin_bit(pin) & _pull_ups) 359 _regs[Pull_enable_set] = _pin_bit(pin); 360 break; 361 default: 362 // Invalid pull-up/down mode for pin. 363 throw -L4_EINVAL; 364 } 365 } 366 367 // Pin function configuration. 368 369 void 370 Gpio_x1600_chip::config_pad(unsigned pin, unsigned func, unsigned value) 371 { 372 if (pin >= _nr_pins) 373 throw -L4_EINVAL; 374 375 if (value > 3) 376 throw -L4_EINVAL; 377 378 switch (func) 379 { 380 // Support two different outputs. 381 382 case Hw::Gpio_chip::Function_gpio: 383 write_reg_pin(Port_int_clear, pin); 384 write_reg_pin(Port_gpio_set, pin); 385 write_reg_pin(value & 1 ? Port_data_set : Port_data_clear, pin); 386 break; 387 388 // Support four different device functions. 389 390 case Hw::Gpio_chip::Function_alt: 391 write_reg_pin(Port_int_clear, pin); 392 write_reg_pin(Port_gpio_clear, pin); 393 write_reg_pin(value & 2 ? Port_group1_set : Port_group1_clear, pin); 394 write_reg_pin(value & 1 ? Port_group0_set : Port_group0_clear, pin); 395 break; 396 default: 397 throw -L4_EINVAL; 398 } 399 400 if (_shadow) 401 _shadow_regs[Shadow_transfer] = _port_number; 402 } 403 404 // Obtain a pin's configuration from a register in the supplied value. 405 406 void 407 Gpio_x1600_chip::config_get(unsigned pin, unsigned reg, unsigned *value) 408 { 409 if (pin >= _nr_pins) 410 throw -L4_EINVAL; 411 412 *value = (_regs[reg] >> _pin_shift(pin)) & 1; 413 } 414 415 // Return function and function-specific configuration for a pin. 416 417 void 418 Gpio_x1600_chip::config_pad_get(unsigned pin, unsigned *func, unsigned *value) 419 { 420 unsigned direction, gpio, group0, group1, interrupt, level, trigger; 421 422 config_get(pin, Port_int, &interrupt); 423 424 if (interrupt) 425 { 426 config_get(pin, Port_trigger, &trigger); 427 config_get(pin, Port_level, &level); 428 429 *func = Hw::Gpio_chip::Function_irq; 430 *value = (trigger ? (level ? L4_IRQ_F_POS_EDGE : L4_IRQ_F_NEG_EDGE) 431 : (level ? L4_IRQ_F_LEVEL_HIGH : L4_IRQ_F_LEVEL_LOW)); 432 return; 433 } 434 435 config_get(pin, Port_gpio, &gpio); 436 437 if (gpio) 438 { 439 config_get(pin, Port_dir, &direction); 440 441 *func = Hw::Gpio_chip::Function_gpio; 442 *value = direction ? Input : Output; 443 return; 444 } 445 446 *func = Hw::Gpio_chip::Function_alt; 447 448 config_get(pin, Port_group0, &group0); 449 config_get(pin, Port_group1, &group1); 450 451 *value = (group1 << 1) | group0; 452 } 453 454 // Obtain an IRQ abstraction for a pin. 455 456 Hw::Gpio_irq_pin * 457 Gpio_x1600_chip::get_irq(unsigned pin) 458 { 459 if (pin >= _nr_pins) 460 throw -L4_EINVAL; 461 462 if (_shadow) 463 return new Gpio_x1600_irq_pin(pin, _regs, _shadow_regs, _port_number); 464 else 465 return new Gpio_x1600_irq_pin(pin, _regs); 466 } 467 468 // Pin function configuration for multiple pins. 469 470 void 471 Gpio_x1600_chip::multi_config_pad(Pin_slice const &mask, unsigned func, unsigned val) 472 { 473 unsigned m = mask.mask; 474 for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1) 475 if (m & 1) 476 config_pad(pin, func, val); 477 } 478 479 // Set up multiple pins with the given mode. 480 481 void 482 Gpio_x1600_chip::multi_setup(Pin_slice const &mask, unsigned mode, unsigned outvalues) 483 { 484 unsigned m = mask.mask; 485 for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1, outvalues >>= 1) 486 if (m & 1) 487 setup(pin, mode, outvalues & 1); 488 } 489 490 491 492 // C language interface functions. 493 494 void *x1600_gpio_init(l4_addr_t start, l4_addr_t end, unsigned pins, 495 l4_uint32_t pull_ups, l4_uint32_t pull_downs) 496 { 497 return (void *) new Gpio_x1600_chip(start, end, pins, pull_ups, pull_downs); 498 } 499 500 void *x1600_gpio_init_shadow(l4_addr_t start, l4_addr_t end, unsigned pins, 501 l4_uint32_t pull_ups, l4_uint32_t pull_downs, 502 l4_addr_t shadow_start, l4_addr_t shadow_end, 503 uint8_t port_number) 504 { 505 return (void *) new Gpio_x1600_chip(start, end, pins, pull_ups, pull_downs, 506 shadow_start, shadow_end, port_number); 507 } 508 509 void x1600_gpio_setup(void *gpio, unsigned pin, unsigned mode, int value) 510 { 511 static_cast<Gpio_x1600_chip *>(gpio)->setup(pin, mode, value); 512 } 513 514 void x1600_gpio_config_pull(void *gpio, unsigned pin, unsigned mode) 515 { 516 static_cast<Gpio_x1600_chip *>(gpio)->config_pull(pin, mode); 517 } 518 519 void x1600_gpio_config_pad(void *gpio, unsigned pin, unsigned func, unsigned value) 520 { 521 static_cast<Gpio_x1600_chip *>(gpio)->config_pad(pin, func, value); 522 } 523 524 void x1600_gpio_config_get(void *gpio, unsigned pin, unsigned reg, unsigned *value) 525 { 526 static_cast<Gpio_x1600_chip *>(gpio)->config_get(pin, reg, value); 527 } 528 529 void x1600_gpio_config_pad_get(void *gpio, unsigned pin, unsigned *func, unsigned *value) 530 { 531 static_cast<Gpio_x1600_chip *>(gpio)->config_pad_get(pin, func, value); 532 } 533 534 void x1600_gpio_multi_setup(void *gpio, Pin_slice const *mask, unsigned mode, unsigned outvalues) 535 { 536 static_cast<Gpio_x1600_chip *>(gpio)->multi_setup(*mask, mode, outvalues); 537 } 538 539 void x1600_gpio_multi_config_pad(void *gpio, Pin_slice const *mask, unsigned func, unsigned value) 540 { 541 static_cast<Gpio_x1600_chip *>(gpio)->multi_config_pad(*mask, func, value); 542 } 543 544 void x1600_gpio_multi_set(void *gpio, Pin_slice const *mask, unsigned data) 545 { 546 static_cast<Gpio_x1600_chip *>(gpio)->multi_set(*mask, data); 547 } 548 549 unsigned x1600_gpio_multi_get(void *gpio, unsigned offset) 550 { 551 return static_cast<Gpio_x1600_chip *>(gpio)->multi_get(offset); 552 } 553 554 int x1600_gpio_get(void *gpio, unsigned pin) 555 { 556 return static_cast<Gpio_x1600_chip *>(gpio)->get(pin); 557 } 558 559 void x1600_gpio_set(void *gpio, unsigned pin, int value) 560 { 561 static_cast<Gpio_x1600_chip *>(gpio)->set(pin, value); 562 } 563 564 void *x1600_gpio_get_irq(void *gpio, unsigned pin) 565 { 566 return (void *) static_cast<Gpio_x1600_chip *>(gpio)->get_irq(pin); 567 } 568 569 bool x1600_gpio_irq_set_mode(void *gpio_irq, unsigned mode) 570 { 571 return static_cast<Hw::Gpio_irq_pin *>(gpio_irq)->do_set_mode(mode); 572 }