1 /* 2 * I2C support for the X1600. 3 * 4 * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-x1600.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/icu.h> 26 #include <l4/util/util.h> 27 #include <sys/time.h> 28 29 /* NOTE: This peripheral is very similar to the JZ4780 with the registers 30 renamed to I2C from SMB, with a few high speed registers added, and 31 with I2C_SDAHD appearing at a different location. */ 32 33 enum Regs 34 { 35 I2c_control = 0x000, // I2C_CON 36 I2c_target_address = 0x004, // I2C_TAR 37 I2c_slave_address = 0x008, // I2C_SAR 38 I2c_master_code = 0x00c, // I2C_HS_MADDR 39 I2c_data_command = 0x010, // I2C_DC 40 Std_high_count = 0x014, // I2C_SHCNT 41 Std_low_count = 0x018, // I2C_SLCNT 42 Fast_high_count = 0x01c, // I2C_FHCNT 43 Fast_low_count = 0x020, // I2C_FLCNT 44 High_high_count = 0x024, // I2C_HHCNT 45 High_low_count = 0x028, // I2C_HLCNT 46 Int_status = 0x02c, // I2C_INTST (read-only) 47 Int_mask = 0x030, // I2C_INTM 48 Int_raw_status = 0x034, // I2C_RINTST (read-only) 49 Rx_fifo_thold = 0x038, // I2C_RXTL 50 Tx_fifo_thold = 0x03c, // I2C_TXTL 51 Int_combined_clear = 0x040, // I2C_CINT (read-only) 52 Int_rx_uf_clear = 0x044, // I2C_CRXUF (read-only) 53 Int_rx_of_clear = 0x048, // I2C_CRXOF (read-only) 54 Int_tx_of_clear = 0x04c, // I2C_CTXOF (read-only) 55 Int_rd_req_clear = 0x050, // I2C_CRXREQ (read-only) 56 Int_tx_abort_clear = 0x054, // I2C_CTXABT (read-only) 57 Int_rx_done_clear = 0x058, // I2C_CRXDN (read-only) 58 Int_activity_clear = 0x05c, // I2C_CACT (read-only) 59 Int_stop_clear = 0x060, // I2C_CSTP (read-only) 60 Int_start_clear = 0x064, // I2C_CSTT (read-only) 61 Int_call_clear = 0x068, // I2C_CGC (read-only) 62 I2c_enable = 0x06c, // I2C_ENB 63 I2c_status = 0x070, // I2C_ST (read-only) 64 Tx_fifo_count = 0x074, // I2C_TXFLR (read-only) 65 Rx_fifo_count = 0x078, // I2C_RXFLR (read-only) 66 I2c_sda_hold_time = 0x07c, // I2C_SDAHD 67 Trans_abort_status = 0x080, // I2C_ABTSRC (read-only) 68 Slv_data_nack = 0x084, // I2CSDNACK 69 I2c_dma_ctrl = 0x088, // I2C_DMACR 70 I2c_trans_data_lvl = 0x08c, // I2C_DMATDLR 71 I2c_recv_data_lvl = 0x090, // I2C_DMARDLR 72 I2c_sda_setup_time = 0x094, // I2C_SDASU 73 I2c_ack_call = 0x098, // I2C_ACKGC 74 I2c_enable_status = 0x09c, // I2C_ENBST (read-only) 75 I2c_spike_suppress = 0x0a0, // I2C_FSPKLEN 76 77 I2c_block_offset = 0x1000 78 }; 79 80 enum I2c_control_bits : unsigned 81 { 82 I2c_disable_slave = 0x40, // SLVDIS (slave disabled) 83 I2c_enable_restart = 0x20, // RESTART 84 I2c_master_10bit = 0x10, // MATP (read-only) 85 I2c_slave_10bit = 0x08, // SATP 86 I2c_speed_mode_mask = 0x06, // SPEED 87 I2c_enable_master = 0x01, // MD (master enabled) 88 I2c_speed_bit = 1, // SPD 89 }; 90 91 enum I2c_speed_mode_values : unsigned 92 { 93 I2c_speed_standard = 1, 94 I2c_speed_fast = 2, 95 I2c_speed_high = 3, 96 }; 97 98 enum I2c_enable_bits : unsigned 99 { 100 I2c_enable_enabled = 0x01, // I2CEN 101 }; 102 103 enum I2c_status_bits : unsigned 104 { 105 I2c_status_master_act = 0x20, // MSTACT (master active) 106 I2c_status_rx_nempty = 0x08, // RFNE (read queue not empty) 107 I2c_status_tx_empty = 0x04, // TFE (write queue empty) 108 I2c_status_tx_nfull = 0x02, // TFNF (write queue not full) 109 I2c_status_active = 0x01, // ACT (device active as master or slave) 110 }; 111 112 enum I2c_target_bits : unsigned 113 { 114 I2c_target_master_10bit = 0x1000, 115 I2c_target_special = 0x0800, // SPECIAL: perform general call or start byte 116 I2c_target_start_byte = 0x0400, // Special: start byte (1) or general call (0) 117 I2c_target_10bits = 0x3ff, // Mask for 10-bit address 118 I2c_target_7bits = 0x7f, // Mask for 7-bit address 119 }; 120 121 enum I2c_hold_control_bits : unsigned 122 { 123 /* The hold enable flag has been removed since the JZ4780 and the hold time 124 field widened. */ 125 126 I2c_hold_mask = 0xffff, 127 }; 128 129 enum I2c_setup_control_bits : unsigned 130 { 131 I2c_setup_mask = 0x0ff, // SDASU 132 }; 133 134 enum I2c_command_bits : unsigned 135 { 136 I2c_command_restart = 0x400, // RESTART: explicit restart before next byte 137 I2c_command_stop = 0x200, // STOP: explicit stop after next byte 138 I2c_command_no_stop = 0x000, 139 I2c_command_read = 0x100, // CMD 140 I2c_command_write = 0x000, // CMD 141 }; 142 143 enum I2c_fifo_bits : unsigned 144 { 145 I2c_fifo_limit = 64, // RXTL, TXTL (256 noted in field description) 146 }; 147 148 enum Int_bits : unsigned 149 { 150 Int_call = 0x800, // IGC (general call received) 151 Int_start = 0x400, // ISTT (start/restart condition occurred) 152 Int_stop = 0x200, // ISTP (stop condition occurred) 153 Int_activity = 0x100, // IACT (bus activity interrupt) 154 Int_rx_done = 0x080, // RXDN (read from master device done) 155 Int_tx_abort = 0x040, // TXABT (transmit abort) 156 Int_rd_req = 0x020, // RDREQ (read request from master device) 157 Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) 158 Int_tx_of = 0x008, // TXOF (overflow when writing to queue) 159 Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) 160 Int_rx_of = 0x002, // RXOF (overflow from device) 161 Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) 162 }; 163 164 165 166 // Initialise a channel. 167 168 I2c_x1600_channel::I2c_x1600_channel(l4_addr_t start, 169 Cpm_x1600_chip *cpm, 170 uint32_t frequency) 171 : _cpm(cpm), _frequency(frequency) 172 { 173 _regs = new Hw::Mmio_register_block<32>(start); 174 } 175 176 // Enable the channel. 177 178 void 179 I2c_x1600_channel::enable() 180 { 181 _regs[I2c_enable] = I2c_enable_enabled; 182 while (!(_regs[I2c_enable_status] & I2c_enable_enabled)); 183 } 184 185 // Disable the channel. 186 187 void 188 I2c_x1600_channel::disable() 189 { 190 _regs[I2c_enable] = 0; 191 while (_regs[I2c_enable_status] & I2c_enable_enabled); 192 } 193 194 // Return the configured frequency. 195 196 uint32_t 197 I2c_x1600_channel::get_frequency() 198 { 199 return _frequency; 200 } 201 202 // Set the frequency-related peripheral parameters. 203 204 void 205 I2c_x1600_channel::set_frequency() 206 { 207 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 208 // obtained from the CPM unit. It is known as I2C_DEV_CLK here and is scaled 209 // to kHz in order to keep the numbers easily representable, as is the bus 210 // frequency. 211 212 uint32_t i2c_dev_clk = _cpm->get_frequency(Clock_pclock) / 1000; 213 214 // Note that this is not I2C_DEV_CLK but the actual I2C bus frequency. 215 216 uint32_t i2c_clk = _frequency / 1000; 217 218 // Select the appropriate speed. 219 220 unsigned int speed = (i2c_clk <= 100) ? I2c_speed_standard 221 : (i2c_clk <= 400 ? I2c_speed_fast 222 : I2c_speed_high); 223 224 // NOTE: Permit broader configuration elsewhere. 225 226 _regs[I2c_control] = (speed << I2c_speed_bit) | 227 I2c_disable_slave | 228 I2c_enable_restart | 229 I2c_enable_master; 230 231 // According to the programming manual, if the PCLK period is T{I2C_DEV_CLK} 232 // then the I2C clock period is... 233 234 // T{SCL} = T{SCL_high} + T{SCL_low} 235 236 // Where... 237 238 // T{SCL_low} = T{I2C_DEV_CLK} * (#cycles for low signal) 239 // T{SCL_high} = T{I2C_DEV_CLK} * (#cycles for high signal) 240 241 // Since, with minimum periods being defined... 242 243 // T{SCL} >= T{min_SCL} 244 // T{SCL_low} >= T{min_SCL_low} 245 // T{SCL_high} >= T{min_SCL_high} 246 // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} 247 248 // Then the following applies... 249 250 // T{I2C_DEV_CLK} * (#cycles for low signal)) >= T{min_SCL_low} 251 // T{I2C_DEV_CLK} * (#cycles for high signal) >= T{min_SCL_high} 252 253 // To work with different clock speeds while maintaining the low-to-high 254 // ratios: 255 256 // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} 257 // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) 258 259 // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} 260 // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) 261 262 // Constraints are given with respect to the high and low count registers. 263 264 // #cycles for high signal = I2CxHCNT + 8 265 // #cycles for low signal = I2CxLCNT + 1 266 267 // From earlier, this yields... 268 269 // T{I2C_DEV_CLK} * (I2CxLCNT + 1) >= T{min_SCL_low} 270 // T{I2C_DEV_CLK} * (I2CxHCNT + 8) >= T{min_SCL_high} 271 272 // Rearranging... 273 274 // I2CxLCNT >= (T{min_SCL_low} / T{I2C_DEV_CLK}) - 1 275 // >= T{min_SCL_low} * I2C_DEV_CLK - 1 276 277 // I2CxHCNT >= (T{min_SCL_high} / T{I2C_DEV_CLK}) - 8 278 // >= T{min_SCL_high} * I2C_DEV_CLK - 8 279 280 // Introducing the definitions for the high and low periods... 281 282 // I2CxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 1 283 // >= (T{min_SCL_low} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 1 284 285 // I2CxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 8 286 // >= (T{min_SCL_high} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 8 287 288 uint32_t high_reg, low_reg; 289 uint32_t high_count, low_count; 290 int32_t hold_count; 291 uint32_t setup_count; 292 293 // Level hold times: 294 295 // Standard Fast High 296 // SCL low 4.7us 1.3us 0.5us 297 // SCL high 4.0us 0.6us 0.26us + 298 // SCL period 8.7us 1.9us 0.76us = 299 300 // See: UM10204 "I2C-bus specification and user manual" 301 // Table 10: t{LOW} and t{HIGH} 302 303 if (i2c_clk <= 100) // 100 kHz 304 { 305 low_count = (i2c_dev_clk * 47) / (i2c_clk * 87) - 1; 306 high_count = (i2c_dev_clk * 40) / (i2c_clk * 87) - 8; 307 low_reg = Std_low_count; 308 high_reg = Std_high_count; 309 } 310 else if (i2c_clk <= 400) // 400 kHz 311 { 312 low_count = (i2c_dev_clk * 13) / (i2c_clk * 19) - 1; 313 high_count = (i2c_dev_clk * 6) / (i2c_clk * 19) - 8; 314 low_reg = Fast_low_count; 315 high_reg = Fast_high_count; 316 } 317 else // > 400 kHz 318 { 319 // Note how the frequencies are scaled to accommodate the extra precision 320 // required. 321 322 low_count = (i2c_dev_clk / 10 * 50) / (i2c_clk / 10 * 76) - 1; 323 high_count = (i2c_dev_clk / 10 * 26) / (i2c_clk / 10 * 76) - 8; 324 low_reg = High_low_count; 325 high_reg = High_high_count; 326 } 327 328 // Minimum counts are 8 and 6 for low and high respectively. 329 330 _regs[low_reg] = low_count < 8 ? 8 : low_count; 331 _regs[high_reg] = high_count < 6 ? 6 : high_count; 332 333 // Data hold and setup times: 334 335 // Standard Fast High 336 // t{HD;DAT} 300ns 300ns 300ns 337 // t{SU;DAT} 250ns 100ns 50ns 338 339 // See: UM10204 "I2C-bus specification and user manual" 340 // Table 10: t{HD;DAT} and t{SU;DAT}, also note [3] 341 342 // T{delay} = (I2CSDAHD + 2) * T{I2C_DEV_CLK} 343 // I2CSDAHD = T{delay} / T{I2C_DEV_CLK} - 2 344 // I2CSDAHD = I2C_DEV_CLK * T{delay} - 2 345 346 // Since the device clock is in kHz (scaled down by 1000) and the times are 347 // given in ns (scaled up by 1000000000), a division of 1000000 is introduced. 348 349 hold_count = (i2c_dev_clk * 300) / 1000000 - 1; 350 351 _regs[I2c_sda_hold_time] = (_regs[I2c_sda_hold_time] & ~I2c_hold_mask) | 352 (hold_count < 0 ? 0 353 : (hold_count < (int) I2c_hold_mask ? (uint32_t) hold_count 354 : I2c_hold_mask)); 355 356 // I2C_SDASU is apparently not used in master mode. 357 358 // T{delay} = (I2CSDASU - 1) * T{I2C_DEV_CLK} 359 // I2CSDASU = T{delay} / T{I2C_DEV_CLK} + 1 360 // I2CSDASU = I2C_DEV_CLK * T{delay} + 1 361 362 if (i2c_clk <= 100) 363 setup_count = (i2c_dev_clk * 250) / 1000000 + 1; 364 else if (i2c_clk <= 400) 365 setup_count = (i2c_dev_clk * 100) / 1000000 + 1; 366 else 367 setup_count = (i2c_dev_clk * 50) / 1000000 + 1; 368 369 _regs[I2c_sda_setup_time] = (_regs[I2c_sda_setup_time] & ~I2c_setup_mask) | 370 (setup_count < I2c_setup_mask ? setup_count : I2c_setup_mask); 371 } 372 373 // Set the target address and enable transfer. 374 // NOTE: Only supporting 7-bit addresses currently. 375 376 void 377 I2c_x1600_channel::set_target(uint8_t address) 378 { 379 disable(); 380 set_frequency(); 381 _regs[I2c_target_address] = address & I2c_target_7bits; 382 init_parameters(); 383 enable(); 384 } 385 386 387 388 // Reset interrupt flags upon certain conditions. 389 390 void 391 I2c_x1600_channel::reset_flags() 392 { 393 volatile uint32_t r; 394 395 _regs[Int_mask] = 0; 396 397 // Read from the register to clear interrupts. 398 399 r = _regs[Int_combined_clear]; 400 (void) r; 401 } 402 403 // Initialise interrupt flags and queue thresholds for reading and writing. 404 405 void 406 I2c_x1600_channel::init_parameters() 407 { 408 // Handle read queue conditions for data, write queue conditions for commands. 409 410 reset_flags(); 411 412 _regs[Tx_fifo_thold] = 0; // write when 0 in queue 413 } 414 415 416 417 // Return whether the device is active. 418 419 int 420 I2c_x1600_channel::active() 421 { 422 return _regs[I2c_status] & I2c_status_master_act; 423 } 424 425 // Return whether data is available to receive. 426 427 int 428 I2c_x1600_channel::have_input() 429 { 430 return _regs[I2c_status] & I2c_status_rx_nempty; 431 } 432 433 // Return whether data is queued for sending. 434 435 int 436 I2c_x1600_channel::have_output() 437 { 438 return !(_regs[I2c_status] & I2c_status_tx_empty); 439 } 440 441 // Return whether data can be queued for sending. 442 443 int 444 I2c_x1600_channel::can_send() 445 { 446 return _regs[I2c_status] & I2c_status_tx_nfull; 447 } 448 449 // Return whether a receive operation has failed. 450 451 int 452 I2c_x1600_channel::read_failed() 453 { 454 return _regs[Int_status] & Int_rx_of; 455 } 456 457 // Return whether a send operation has failed. 458 459 int 460 I2c_x1600_channel::write_failed() 461 { 462 return _regs[Int_status] & Int_tx_abort; 463 } 464 465 int 466 I2c_x1600_channel::read_done() 467 { 468 return _pos == _total; 469 } 470 471 int 472 I2c_x1600_channel::write_done() 473 { 474 return (_reqpos == _total) && !have_output(); 475 } 476 477 unsigned 478 I2c_x1600_channel::have_read() 479 { 480 return _pos; 481 } 482 483 unsigned 484 I2c_x1600_channel::have_written() 485 { 486 return _reqpos; 487 } 488 489 int 490 I2c_x1600_channel::failed() 491 { 492 return _fail; 493 } 494 495 496 497 // Send read commands for empty queue entries. 498 499 void 500 I2c_x1600_channel::queue_reads() 501 { 502 unsigned int remaining = _total - _reqpos; 503 unsigned int queued = _reqpos - _pos; 504 unsigned int can_queue = I2c_fifo_limit - queued; 505 506 // Keep the number of reads in progress below the length of the read queue. 507 508 if (!can_queue) 509 return; 510 511 // At most, only queue as many reads as are remaining. 512 513 if (remaining < can_queue) 514 can_queue = remaining; 515 516 // Queue read requests for any remaining queue entries. 517 518 while (can_queue && can_send()) 519 { 520 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 521 522 _regs[I2c_data_command] = I2c_command_read | stop; 523 _reqpos++; 524 can_queue--; 525 } 526 527 // Update the threshold to be notified of any reduced remaining amount. 528 529 set_read_threshold(); 530 } 531 532 // Send write commands for empty queue entries. 533 534 void 535 I2c_x1600_channel::queue_writes() 536 { 537 unsigned int remaining = _total - _reqpos; 538 unsigned int can_queue = I2c_fifo_limit; 539 540 if (remaining < can_queue) 541 can_queue = remaining; 542 543 // Queue write requests for any remaining queue entries. 544 545 while (can_queue && can_send()) 546 { 547 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 548 549 _regs[I2c_data_command] = I2c_command_write | _buf[_reqpos] | stop; 550 _reqpos++; 551 can_queue--; 552 } 553 } 554 555 // Store read command results from the queue. 556 557 void 558 I2c_x1600_channel::store_reads() 559 { 560 // Read any input and store it in the buffer. 561 562 while (have_input() && (_pos < _reqpos)) 563 { 564 _buf[_pos] = _regs[I2c_data_command] & 0xff; 565 _pos++; 566 } 567 } 568 569 void 570 I2c_x1600_channel::set_read_threshold() 571 { 572 unsigned int queued = _reqpos - _pos; 573 574 if (!queued) 575 return; 576 577 // Read all expected. 578 579 _regs[Rx_fifo_thold] = queued - 1; 580 } 581 582 // Read from the target device. 583 584 void 585 I2c_x1600_channel::start_read(uint8_t buf[], unsigned int total, int stop) 586 { 587 _buf = buf; 588 _total = total; 589 _pos = 0; 590 _reqpos = 0; 591 _fail = 0; 592 _stop = stop; 593 594 reset_flags(); 595 596 _regs[Int_mask] = Int_rx_full | // read condition (reading needed) 597 Int_rx_of | // abort condition 598 Int_tx_abort; // general abort condition 599 600 // Perform initial read requests. 601 602 read(); 603 } 604 605 void 606 I2c_x1600_channel::read() 607 { 608 // Test for the general transfer abort condition. 609 610 if (read_failed() || write_failed()) 611 { 612 _fail = 1; 613 _regs[Int_mask] = 0; 614 disable(); 615 enable(); 616 return; 617 } 618 619 if (_regs[Int_status] & Int_rx_full) 620 store_reads(); 621 622 // Always attempt to queue more read requests. 623 624 queue_reads(); 625 } 626 627 // Write to the target device. 628 629 void 630 I2c_x1600_channel::start_write(uint8_t buf[], unsigned int total, int stop) 631 { 632 _buf = buf; 633 _total = total; 634 _reqpos = 0; 635 _fail = 0; 636 _stop = stop; 637 638 reset_flags(); 639 640 // Enable interrupts for further writes. 641 642 _regs[Int_mask] = Int_tx_empty | // write condition (writing needed) 643 Int_tx_abort; // abort condition 644 645 // Perform initial writes. 646 647 write(); 648 } 649 650 void 651 I2c_x1600_channel::write() 652 { 653 if (write_failed()) 654 { 655 _fail = 1; 656 _regs[Int_mask] = 0; 657 disable(); 658 enable(); 659 return; 660 } 661 662 if (_regs[Int_status] & Int_tx_empty) 663 queue_writes(); 664 } 665 666 // Explicitly stop communication. 667 668 void 669 I2c_x1600_channel::stop() 670 { 671 } 672 673 674 675 // Initialise the I2C controller. 676 677 I2c_x1600_chip::I2c_x1600_chip(l4_addr_t start, l4_addr_t end, 678 Cpm_x1600_chip *cpm, 679 uint32_t frequency) 680 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 681 { 682 } 683 684 // Obtain a channel object. 685 686 I2c_x1600_channel * 687 I2c_x1600_chip::get_channel(uint8_t channel) 688 { 689 l4_addr_t block = _start + channel * I2c_block_offset; 690 enum Clock_identifiers bits[] = {Clock_i2c0, Clock_i2c1}; 691 692 if (channel < 2) 693 { 694 _cpm->start_clock(bits[channel]); 695 return new I2c_x1600_channel(block, _cpm, _frequency); 696 } 697 else 698 throw -L4_EINVAL; 699 } 700 701 702 703 // C language interface functions. 704 705 void *x1600_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 706 { 707 return (void *) new I2c_x1600_chip(start, end, static_cast<Cpm_x1600_chip *>(cpm), frequency); 708 } 709 710 void x1600_i2c_disable(void *i2c_channel) 711 { 712 static_cast<I2c_x1600_channel *>(i2c_channel)->disable(); 713 } 714 715 void *x1600_i2c_get_channel(void *i2c, uint8_t channel) 716 { 717 return static_cast<I2c_x1600_chip *>(i2c)->get_channel(channel); 718 } 719 720 uint32_t x1600_i2c_get_frequency(void *i2c_channel) 721 { 722 return static_cast<I2c_x1600_channel *>(i2c_channel)->get_frequency(); 723 } 724 725 void x1600_i2c_set_target(void *i2c_channel, uint8_t addr) 726 { 727 static_cast<I2c_x1600_channel *>(i2c_channel)->set_target(addr); 728 } 729 730 void x1600_i2c_start_read(void *i2c_channel, uint8_t buf[], unsigned int total, 731 int stop) 732 { 733 static_cast<I2c_x1600_channel *>(i2c_channel)->start_read(buf, total, stop); 734 } 735 736 void x1600_i2c_read(void *i2c_channel) 737 { 738 static_cast<I2c_x1600_channel *>(i2c_channel)->read(); 739 } 740 741 void x1600_i2c_start_write(void *i2c_channel, uint8_t buf[], unsigned int total, 742 int stop) 743 { 744 static_cast<I2c_x1600_channel *>(i2c_channel)->start_write(buf, total, stop); 745 } 746 747 void x1600_i2c_write(void *i2c_channel) 748 { 749 static_cast<I2c_x1600_channel *>(i2c_channel)->write(); 750 } 751 752 int x1600_i2c_read_done(void *i2c_channel) 753 { 754 return static_cast<I2c_x1600_channel *>(i2c_channel)->read_done(); 755 } 756 757 int x1600_i2c_write_done(void *i2c_channel) 758 { 759 return static_cast<I2c_x1600_channel *>(i2c_channel)->write_done(); 760 } 761 762 unsigned int x1600_i2c_have_read(void *i2c_channel) 763 { 764 return static_cast<I2c_x1600_channel *>(i2c_channel)->have_read(); 765 } 766 767 unsigned int x1600_i2c_have_written(void *i2c_channel) 768 { 769 return static_cast<I2c_x1600_channel *>(i2c_channel)->have_written(); 770 } 771 772 int x1600_i2c_failed(void *i2c_channel) 773 { 774 return static_cast<I2c_x1600_channel *>(i2c_channel)->failed(); 775 } 776 777 void x1600_i2c_stop(void *i2c_channel) 778 { 779 static_cast<I2c_x1600_channel *>(i2c_channel)->stop(); 780 }