1 /* 2 * I2C support for the X1600. 3 * 4 * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-x1600.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/icu.h> 26 #include <l4/util/util.h> 27 #include <sys/time.h> 28 29 #include <stdio.h> 30 31 /* NOTE: This peripheral is very similar to the JZ4780 with the registers 32 renamed to I2C from SMB, with a few high speed registers added, and 33 with I2C_SDAHD appearing at a different location. */ 34 35 enum Regs 36 { 37 I2c_control = 0x000, // I2C_CON 38 I2c_target_address = 0x004, // I2C_TAR 39 I2c_slave_address = 0x008, // I2C_SAR 40 I2c_master_code = 0x00c, // I2C_HS_MADDR 41 I2c_data_command = 0x010, // I2C_DC 42 Std_high_count = 0x014, // I2C_SHCNT 43 Std_low_count = 0x018, // I2C_SLCNT 44 Fast_high_count = 0x01c, // I2C_FHCNT 45 Fast_low_count = 0x020, // I2C_FLCNT 46 High_high_count = 0x024, // I2C_HHCNT 47 High_low_count = 0x028, // I2C_HLCNT 48 Int_status = 0x02c, // I2C_INTST (read-only) 49 Int_mask = 0x030, // I2C_INTM 50 Int_raw_status = 0x034, // I2C_RINTST (read-only) 51 Rx_fifo_thold = 0x038, // I2C_RXTL 52 Tx_fifo_thold = 0x03c, // I2C_TXTL 53 Int_combined_clear = 0x040, // I2C_CINT (read-only) 54 Int_rx_uf_clear = 0x044, // I2C_CRXUF (read-only) 55 Int_rx_of_clear = 0x048, // I2C_CRXOF (read-only) 56 Int_tx_of_clear = 0x04c, // I2C_CTXOF (read-only) 57 Int_rd_req_clear = 0x050, // I2C_CRXREQ (read-only) 58 Int_tx_abort_clear = 0x054, // I2C_CTXABT (read-only) 59 Int_rx_done_clear = 0x058, // I2C_CRXDN (read-only) 60 Int_activity_clear = 0x05c, // I2C_CACT (read-only) 61 Int_stop_clear = 0x060, // I2C_CSTP (read-only) 62 Int_start_clear = 0x064, // I2C_CSTT (read-only) 63 Int_call_clear = 0x068, // I2C_CGC (read-only) 64 I2c_enable = 0x06c, // I2C_ENB 65 I2c_status = 0x070, // I2C_ST (read-only) 66 Tx_fifo_count = 0x074, // I2C_TXFLR (read-only) 67 Rx_fifo_count = 0x078, // I2C_RXFLR (read-only) 68 I2c_sda_hold_time = 0x07c, // I2C_SDAHD 69 Trans_abort_status = 0x080, // I2C_ABTSRC (read-only) 70 Slv_data_nack = 0x084, // I2CSDNACK 71 I2c_dma_ctrl = 0x088, // I2C_DMACR 72 I2c_trans_data_lvl = 0x08c, // I2C_DMATDLR 73 I2c_recv_data_lvl = 0x090, // I2C_DMARDLR 74 I2c_sda_setup_time = 0x094, // I2C_SDASU 75 I2c_ack_call = 0x098, // I2C_ACKGC 76 I2c_enable_status = 0x09c, // I2C_ENBST (read-only) 77 I2c_spike_suppress = 0x0a0, // I2C_FSPKLEN 78 79 I2c_block_offset = 0x1000 80 }; 81 82 enum I2c_control_bits : unsigned 83 { 84 I2c_disable_slave = 0x40, // SLVDIS (slave disabled) 85 I2c_enable_restart = 0x20, // RESTART 86 I2c_master_10bit = 0x10, // MATP (read-only) 87 I2c_slave_10bit = 0x08, // SATP 88 I2c_speed_mode_mask = 0x06, // SPEED 89 I2c_enable_master = 0x01, // MD (master enabled) 90 I2c_speed_bit = 1, // SPD 91 }; 92 93 enum I2c_speed_mode_values : unsigned 94 { 95 I2c_speed_standard = 1, 96 I2c_speed_fast = 2, 97 I2c_speed_high = 3, 98 }; 99 100 enum I2c_enable_bits : unsigned 101 { 102 I2c_enable_enabled = 0x01, // I2CEN 103 }; 104 105 enum I2c_status_bits : unsigned 106 { 107 I2c_status_master_act = 0x20, // MSTACT (master active) 108 I2c_status_rx_nempty = 0x08, // RFNE (read queue not empty) 109 I2c_status_tx_empty = 0x04, // TFE (write queue empty) 110 I2c_status_tx_nfull = 0x02, // TFNF (write queue not full) 111 I2c_status_active = 0x01, // ACT (device active as master or slave) 112 }; 113 114 enum I2c_target_bits : unsigned 115 { 116 I2c_target_master_10bit = 0x1000, 117 I2c_target_special = 0x0800, // SPECIAL: perform general call or start byte 118 I2c_target_start_byte = 0x0400, // Special: start byte (1) or general call (0) 119 I2c_target_10bits = 0x3ff, // Mask for 10-bit address 120 I2c_target_7bits = 0x7f, // Mask for 7-bit address 121 }; 122 123 enum I2c_hold_control_bits : unsigned 124 { 125 /* The hold enable flag has been removed since the JZ4780 and the hold time 126 field widened. */ 127 128 I2c_hold_mask = 0xffff, 129 }; 130 131 enum I2c_setup_control_bits : unsigned 132 { 133 I2c_setup_mask = 0x0ff, // SDASU 134 }; 135 136 enum I2c_command_bits : unsigned 137 { 138 I2c_command_restart = 0x400, // RESTART: explicit restart before next byte 139 I2c_command_stop = 0x200, // STOP: explicit stop after next byte 140 I2c_command_no_stop = 0x000, 141 I2c_command_read = 0x100, // CMD 142 I2c_command_write = 0x000, // CMD 143 }; 144 145 enum I2c_fifo_bits : unsigned 146 { 147 I2c_fifo_limit = 64, // RXTL, TXTL (256 noted in field description) 148 }; 149 150 enum Int_bits : unsigned 151 { 152 Int_call = 0x800, // IGC (general call received) 153 Int_start = 0x400, // ISTT (start/restart condition occurred) 154 Int_stop = 0x200, // ISTP (stop condition occurred) 155 Int_activity = 0x100, // IACT (bus activity interrupt) 156 Int_rx_done = 0x080, // RXDN (read from master device done) 157 Int_tx_abort = 0x040, // TXABT (transmit abort) 158 Int_rd_req = 0x020, // RDREQ (read request from master device) 159 Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) 160 Int_tx_of = 0x008, // TXOF (overflow when writing to queue) 161 Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) 162 Int_rx_of = 0x002, // RXOF (overflow from device) 163 Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) 164 }; 165 166 167 168 // Initialise a channel. 169 170 I2c_x1600_channel::I2c_x1600_channel(l4_addr_t start, 171 Cpm_x1600_chip *cpm, 172 uint32_t frequency) 173 : _cpm(cpm), _frequency(frequency) 174 { 175 _regs = new Hw::Mmio_register_block<32>(start); 176 } 177 178 // Enable the channel. 179 180 void 181 I2c_x1600_channel::enable() 182 { 183 _regs[I2c_enable] = I2c_enable_enabled; 184 while (!(_regs[I2c_enable_status] & I2c_enable_enabled)); 185 } 186 187 // Disable the channel. 188 189 void 190 I2c_x1600_channel::disable() 191 { 192 _regs[I2c_enable] = 0; 193 while (_regs[I2c_enable_status] & I2c_enable_enabled); 194 } 195 196 // Return the configured frequency. 197 198 uint32_t 199 I2c_x1600_channel::get_frequency() 200 { 201 return _frequency; 202 } 203 204 // Set the frequency-related peripheral parameters. 205 206 void 207 I2c_x1600_channel::set_frequency() 208 { 209 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 210 // obtained from the CPM unit. It is known as I2C_DEV_CLK here and is scaled 211 // to kHz in order to keep the numbers easily representable, as is the bus 212 // frequency. 213 214 uint32_t i2c_dev_clk = _cpm->get_frequency(Clock_pclock) / 1000; 215 216 // Note that this is not I2C_DEV_CLK but the actual I2C bus frequency. 217 218 uint32_t i2c_clk = _frequency / 1000; 219 220 // Select the appropriate speed. 221 222 unsigned int speed = (i2c_clk <= 100) ? I2c_speed_standard 223 : (i2c_clk <= 400 ? I2c_speed_fast 224 : I2c_speed_high); 225 226 _regs[I2c_control] = _regs[I2c_control] | (speed << I2c_speed_bit) | 227 I2c_disable_slave | 228 I2c_enable_restart | 229 I2c_enable_master; 230 231 // According to the programming manual, if the PCLK period is T{I2C_DEV_CLK} 232 // then the I2C clock period is... 233 234 // T{SCL} = T{SCL_high} + T{SCL_low} 235 236 // Where... 237 238 // T{SCL_low} = T{I2C_DEV_CLK} * (#cycles for low signal) 239 // T{SCL_high} = T{I2C_DEV_CLK} * (#cycles for high signal) 240 241 // Since, with minimum periods being defined... 242 243 // T{SCL} >= T{min_SCL} 244 // T{SCL_low} >= T{min_SCL_low} 245 // T{SCL_high} >= T{min_SCL_high} 246 // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} 247 248 // Then the following applies... 249 250 // T{I2C_DEV_CLK} * (#cycles for low signal)) >= T{min_SCL_low} 251 // T{I2C_DEV_CLK} * (#cycles for high signal) >= T{min_SCL_high} 252 253 // To work with different clock speeds while maintaining the low-to-high 254 // ratios: 255 256 // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} 257 // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) 258 259 // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} 260 // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) 261 262 // Constraints are given with respect to the high and low count registers. 263 264 // #cycles for high signal = I2CxHCNT + 8 265 // #cycles for low signal = I2CxLCNT + 1 266 267 // From earlier, this yields... 268 269 // T{I2C_DEV_CLK} * (I2CxLCNT + 1) >= T{min_SCL_low} 270 // T{I2C_DEV_CLK} * (I2CxHCNT + 8) >= T{min_SCL_high} 271 272 // Rearranging... 273 274 // I2CxLCNT >= (T{min_SCL_low} / T{I2C_DEV_CLK}) - 1 275 // >= T{min_SCL_low} * I2C_DEV_CLK - 1 276 277 // I2CxHCNT >= (T{min_SCL_high} / T{I2C_DEV_CLK}) - 8 278 // >= T{min_SCL_high} * I2C_DEV_CLK - 8 279 280 // Introducing the definitions for the high and low periods... 281 282 // I2CxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 1 283 // >= (T{min_SCL_low} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 1 284 285 // I2CxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 8 286 // >= (T{min_SCL_high} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 8 287 288 uint32_t high_reg, low_reg; 289 uint32_t high_count, low_count; 290 int32_t hold_count; 291 uint32_t setup_count; 292 293 // Level hold times: 294 295 // Standard Fast High 296 // SCL low 4.7us 1.3us 0.5us 297 // SCL high 4.0us 0.6us 0.26us + 298 // SCL period 8.7us 1.9us 0.76us = 299 300 // See: UM10204 "I2C-bus specification and user manual" 301 // Table 10: t{LOW} and t{HIGH} 302 303 if (i2c_clk <= 100) // 100 kHz 304 { 305 low_count = (i2c_dev_clk * 47) / (i2c_clk * 87) - 1; 306 high_count = (i2c_dev_clk * 40) / (i2c_clk * 87) - 8; 307 low_reg = Std_low_count; 308 high_reg = Std_high_count; 309 } 310 else if (i2c_clk <= 400) // 400 kHz 311 { 312 low_count = (i2c_dev_clk * 13) / (i2c_clk * 19) - 1; 313 high_count = (i2c_dev_clk * 6) / (i2c_clk * 19) - 8; 314 low_reg = Fast_low_count; 315 high_reg = Fast_high_count; 316 } 317 else // > 400 kHz 318 { 319 // Note how the frequencies are scaled to accommodate the extra precision 320 // required. 321 322 low_count = (i2c_dev_clk / 10 * 50) / (i2c_clk / 10 * 76) - 1; 323 high_count = (i2c_dev_clk / 10 * 26) / (i2c_clk / 10 * 76) - 8; 324 low_reg = High_low_count; 325 high_reg = High_high_count; 326 } 327 328 // Minimum counts are 8 and 6 for low and high respectively. 329 330 _regs[low_reg] = low_count < 8 ? 8 : low_count; 331 _regs[high_reg] = high_count < 6 ? 6 : high_count; 332 333 //printf("low_count: %d\n", low_count); 334 //printf("high_count: %d\n", high_count); 335 336 // Data hold and setup times: 337 338 // Standard Fast High 339 // t{HD;DAT} 300ns 300ns 300ns 340 // t{SU;DAT} 250ns 100ns 50ns 341 342 // See: UM10204 "I2C-bus specification and user manual" 343 // Table 10: t{HD;DAT} and t{SU;DAT}, also note [3] 344 345 // T{delay} = (I2CSDAHD + 2) * T{I2C_DEV_CLK} 346 // I2CSDAHD = T{delay} / T{I2C_DEV_CLK} - 2 347 // I2CSDAHD = I2C_DEV_CLK * T{delay} - 2 348 349 // Since the device clock is in kHz (scaled down by 1000) and the times are 350 // given in ns (scaled up by 1000000000), a division of 1000000 is introduced. 351 352 hold_count = (i2c_dev_clk * 300) / 1000000 - 1; 353 354 _regs[I2c_sda_hold_time] = (_regs[I2c_sda_hold_time] & ~I2c_hold_mask) | 355 (hold_count < 0 ? 0 356 : (hold_count < (int) I2c_hold_mask ? (uint32_t) hold_count 357 : I2c_hold_mask)); 358 359 //printf("i2c_dev_clk: %d\n", i2c_dev_clk); 360 //printf("SDA hold: %x\n", hold_count); 361 362 // I2C_SDASU is apparently not used in master mode. 363 364 // T{delay} = (I2CSDASU - 1) * T{I2C_DEV_CLK} 365 // I2CSDASU = T{delay} / T{I2C_DEV_CLK} + 1 366 // I2CSDASU = I2C_DEV_CLK * T{delay} + 1 367 368 if (i2c_clk <= 100) 369 setup_count = (i2c_dev_clk * 250) / 1000000 + 1; 370 else if (i2c_clk <= 400) 371 setup_count = (i2c_dev_clk * 100) / 1000000 + 1; 372 else 373 setup_count = (i2c_dev_clk * 50) / 1000000 + 1; 374 375 _regs[I2c_sda_setup_time] = (_regs[I2c_sda_setup_time] & ~I2c_setup_mask) | 376 (setup_count < I2c_setup_mask ? setup_count : I2c_setup_mask); 377 } 378 379 // Set the target address and enable transfer. 380 // NOTE: Only supporting 7-bit addresses currently. 381 382 void 383 I2c_x1600_channel::set_target(uint8_t address) 384 { 385 //printf("set_target: %x\n", address); 386 disable(); 387 set_frequency(); 388 _regs[I2c_target_address] = address & I2c_target_7bits; 389 enable(); 390 init_parameters(); 391 //printf("I2c_enable_status: %x\n", (uint32_t) _regs[I2c_enable_status]); 392 //printf("I2c_status: %x\n", (uint32_t) _regs[I2c_status]); 393 //printf("Int_mask: %x\n", (uint32_t) _regs[Int_mask]); 394 //printf("Int_status: %x\n", (uint32_t) _regs[Int_status]); 395 printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); 396 } 397 398 399 400 // Reset interrupt flags upon certain conditions. 401 402 void 403 I2c_x1600_channel::reset_flags() 404 { 405 volatile uint32_t r; 406 407 _regs[Int_mask] = 0; 408 409 // Read from the register to clear interrupts. 410 411 r = _regs[Int_combined_clear]; 412 (void) r; 413 } 414 415 // Initialise interrupt flags and queue thresholds for reading and writing. 416 417 void 418 I2c_x1600_channel::init_parameters() 419 { 420 // Handle read queue conditions for data, write queue conditions for commands. 421 422 reset_flags(); 423 424 _regs[Tx_fifo_thold] = 0; // write when 0 in queue 425 } 426 427 428 429 // Return whether the device is active. 430 431 int 432 I2c_x1600_channel::active() 433 { 434 return _regs[I2c_status] & I2c_status_master_act; 435 } 436 437 // Return whether data is available to receive. 438 439 int 440 I2c_x1600_channel::have_input() 441 { 442 return _regs[I2c_status] & I2c_status_rx_nempty; 443 } 444 445 // Return whether data is queued for sending. 446 447 int 448 I2c_x1600_channel::have_output() 449 { 450 return !(_regs[I2c_status] & I2c_status_tx_empty); 451 } 452 453 // Return whether data can be queued for sending. 454 455 int 456 I2c_x1600_channel::can_send() 457 { 458 return _regs[I2c_status] & I2c_status_tx_nfull; 459 } 460 461 // Return whether a receive operation has failed. 462 463 int 464 I2c_x1600_channel::read_failed() 465 { 466 return _regs[Int_status] & Int_rx_of; 467 } 468 469 // Return whether a send operation has failed. 470 471 int 472 I2c_x1600_channel::write_failed() 473 { 474 return _regs[Int_status] & Int_tx_abort; 475 } 476 477 int 478 I2c_x1600_channel::read_done() 479 { 480 return _pos == _total; 481 } 482 483 int 484 I2c_x1600_channel::write_done() 485 { 486 return _reqpos == _total; 487 } 488 489 unsigned 490 I2c_x1600_channel::have_read() 491 { 492 return _pos; 493 } 494 495 unsigned 496 I2c_x1600_channel::have_written() 497 { 498 return _reqpos; 499 } 500 501 int 502 I2c_x1600_channel::failed() 503 { 504 return _fail; 505 } 506 507 508 509 // Send read commands for empty queue entries. 510 511 void 512 I2c_x1600_channel::queue_reads() 513 { 514 unsigned int remaining = _total - _reqpos; 515 unsigned int queued = _reqpos - _pos; 516 unsigned int can_queue = I2c_fifo_limit - queued; 517 518 // Keep the number of reads in progress below the length of the read queue. 519 520 if (!can_queue) 521 return; 522 523 // At most, only queue as many reads as are remaining. 524 525 if (remaining < can_queue) 526 can_queue = remaining; 527 528 // Queue read requests for any remaining queue entries. 529 530 while (can_queue && can_send()) 531 { 532 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 533 printf("Queue read %d/%d %s\n", _reqpos, _total - 1, stop ? "stop" : "continue"); 534 535 _regs[I2c_data_command] = I2c_command_read | stop; 536 _reqpos++; 537 can_queue--; 538 } 539 540 // Update the threshold to be notified of any reduced remaining amount. 541 542 set_read_threshold(); 543 } 544 545 // Send write commands for empty queue entries. 546 547 void 548 I2c_x1600_channel::queue_writes() 549 { 550 unsigned int remaining = _total - _reqpos; 551 unsigned int can_queue = I2c_fifo_limit; 552 553 if (remaining < can_queue) 554 can_queue = remaining; 555 556 printf("queue_writes: %d %s\n", can_queue, can_send() ? "can send" : "cannot send"); 557 558 // Queue write requests for any remaining queue entries. 559 560 while (can_queue && can_send()) 561 { 562 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 563 printf("Queue write %d/%d %s\n", _reqpos, _total - 1, stop ? "stop" : "continue"); 564 565 _regs[I2c_data_command] = I2c_command_write | _buf[_reqpos] | stop; 566 _reqpos++; 567 can_queue--; 568 } 569 570 printf("Tx_fifo_count = %d\n", (uint32_t) _regs[Tx_fifo_count]); 571 } 572 573 // Store read command results from the queue. 574 575 void 576 I2c_x1600_channel::store_reads() 577 { 578 printf("store_reads: %s\n", have_input() ? "input" : "no input"); 579 580 // Read any input and store it in the buffer. 581 582 while (have_input() && (_pos < _reqpos)) 583 { 584 _buf[_pos] = _regs[I2c_data_command] & 0xff; 585 _pos++; 586 } 587 } 588 589 void 590 I2c_x1600_channel::set_read_threshold() 591 { 592 unsigned int queued = _reqpos - _pos; 593 594 if (!queued) 595 return; 596 597 // Read all expected. 598 599 _regs[Rx_fifo_thold] = queued - 1; 600 printf("Rx_fifo_thold = %d\n", (uint32_t) _regs[Rx_fifo_thold]); 601 } 602 603 // Read from the target device. 604 605 void 606 I2c_x1600_channel::start_read(uint8_t buf[], unsigned int total, int stop) 607 { 608 _buf = buf; 609 _total = total; 610 _pos = 0; 611 _reqpos = 0; 612 _fail = 0; 613 _stop = stop; 614 615 printf("start_read: %d\n", total); 616 617 _regs[Int_mask] = Int_rx_full | // read condition (reading needed) 618 Int_rx_of | // abort condition 619 Int_tx_abort; // abort condition 620 621 // Perform initial read requests. 622 623 read(); 624 } 625 626 void 627 I2c_x1600_channel::read() 628 { 629 printf("Rx_fifo_count = %d\n", (uint32_t) _regs[Rx_fifo_count]); 630 printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); 631 printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]); 632 633 if (read_failed() || write_failed()) 634 { 635 _fail = 1; 636 _regs[Int_mask] = 0; 637 return; 638 } 639 640 if (_regs[Int_status] & Int_rx_full) 641 store_reads(); 642 643 // Always attempt to queue more read requests. 644 645 queue_reads(); 646 } 647 648 // Write to the target device. 649 650 void 651 I2c_x1600_channel::start_write(uint8_t buf[], unsigned int total, int stop) 652 { 653 _buf = buf; 654 _total = total; 655 _reqpos = 0; 656 _fail = 0; 657 _stop = stop; 658 659 printf("start_write: %d\n", total); 660 661 // Enable interrupts for further writes. 662 663 _regs[Int_mask] = Int_tx_empty | // write condition (writing needed) 664 Int_tx_abort; // abort condition 665 666 // Perform initial writes. 667 668 write(); 669 } 670 671 void 672 I2c_x1600_channel::write() 673 { 674 printf("Tx_fifo_count = %d\n", (uint32_t) _regs[Tx_fifo_count]); 675 printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); 676 printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]); 677 678 if (write_failed()) 679 { 680 _fail = 1; 681 _regs[Int_mask] = 0; 682 return; 683 } 684 685 if (_regs[Int_status] & Int_tx_empty) 686 queue_writes(); 687 } 688 689 // Explicitly stop communication. 690 691 void 692 I2c_x1600_channel::stop() 693 { 694 } 695 696 697 698 // Initialise the I2C controller. 699 700 I2c_x1600_chip::I2c_x1600_chip(l4_addr_t start, l4_addr_t end, 701 Cpm_x1600_chip *cpm, 702 uint32_t frequency) 703 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 704 { 705 } 706 707 // Obtain a channel object. 708 709 I2c_x1600_channel * 710 I2c_x1600_chip::get_channel(uint8_t channel) 711 { 712 l4_addr_t block = _start + channel * I2c_block_offset; 713 enum Clock_identifiers bits[] = {Clock_i2c0, Clock_i2c1}; 714 715 if (channel < 2) 716 { 717 _cpm->start_clock(bits[channel]); 718 return new I2c_x1600_channel(block, _cpm, _frequency); 719 } 720 else 721 throw -L4_EINVAL; 722 } 723 724 725 726 // C language interface functions. 727 728 void *x1600_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 729 { 730 return (void *) new I2c_x1600_chip(start, end, static_cast<Cpm_x1600_chip *>(cpm), frequency); 731 } 732 733 void x1600_i2c_disable(void *i2c_channel) 734 { 735 static_cast<I2c_x1600_channel *>(i2c_channel)->disable(); 736 } 737 738 void *x1600_i2c_get_channel(void *i2c, uint8_t channel) 739 { 740 return static_cast<I2c_x1600_chip *>(i2c)->get_channel(channel); 741 } 742 743 uint32_t x1600_i2c_get_frequency(void *i2c_channel) 744 { 745 return static_cast<I2c_x1600_channel *>(i2c_channel)->get_frequency(); 746 } 747 748 void x1600_i2c_set_target(void *i2c_channel, uint8_t addr) 749 { 750 static_cast<I2c_x1600_channel *>(i2c_channel)->set_target(addr); 751 } 752 753 void x1600_i2c_start_read(void *i2c_channel, uint8_t buf[], unsigned int total, 754 int stop) 755 { 756 static_cast<I2c_x1600_channel *>(i2c_channel)->start_read(buf, total, stop); 757 } 758 759 void x1600_i2c_read(void *i2c_channel) 760 { 761 static_cast<I2c_x1600_channel *>(i2c_channel)->read(); 762 } 763 764 void x1600_i2c_start_write(void *i2c_channel, uint8_t buf[], unsigned int total, 765 int stop) 766 { 767 static_cast<I2c_x1600_channel *>(i2c_channel)->start_write(buf, total, stop); 768 } 769 770 void x1600_i2c_write(void *i2c_channel) 771 { 772 static_cast<I2c_x1600_channel *>(i2c_channel)->write(); 773 } 774 775 int x1600_i2c_read_done(void *i2c_channel) 776 { 777 return static_cast<I2c_x1600_channel *>(i2c_channel)->read_done(); 778 } 779 780 int x1600_i2c_write_done(void *i2c_channel) 781 { 782 return static_cast<I2c_x1600_channel *>(i2c_channel)->write_done(); 783 } 784 785 unsigned int x1600_i2c_have_read(void *i2c_channel) 786 { 787 return static_cast<I2c_x1600_channel *>(i2c_channel)->have_read(); 788 } 789 790 unsigned int x1600_i2c_have_written(void *i2c_channel) 791 { 792 return static_cast<I2c_x1600_channel *>(i2c_channel)->have_written(); 793 } 794 795 int x1600_i2c_failed(void *i2c_channel) 796 { 797 return static_cast<I2c_x1600_channel *>(i2c_channel)->failed(); 798 } 799 800 void x1600_i2c_stop(void *i2c_channel) 801 { 802 static_cast<I2c_x1600_channel *>(i2c_channel)->stop(); 803 }