1 /* 2 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 17 * Boston, MA 02110-1301, USA 18 */ 19 20 #include <l4/devices/i2c-jz4780.h> 21 #include <l4/devices/hw_mmio_register_block.h> 22 23 #include <l4/sys/icu.h> 24 #include <l4/util/util.h> 25 #include <sys/time.h> 26 27 #include <cstdio> 28 29 /* 30 I2C pins: 31 32 I2C0: PD30/SMB0_SDA, PD31/SMB0_SCK 33 I2C1: PD30/SMB1_SDA, PD31/SMB1_SCK (pulled up on CI20) 34 I2C2: PF16/SMB2_SDA, PF17/SMB2_SCK 35 PWM: PD10/SMB3_SDA, PD11/SMB3_SCK 36 PWM: PE3/SMB4_SDA, PE4/SMB4_SCK 37 I2C4: PE12/SMB4_SDA, PE13/SMB4_SCK 38 HDMI: PF25/SMB4_SDA/DDCSDA, PF24/SMB4_SCK/DDCSCK 39 40 See: http://mipscreator.imgtec.com/CI20/hardware/board/ci20_jz4780_v2.0.pdf 41 */ 42 43 enum Regs 44 { 45 Smb_control = 0x000, // SMBCON 46 Smb_target_address = 0x004, // SMBTAR 47 Smb_slave_address = 0x008, // SMBSAR 48 Smb_data_command = 0x010, // SMBDC 49 Std_high_count = 0x014, // SMBSHCNT 50 Std_low_count = 0x018, // SMBSLCNT 51 Fast_high_count = 0x01c, // SMBFHCNT 52 Fast_low_count = 0x020, // SMBFLCNT 53 Int_status = 0x02c, // SMBINTST (read-only) 54 Int_mask = 0x030, // SMBINTM 55 56 Rx_fifo_thold = 0x038, // SMBRXTL 57 Tx_fifo_thold = 0x03c, // SMBTXTL 58 Int_combined_clear = 0x040, // SMBCINT (read-only) 59 Int_rx_uf_clear = 0x044, // SMBCRXUF (read-only) 60 Int_rx_of_clear = 0x048, // SMBCRXOF (read-only) 61 Int_tx_of_clear = 0x04c, // SMBCTXOF (read-only) 62 Int_rd_req_clear = 0x050, // SMBCRXREQ (read-only) 63 Int_tx_abort_clear = 0x054, // SMBCTXABT (read-only) 64 Int_rx_done_clear = 0x058, // SMBCRXDN (read-only) 65 Int_activity_clear = 0x05c, // SMBCACT (read-only) 66 Int_stop_clear = 0x060, // SMBCSTP (read-only) 67 Int_start_clear = 0x064, // SMBCSTT (read-only) 68 Int_call_clear = 0x068, // SMBCGC (read-only) 69 Smb_enable = 0x06c, // SMBENB 70 Smb_status = 0x070, // SMBST (read-only) 71 72 Tx_fifo_count = 0x074, // SMBTXFLR (read-only) 73 Rx_fifo_count = 0x078, // SMBRXFLR (read-only) 74 75 Trans_abort_status0 = 0x080, // SMBABTSRC (read-only) 76 Trans_abort_status1 = 0x084, // ... (read-only) 77 78 Smb_dma_ctrl = 0x088, // SMBDMACR 79 Smb_trans_data_lvl = 0x08c, // SMBDMATDLR 80 Smb_recv_data_lvl = 0x090, // SMBDMARDLR 81 Smb_sda_setup_time = 0x094, // SMBSDASU 82 Smb_ack_call = 0x098, // SMBACKGC 83 84 Smb_enable_status = 0x09c, // SMBENBST (read-only) 85 Smb_sda_hold_time = 0x0d0, // SMBSDAHD 86 87 Smb_block_offset = 0x1000 88 }; 89 90 enum Smb_control_bits : unsigned 91 { 92 Smb_no_stop_empty = 0x80, // STPHLD (no STP condition when queue empty) 93 Smb_disable_slave = 0x40, // SLVDIS (slave disabled) 94 Smb_enable_restart = 0x20, // REST 95 Smb_enable_master = 0x01, // MD (master enabled) 96 Smb_speed_bit = 1, // SPD 97 }; 98 99 enum Smb_enable_bits : unsigned 100 { 101 Smb_enable_enabled = 0x01, // SMBEN 102 }; 103 104 enum Smb_status_bits : unsigned 105 { 106 Smb_status_master_act = 0x20, // MSTACT (master active) 107 Smb_status_rx_nempty = 0x08, // RFNE (read queue not empty) 108 Smb_status_tx_empty = 0x04, // TFE (write queue empty) 109 Smb_status_tx_nfull = 0x02, // TFNF (write queue not full) 110 Smb_status_active = 0x01, // ACT (device active as master or slave) 111 }; 112 113 enum Smb_target_bits : unsigned 114 { 115 Smb_target_7bits = 0x7f, 116 }; 117 118 enum Smb_hold_control_bits : unsigned 119 { 120 Smb_hold_enable = 0x100, // HDENB 121 Smb_hold_disable = 0x000, // HDENB 122 Smb_hold_mask = 0x1ff, 123 }; 124 125 enum Smb_setup_control_bits : unsigned 126 { 127 Smb_setup_mask = 0x0ff, 128 }; 129 130 enum Smb_command_bits : unsigned 131 { 132 Smb_command_read = 0x100, // CMD 133 Smb_command_write = 0x000, // CMD 134 }; 135 136 enum Smb_fifo_bits : unsigned 137 { 138 Smb_fifo_limit = 16, 139 }; 140 141 enum Int_bits : unsigned 142 { 143 Int_call = 0x800, // IGC (general call received) 144 Int_start = 0x400, // ISTT (start/restart condition occurred) 145 Int_stop = 0x200, // ISTP (stop condition occurred) 146 Int_activity = 0x100, // IACT (bus activity interrupt) 147 Int_rx_done = 0x080, // RXDN (read from master device done) 148 Int_tx_abort = 0x040, // TXABT (transmit abort) 149 Int_rd_req = 0x020, // RDREQ (read request from master device) 150 Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) 151 Int_tx_of = 0x008, // TXOF (overflow when writing to queue) 152 Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) 153 Int_rx_of = 0x002, // RXOF (overflow from device) 154 Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) 155 }; 156 157 158 159 // Initialise a channel. 160 161 I2c_jz4780_channel::I2c_jz4780_channel(l4_addr_t start, 162 Cpm_jz4780_chip *cpm, 163 uint32_t frequency) 164 : _cpm(cpm), _frequency(frequency) 165 { 166 _regs = new Hw::Mmio_register_block<32>(start); 167 } 168 169 // Enable the channel. 170 171 void 172 I2c_jz4780_channel::enable() 173 { 174 _regs[Smb_enable] = Smb_enable_enabled; 175 while (!(_regs[Smb_enable_status] & Smb_enable_enabled)); 176 } 177 178 // Disable the channel. 179 180 void 181 I2c_jz4780_channel::disable() 182 { 183 _regs[Smb_enable] = 0; 184 while (_regs[Smb_enable_status] & Smb_enable_enabled); 185 } 186 187 // Set the frequency-related peripheral parameters. 188 189 void 190 I2c_jz4780_channel::set_frequency() 191 { 192 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 193 // obtained from the CPM unit. It is known as SMB_CLK here and is scaled to 194 // kHz in order to keep the numbers easily representable, as is the bus 195 // frequency. 196 197 uint32_t smb_clk = _cpm->get_pclock_frequency() / 1000; 198 uint32_t i2c_clk = _frequency / 1000; 199 unsigned int speed = (i2c_clk <= 100) ? 1 : 2; 200 201 _regs[Smb_control] = _regs[Smb_control] | (speed << Smb_speed_bit) | 202 Smb_disable_slave | 203 Smb_enable_restart | 204 Smb_enable_master; 205 206 // According to the programming manual, if the PCLK period is T{SMB_CLK} 207 // then the I2C clock period is... 208 209 // T{SCL} = T{SCL_high} + T{SCL_low} 210 211 // Where... 212 213 // T{SCL_low} = T{SMB_CLK} * (#cycles for low signal) 214 // T{SCL_high} = T{SMB_CLK} * (#cycles for high signal) 215 216 // Since, with minimum periods being defined... 217 218 // T{SCL} >= T{min_SCL} 219 // T{SCL_low} >= T{min_SCL_low} 220 // T{SCL_high} >= T{min_SCL_high} 221 // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} 222 223 // Then the following applies... 224 225 // T{SMB_CLK} * (#cycles for low signal)) >= T{min_SCL_low} 226 // T{SMB_CLK} * (#cycles for high signal) >= T{min_SCL_high} 227 228 // To work with different clock speeds while maintaining the low-to-high 229 // ratios: 230 231 // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} 232 // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) 233 234 // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} 235 // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) 236 237 // Constraints are given with respect to the high and low count registers. 238 239 // #cycles for high signal = SMBxHCNT + 8 240 // #cycles for low signal = SMBxLCNT + 1 241 242 // From earlier, this yields... 243 244 // T{SMB_CLK} * (SMBxLCNT + 1) >= T{min_SCL_low} 245 // T{SMB_CLK} * (SMBxHCNT + 8) >= T{min_SCL_high} 246 247 // Rearranging... 248 249 // SMBxLCNT >= (T{min_SCL_low} / T{SMB_CLK}) - 1 250 // >= T{min_SCL_low} * SMB_CLK - 1 251 252 // SMBxHCNT >= (T{min_SCL_high} / T{SMB_CLK}) - 8 253 // >= T{min_SCL_high} * SMB_CLK - 8 254 255 // Introducing the definitions for the high and low periods... 256 257 // SMBxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * SMB_CLK - 1 258 // >= (T{min_SCL_low} / T{min_SCL}) * SMB_CLK / I2C_CLK - 1 259 260 // SMBxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * SMB_CLK - 8 261 // >= (T{min_SCL_high} / T{min_SCL}) * SMB_CLK / I2C_CLK - 8 262 263 uint32_t high_reg, low_reg; 264 uint32_t high_count, low_count; 265 int32_t hold_count; 266 uint32_t setup_count; 267 268 // Level hold times: 269 270 // Standard Fast 271 // SCL low 4.7us 1.3us 272 // SCL high 4.0us 0.6us + 273 // SCL period 8.7us 1.9us = 274 275 if (i2c_clk <= 100) // 100 kHz 276 { 277 low_count = (smb_clk * 47) / (i2c_clk * 87) - 1; 278 high_count = (smb_clk * 40) / (i2c_clk * 87) - 8; 279 low_reg = Std_low_count; 280 high_reg = Std_high_count; 281 } 282 else 283 { 284 low_count = (smb_clk * 13) / (i2c_clk * 19) - 1; 285 high_count = (smb_clk * 6) / (i2c_clk * 19) - 8; 286 low_reg = Fast_low_count; 287 high_reg = Fast_high_count; 288 } 289 290 // Minimum counts are 8 and 6 for low and high respectively. 291 292 _regs[low_reg] = low_count < 8 ? 8 : low_count; 293 _regs[high_reg] = high_count < 6 ? 6 : high_count; 294 295 // Data hold and setup times: 296 297 // Standard Fast 298 // t{HD;DAT} 300ns 300ns 299 // t{SU;DAT} 250ns 100ns 300 301 // T{delay} = (SMBSDAHD + 1) * T{SMB_CLK} 302 // SMBSDAHD = T{delay} / T{SMB_CLK} - 1 303 // SMBSDAHD = SMB_CLK * T{delay} - 1 304 305 hold_count = (smb_clk * 300) / 1000000 - 1; 306 307 _regs[Smb_sda_hold_time] = (_regs[Smb_sda_hold_time] & ~Smb_hold_mask) | 308 (hold_count >= 0 ? Smb_hold_enable : Smb_hold_disable) | 309 (hold_count < 0 ? 0 : hold_count < 255 ? hold_count : 255); 310 311 // T{delay} = (SMBSDASU - 1) * T{SMB_CLK} 312 // SMBSDASU = T{delay} / T{SMB_CLK} + 1 313 // SMBSDASU = SMB_CLK * T{delay} + 1 314 315 if (i2c_clk <= 100) 316 setup_count = (smb_clk * 250) / 1000000 + 1; 317 else 318 setup_count = (smb_clk * 100) / 1000000 + 1; 319 320 _regs[Smb_sda_setup_time] = (_regs[Smb_sda_setup_time] & ~Smb_setup_mask) | 321 (setup_count < 255 ? setup_count : 255); 322 } 323 324 // Set the target address and enable transfer. 325 // NOTE: Only supporting 7-bit addresses currently. 326 327 void 328 I2c_jz4780_channel::set_target(uint8_t address) 329 { 330 disable(); 331 set_frequency(); 332 _regs[Smb_target_address] = address & Smb_target_7bits; 333 enable(); 334 init_parameters(); 335 } 336 337 338 339 // Reset interrupt flags upon certain conditions. 340 341 void 342 I2c_jz4780_channel::reset_flags() 343 { 344 volatile uint32_t r; 345 346 _regs[Int_mask] = 0; 347 348 // Read from the register to clear interrupts. 349 350 r = _regs[Int_combined_clear]; 351 (void) r; 352 } 353 354 // Initialise interrupt flags and queue thresholds for reading and writing. 355 356 void 357 I2c_jz4780_channel::init_parameters() 358 { 359 // Handle read queue conditions for data, write queue conditions for commands. 360 361 reset_flags(); 362 363 _regs[Int_mask] = Int_rx_full | // read condition (reading needed) 364 Int_rx_of | // abort condition 365 Int_tx_empty | // write condition (writing needed) 366 Int_tx_abort; // abort condition 367 368 _regs[Tx_fifo_thold] = 0; // write when 0 in queue 369 370 // Make sure that the stop condition does not occur automatically. 371 372 _regs[Smb_control] = _regs[Smb_control] | Smb_no_stop_empty; 373 } 374 375 376 377 // Return whether the device is active. 378 379 int 380 I2c_jz4780_channel::active() 381 { 382 return _regs[Smb_status] & Smb_status_master_act; 383 } 384 385 // Return whether data is available to receive. 386 387 int 388 I2c_jz4780_channel::have_input() 389 { 390 return _regs[Smb_status] & Smb_status_rx_nempty; 391 } 392 393 // Return whether data is queued for sending. 394 395 int 396 I2c_jz4780_channel::have_output() 397 { 398 return !(_regs[Smb_status] & Smb_status_tx_empty); 399 } 400 401 // Return whether data can be queued for sending. 402 403 int 404 I2c_jz4780_channel::can_send() 405 { 406 return _regs[Smb_status] & Smb_status_tx_nfull; 407 } 408 409 // Return whether a receive operation has failed. 410 411 int 412 I2c_jz4780_channel::read_failed() 413 { 414 return _regs[Int_status] & Int_rx_of; 415 } 416 417 // Return whether a send operation has failed. 418 419 int 420 I2c_jz4780_channel::write_failed() 421 { 422 return _regs[Int_status] & Int_tx_abort; 423 } 424 425 int 426 I2c_jz4780_channel::read_done() 427 { 428 return _pos == _total; 429 } 430 431 int 432 I2c_jz4780_channel::write_done() 433 { 434 return _reqpos == _total; 435 } 436 437 unsigned 438 I2c_jz4780_channel::have_read() 439 { 440 return _pos; 441 } 442 443 unsigned 444 I2c_jz4780_channel::have_written() 445 { 446 return _reqpos; 447 } 448 449 int 450 I2c_jz4780_channel::failed() 451 { 452 return _fail; 453 } 454 455 456 457 // Send read commands for empty queue entries. 458 459 void 460 I2c_jz4780_channel::queue_reads() 461 { 462 unsigned int remaining = _total - _reqpos; 463 unsigned int queued = _reqpos - _pos; 464 465 // Permit one more issued read request due to the behaviour of the peripheral 466 // to withhold a request unless the stop condition has been issued. 467 468 unsigned int can_queue = Smb_fifo_limit - queued + 1; 469 470 // Keep the number of reads in progress below the length of the read queue. 471 472 if (!can_queue) 473 return; 474 475 // At most, only queue as many reads as are remaining. 476 477 if (remaining < can_queue) 478 can_queue = remaining; 479 480 // Queue read requests for any remaining queue entries. 481 482 while (can_queue && can_send()) 483 { 484 _regs[Smb_data_command] = Smb_command_read; 485 _reqpos++; 486 can_queue--; 487 } 488 489 // Issue the stop condition after the final read request. 490 // In practice, an extra read request works better since it does not risk a 491 // transmission abort condition and would permit following transactions. 492 // However, it does risk causing an address autoincrement with some devices. 493 494 if (_total == _reqpos) 495 _regs[Smb_data_command] = Smb_command_read; 496 //stop(); 497 498 // Update the threshold to be notified of any reduced remaining amount. 499 500 set_read_threshold(); 501 } 502 503 // Send write commands for empty queue entries. 504 505 void 506 I2c_jz4780_channel::queue_writes() 507 { 508 unsigned int remaining = _total - _reqpos; 509 unsigned int can_queue = Smb_fifo_limit; 510 511 if (remaining < can_queue) 512 can_queue = remaining; 513 514 // Queue write requests for any remaining queue entries. 515 516 while (can_queue && can_send()) 517 { 518 _regs[Smb_data_command] = Smb_command_write | _buf[_reqpos]; 519 _reqpos++; 520 can_queue--; 521 } 522 } 523 524 // Store read command results from the queue. 525 526 void 527 I2c_jz4780_channel::store_reads() 528 { 529 // Read any input and store it in the buffer. 530 531 while (have_input() && (_pos < _reqpos)) 532 { 533 _buf[_pos] = _regs[Smb_data_command] & 0xff; 534 _pos++; 535 } 536 } 537 538 void 539 I2c_jz4780_channel::set_read_threshold() 540 { 541 unsigned int queued = _reqpos - _pos; 542 543 if (!queued) 544 return; 545 546 // Read all expected. 547 548 _regs[Rx_fifo_thold] = queued - 1; 549 } 550 551 // Read from the target device. 552 553 void 554 I2c_jz4780_channel::start_read(uint8_t buf[], unsigned int total) 555 { 556 _buf = buf; 557 _total = total; 558 _pos = 0; 559 _reqpos = 0; 560 _fail = 0; 561 562 set_read_threshold(); 563 } 564 565 void 566 I2c_jz4780_channel::read() 567 { 568 if (read_failed() || write_failed()) 569 { 570 _fail = 1; 571 return; 572 } 573 574 if (_regs[Int_status] & Int_rx_full) 575 store_reads(); 576 if (_regs[Int_status] & Int_tx_empty) 577 queue_reads(); 578 } 579 580 // Write to the target device. 581 582 void 583 I2c_jz4780_channel::start_write(uint8_t buf[], unsigned int total) 584 { 585 _buf = buf; 586 _total = total; 587 _reqpos = 0; 588 _fail = 0; 589 } 590 591 void 592 I2c_jz4780_channel::write() 593 { 594 if (write_failed()) 595 { 596 _fail = 1; 597 return; 598 } 599 600 if (_regs[Int_status] & Int_tx_empty) 601 queue_writes(); 602 } 603 604 // Explicitly stop communication. 605 606 void 607 I2c_jz4780_channel::stop() 608 { 609 _regs[Smb_control] = _regs[Smb_control] & ~Smb_no_stop_empty; 610 } 611 612 613 614 // Initialise the I2C controller. 615 616 I2c_jz4780_chip::I2c_jz4780_chip(l4_addr_t start, l4_addr_t end, 617 Cpm_jz4780_chip *cpm, 618 uint32_t frequency) 619 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 620 { 621 } 622 623 // Obtain a channel object. 624 625 I2c_jz4780_channel * 626 I2c_jz4780_chip::get_channel(uint8_t channel) 627 { 628 l4_addr_t block = _start + channel * Smb_block_offset; 629 630 if (block < _end) 631 { 632 _cpm->start_i2c(channel); 633 return new I2c_jz4780_channel(block, _cpm, _frequency); 634 } 635 else 636 throw -L4_EINVAL; 637 } 638 639 640 641 // C language interface functions. 642 643 void *jz4780_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 644 { 645 return (void *) new I2c_jz4780_chip(start, end, static_cast<Cpm_jz4780_chip *>(cpm), frequency); 646 } 647 648 void jz4780_i2c_disable(void *i2c_channel) 649 { 650 static_cast<I2c_jz4780_channel *>(i2c_channel)->disable(); 651 } 652 653 void *jz4780_i2c_get_channel(void *i2c, uint8_t channel) 654 { 655 return static_cast<I2c_jz4780_chip *>(i2c)->get_channel(channel); 656 } 657 658 void jz4780_i2c_set_target(void *i2c_channel, uint8_t addr) 659 { 660 static_cast<I2c_jz4780_channel *>(i2c_channel)->set_target(addr); 661 } 662 663 void jz4780_i2c_start_read(void *i2c_channel, uint8_t buf[], unsigned int total) 664 { 665 static_cast<I2c_jz4780_channel *>(i2c_channel)->start_read(buf, total); 666 } 667 668 void jz4780_i2c_read(void *i2c_channel) 669 { 670 static_cast<I2c_jz4780_channel *>(i2c_channel)->read(); 671 } 672 673 void jz4780_i2c_start_write(void *i2c_channel, uint8_t buf[], unsigned int total) 674 { 675 static_cast<I2c_jz4780_channel *>(i2c_channel)->start_write(buf, total); 676 } 677 678 void jz4780_i2c_write(void *i2c_channel) 679 { 680 static_cast<I2c_jz4780_channel *>(i2c_channel)->write(); 681 } 682 683 int jz4780_i2c_read_done(void *i2c_channel) 684 { 685 return static_cast<I2c_jz4780_channel *>(i2c_channel)->read_done(); 686 } 687 688 int jz4780_i2c_write_done(void *i2c_channel) 689 { 690 return static_cast<I2c_jz4780_channel *>(i2c_channel)->write_done(); 691 } 692 693 unsigned int jz4780_i2c_have_read(void *i2c_channel) 694 { 695 return static_cast<I2c_jz4780_channel *>(i2c_channel)->have_read(); 696 } 697 698 unsigned int jz4780_i2c_have_written(void *i2c_channel) 699 { 700 return static_cast<I2c_jz4780_channel *>(i2c_channel)->have_written(); 701 } 702 703 int jz4780_i2c_failed(void *i2c_channel) 704 { 705 return static_cast<I2c_jz4780_channel *>(i2c_channel)->failed(); 706 } 707 708 void jz4780_i2c_stop(void *i2c_channel) 709 { 710 static_cast<I2c_jz4780_channel *>(i2c_channel)->stop(); 711 }