1 /* 2 * DMA support for the JZ4780. 3 * NOTE: This should be combined with the X1600 support. 4 * 5 * Copyright (C) 2021, 2023, 2024 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 */ 22 23 #include <l4/devices/cpm-jz4780.h> 24 #include <l4/devices/dma-jz4780.h> 25 #include <l4/devices/hw_mmio_register_block.h> 26 27 #include <l4/sys/cache.h> 28 #include <l4/sys/ipc.h> 29 #include <l4/sys/irq.h> 30 #include <l4/sys/rcv_endpoint.h> 31 #include <l4/util/util.h> 32 33 #include <systypes/thread.h> 34 35 #include <stdio.h> 36 37 38 39 enum Global_regs 40 { 41 Dma_control = 0x1000, // DMAC 42 Dma_irq_pending = 0x1004, // DIRQP 43 Dma_doorbell = 0x1008, // DDB 44 Dma_doorbell_set = 0x100c, // DDS 45 Dma_channel_programmable = 0x101c, // DMACP 46 Dma_soft_irq_pending = 0x1020, // DSIRQP 47 Dma_soft_irq_mask = 0x1024, // DSIRQM 48 Dma_mcu_irq_pending = 0x1028, // DCIRQP 49 Dma_mcu_irq_mask = 0x102c, // DCIRQM 50 }; 51 52 enum Channel_regs 53 { 54 Dma_source = 0x00, // DSA 55 Dma_destination = 0x04, // DTA 56 Dma_transfer_count = 0x08, // DTC 57 Dma_request_source = 0x0c, // DRT 58 Dma_control_status = 0x10, // DCS 59 Dma_command = 0x14, // DCM 60 Dma_descriptor_address = 0x18, // DDA 61 Dma_stride = 0x1c, // DSD 62 }; 63 64 enum Dma_control_bits : unsigned 65 { 66 Dma_fast_msc_transfer = 0x80000000, // FMSC 67 Dma_fast_ssi_transfer = 0x40000000, // FSSI 68 Dma_fast_tssi_transfer = 0x20000000, // FTSSI 69 Dma_fast_uart_transfer = 0x10000000, // FUART 70 Dma_fast_aic_transfer = 0x08000000, // FAIC 71 72 Dma_intc_irq_channel_mask = 0x003e0000, // INTCC 73 Dma_intc_irq_channel_bind = 0x00010000, // INTCE 74 75 Dma_control_trans_halted = 0x00000008, // HLT 76 Dma_control_address_error = 0x00000004, // AR 77 Dma_control_special_ch01 = 0x00000002, // CH01 78 Dma_control_enable = 0x00000001, // DMAE 79 }; 80 81 enum Dma_transfer_count_bits : unsigned 82 { 83 Dma_descriptor_offset_mask = 0xff000000, // DOA (in DES3) 84 Dma_transfer_count_mask = 0x00ffffff, 85 86 Dma_descriptor_offset_shift = 24, 87 }; 88 89 enum Dma_request_source_bits : unsigned 90 { 91 Dma_request_type_mask = 0x0000003f, 92 }; 93 94 enum Dma_control_status_bits : unsigned 95 { 96 Dma_no_descriptor_transfer = 0x80000000, 97 Dma_8word_descriptor = 0x40000000, 98 Dma_4word_descriptor = 0x00000000, 99 Dma_copy_offset_mask = 0x0000ff00, 100 Dma_address_error = 0x00000010, 101 Dma_trans_completed = 0x00000008, 102 Dma_trans_halted = 0x00000004, 103 Dma_channel_enable = 0x00000001, 104 105 Dma_copy_offset_shift = 8, 106 }; 107 108 enum Dma_command_bits : unsigned 109 { 110 Dma_special_source_mask = 0x0c000000, 111 Dma_special_source_tcsm = 0x00000000, 112 Dma_special_source_bch_nemc = 0x04000000, 113 Dma_special_source_reserved_ddr = 0x08000000, 114 115 Dma_special_destination_mask = 0x03000000, 116 Dma_special_destination_tcsm = 0x00000000, 117 Dma_special_destination_bch_nemc = 0x01000000, 118 Dma_special_destination_reserved_ddr = 0x02000000, 119 120 Dma_source_address_increment = 0x00800000, 121 Dma_source_address_no_increment = 0x00000000, 122 Dma_destination_address_increment = 0x00400000, 123 Dma_destination_address_no_increment = 0x00000000, 124 125 Dma_recommended_data_unit_size_mask = 0x000f0000, 126 Dma_source_port_width_mask = 0x0000c000, 127 Dma_destination_port_width_mask = 0x00003000, 128 Dma_transfer_unit_size_mask = 0x00000f00, 129 130 Dma_trans_unit_size_32_bit = 0x00000000, 131 Dma_trans_unit_size_8_bit = 0x00000100, 132 Dma_trans_unit_size_16_bit = 0x00000200, 133 Dma_trans_unit_size_16_byte = 0x00000300, 134 Dma_trans_unit_size_32_byte = 0x00000400, 135 Dma_trans_unit_size_64_byte = 0x00000500, 136 Dma_trans_unit_size_128_byte = 0x00000600, 137 Dma_trans_unit_size_autonomous = 0x00000700, 138 139 Dma_stride_enable = 0x00000004, 140 Dma_transfer_irq_enable = 0x00000002, 141 Dma_descriptor_link_enable = 0x00000001, 142 143 Dma_recommended_data_unit_size_shift = 16, 144 Dma_source_port_width_shift = 14, 145 Dma_destination_port_width_shift = 12, 146 Dma_transfer_unit_size_shift = 8, 147 }; 148 149 enum Dma_port_width_values : unsigned 150 { 151 Dma_port_width_32_bit = 0, 152 Dma_port_width_8_bit = 1, 153 Dma_port_width_16_bit = 2, 154 }; 155 156 157 158 // Initialise a channel. 159 160 Dma_jz4780_channel::Dma_jz4780_channel(Dma_chip *chip, uint8_t channel, 161 l4_addr_t start, l4_cap_idx_t irq) 162 : _chip(chip), _channel(channel), _irq(irq) 163 { 164 _regs = new Hw::Mmio_register_block<32>(start); 165 166 // Initialise the transfer count. 167 168 _regs[Dma_transfer_count] = 0; 169 } 170 171 // Return the closest interval length greater than or equal to the number of 172 // units given encoded in the request detection interval length field of the 173 // control/status register. 174 175 uint32_t 176 Dma_jz4780_channel::encode_req_detect_int_length(uint8_t units) 177 { 178 static uint8_t lengths[] = {0, 1, 2, 3, 4, 8, 16, 32, 64, 128}; 179 int i; 180 181 if (!units) 182 return 0; 183 184 for (i = 0; i <= 9; i++) 185 { 186 if (lengths[i] >= units) 187 break; 188 } 189 190 return i << Dma_recommended_data_unit_size_shift; 191 } 192 193 // Encode the appropriate source port width for the given request type. 194 195 uint32_t 196 Dma_jz4780_channel::encode_source_port_width(uint8_t width) 197 { 198 switch (width) 199 { 200 case 1: 201 return Dma_port_width_8_bit << Dma_source_port_width_shift; 202 203 case 2: 204 return Dma_port_width_16_bit << Dma_source_port_width_shift; 205 206 default: 207 return Dma_port_width_32_bit << Dma_source_port_width_shift; 208 } 209 } 210 211 // Encode the appropriate destination port width for the given request type. 212 213 uint32_t 214 Dma_jz4780_channel::encode_destination_port_width(uint8_t width) 215 { 216 switch (width) 217 { 218 case 1: 219 return Dma_port_width_8_bit << Dma_destination_port_width_shift; 220 221 case 2: 222 return Dma_port_width_16_bit << Dma_destination_port_width_shift; 223 224 default: 225 return Dma_port_width_32_bit << Dma_destination_port_width_shift; 226 } 227 } 228 229 // Encode the transfer unit size. 230 // NOTE: This does not handle the external case. 231 232 uint32_t 233 Dma_jz4780_channel::encode_transfer_unit_size(uint8_t size) 234 { 235 switch (size) 236 { 237 case 0: 238 return Dma_trans_unit_size_autonomous; 239 240 case 1: 241 return Dma_trans_unit_size_8_bit; 242 243 case 2: 244 return Dma_trans_unit_size_16_bit; 245 246 case 16: 247 return Dma_trans_unit_size_16_byte; 248 249 case 32: 250 return Dma_trans_unit_size_32_byte; 251 252 case 64: 253 return Dma_trans_unit_size_64_byte; 254 255 case 128: 256 return Dma_trans_unit_size_128_byte; 257 258 default: 259 return Dma_trans_unit_size_32_bit; 260 } 261 } 262 263 // Transfer data between memory locations. 264 265 unsigned int 266 Dma_jz4780_channel::transfer(uint32_t source, uint32_t destination, 267 unsigned int count, 268 bool source_increment, bool destination_increment, 269 uint8_t source_width, uint8_t destination_width, 270 uint8_t transfer_unit_size, 271 int type, 272 l4_addr_t desc_vaddr, 273 l4re_dma_space_dma_addr_t desc_paddr) 274 { 275 printf("transfer:%s%s%s%s\n", error() ? " error" : "", 276 halted() ? " halted" : "", 277 completed() ? " completed" : "", 278 _regs[Dma_transfer_count] ? " count" : ""); 279 280 // Ensure an absence of address error and halt conditions globally and in this channel. 281 282 if (error() || halted()) 283 return 0; 284 285 // Ensure a zero transfer count for this channel. 286 287 if (_regs[Dma_transfer_count]) 288 return 0; 289 290 // Disable the channel. 291 292 _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_channel_enable; 293 294 // Set transfer count to the number of units. 295 296 unsigned int units = count < Dma_transfer_count_mask ? count : Dma_transfer_count_mask; 297 298 // NOTE: Request detection interval length (for autonomous mode) not considered. 299 300 uint32_t command = (source_increment ? Dma_source_address_increment : 301 Dma_source_address_no_increment) | 302 (destination_increment ? Dma_destination_address_increment : 303 Dma_destination_address_no_increment) | 304 encode_source_port_width(source_width) | 305 encode_destination_port_width(destination_width) | 306 encode_transfer_unit_size(transfer_unit_size) | 307 Dma_transfer_irq_enable; 308 309 // Populate the descriptor, largely corresponding to the population of 310 // registers when descriptors are not being used. 311 312 if (desc_vaddr) 313 { 314 struct jz4780_dma_descriptor *desc = (struct jz4780_dma_descriptor *) desc_vaddr; 315 316 // NOTE: Linking to the same descriptor. 317 318 uint32_t descriptor_offset = 0; 319 320 desc->command = command | Dma_descriptor_link_enable; 321 desc->source = source; 322 desc->destination = destination; 323 desc->transfer_count = (units & Dma_transfer_count_mask) | 324 (descriptor_offset << Dma_descriptor_offset_shift); 325 desc->request_source = (enum Dma_jz4780_request_type) type; 326 327 // NOTE: Stride not supported yet. 328 329 l4_cache_clean_data((unsigned long) desc_vaddr, 330 (unsigned long) desc_vaddr + sizeof(*desc)); 331 332 // Commit the descriptor. 333 334 _regs[Dma_descriptor_address] = desc_paddr; 335 _chip->commit_descriptor(_channel); 336 } 337 338 // Otherwise, populate the registers for a one-off transfer. 339 340 else 341 { 342 _regs[Dma_command] = command; 343 _regs[Dma_source] = source; 344 _regs[Dma_destination] = destination; 345 _regs[Dma_transfer_count] = units & Dma_transfer_count_mask; 346 _regs[Dma_request_source] = type; 347 } 348 349 // Enable the channel with descriptor transfer configured if appropriate. 350 351 _regs[Dma_control_status] = (desc_vaddr ? Dma_8word_descriptor : 352 Dma_no_descriptor_transfer) | 353 Dma_channel_enable; 354 355 // Return the number of units to transfer. 356 357 return units; 358 } 359 360 unsigned int 361 Dma_jz4780_channel::wait() 362 { 363 // An interrupt will occur upon completion, the completion flag will be set 364 // and the transfer count will be zero. 365 366 unsigned int remaining = 0; 367 368 do 369 { 370 if (!wait_for_irq(1000000)) 371 printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); 372 else 373 { 374 printf("status = %x\n", (uint32_t) _regs[Dma_control_status]); 375 remaining = _regs[Dma_transfer_count]; 376 ack_irq(); 377 break; 378 } 379 } 380 while (!error() && !halted() && !completed()); 381 382 // Reset the channel status. 383 384 _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_channel_enable | 385 Dma_trans_completed | Dma_address_error | 386 Dma_trans_halted); 387 _regs[Dma_transfer_count] = 0; 388 389 // Return the number of remaining units. 390 391 return remaining; 392 } 393 394 // Wait indefinitely for an interrupt request, returning true if one was delivered. 395 396 bool 397 Dma_jz4780_channel::wait_for_irq() 398 { 399 if (l4_is_valid_cap(_irq)) 400 { 401 if (l4_error(l4_rcv_ep_bind_thread(_irq, get_current_thread(), 0))) 402 return false; 403 404 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && _chip->have_interrupt(_channel); 405 } 406 else 407 return true; 408 } 409 410 // Wait up to the given timeout (in microseconds) for an interrupt request, 411 // returning true if one was delivered. 412 413 bool 414 Dma_jz4780_channel::wait_for_irq(unsigned int timeout) 415 { 416 if (l4_is_valid_cap(_irq)) 417 { 418 if (l4_error(l4_rcv_ep_bind_thread(_irq, get_current_thread(), 0))) 419 return false; 420 421 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, l4util_micros2l4to(timeout)))) && _chip->have_interrupt(_channel); 422 } 423 else 424 return true; 425 } 426 427 // Acknowledge an interrupt condition. 428 429 void 430 Dma_jz4780_channel::ack_irq() 431 { 432 _chip->ack_irq(_channel); 433 } 434 435 // Return whether a transfer has completed. 436 437 bool 438 Dma_jz4780_channel::completed() 439 { 440 return _regs[Dma_control_status] & Dma_trans_completed ? true : false; 441 } 442 443 // Return whether an address error condition has arisen. 444 445 bool 446 Dma_jz4780_channel::error() 447 { 448 return _chip->error() || (_regs[Dma_control_status] & Dma_address_error ? true : false); 449 } 450 451 // Return whether a transfer has halted. 452 453 bool 454 Dma_jz4780_channel::halted() 455 { 456 return _chip->halted() || (_regs[Dma_control_status] & Dma_trans_halted ? true : false); 457 } 458 459 460 461 // Initialise the I2C controller. 462 463 Dma_jz4780_chip::Dma_jz4780_chip(l4_addr_t start, l4_addr_t end, Cpm_chip *cpm) 464 : _start(start), _end(end), _cpm(cpm) 465 { 466 _regs = new Hw::Mmio_register_block<32>(start); 467 } 468 469 // Enable the peripheral. 470 471 void 472 Dma_jz4780_chip::enable() 473 { 474 // Make sure that the DMA clock is available. 475 476 _cpm->start_clock(Clock_dma); 477 478 _regs[Dma_control] = Dma_control_enable; 479 while (!(_regs[Dma_control] & Dma_control_enable)); 480 } 481 482 // Disable the channel. 483 484 void 485 Dma_jz4780_chip::disable() 486 { 487 _regs[Dma_control] = 0; 488 while (_regs[Dma_control] & Dma_control_enable); 489 } 490 491 // Obtain a channel object. 492 493 Dma_channel * 494 Dma_jz4780_chip::get_channel(uint8_t channel, l4_cap_idx_t irq) 495 { 496 if (channel < 32) 497 return new Dma_jz4780_channel(this, channel, _start + 0x20 * channel, irq); 498 else 499 throw -L4_EINVAL; 500 } 501 502 // Return whether an interrupt is pending on the given channel. 503 504 bool 505 Dma_jz4780_chip::have_interrupt(uint8_t channel) 506 { 507 return _regs[Dma_irq_pending] & (1 << channel) ? true : false; 508 } 509 510 // Acknowledge an interrupt condition on the given channel. 511 512 void 513 Dma_jz4780_chip::ack_irq(uint8_t channel) 514 { 515 _regs[Dma_irq_pending] = _regs[Dma_irq_pending] & ~(1 << channel); 516 } 517 518 // Return whether an address error condition has arisen. 519 520 bool 521 Dma_jz4780_chip::error() 522 { 523 return _regs[Dma_control] & Dma_control_address_error ? true : false; 524 } 525 526 // Return whether a transfer has halted. 527 528 bool 529 Dma_jz4780_chip::halted() 530 { 531 return _regs[Dma_control] & Dma_control_trans_halted ? true : false; 532 } 533 534 void 535 Dma_jz4780_chip::commit_descriptor(uint8_t channel) 536 { 537 _regs[Dma_doorbell_set] = (1 << channel); 538 } 539 540 Dma_chip *jz4780_dma_chip(l4_addr_t start, l4_addr_t end, Cpm_chip *cpm) 541 { 542 return new Dma_jz4780_chip(start, end, cpm); 543 } 544 545 546 547 // C language interface functions. 548 549 void *jz4780_dma_init(l4_addr_t start, l4_addr_t end, void *cpm) 550 { 551 return (void *) jz4780_dma_chip(start, end, static_cast<Cpm_chip *>(cpm)); 552 } 553 554 void jz4780_dma_disable(void *dma_chip) 555 { 556 static_cast<Dma_chip *>(dma_chip)->disable(); 557 } 558 559 void jz4780_dma_enable(void *dma_chip) 560 { 561 static_cast<Dma_chip *>(dma_chip)->enable(); 562 } 563 564 void *jz4780_dma_get_channel(void *dma, uint8_t channel, l4_cap_idx_t irq) 565 { 566 return static_cast<Dma_chip *>(dma)->get_channel(channel, irq); 567 } 568 569 unsigned int jz4780_dma_transfer(void *dma_channel, 570 uint32_t source, uint32_t destination, 571 unsigned int count, 572 int source_increment, int destination_increment, 573 uint8_t source_width, uint8_t destination_width, 574 uint8_t transfer_unit_size, 575 enum Dma_jz4780_request_type type) 576 { 577 return static_cast<Dma_jz4780_channel *>(dma_channel)->transfer(source, 578 destination, count, source_increment, destination_increment, source_width, 579 destination_width, transfer_unit_size, type); 580 } 581 582 unsigned int jz4780_dma_transfer_descriptor(void *dma_channel, 583 uint32_t source, uint32_t destination, 584 unsigned int count, 585 int source_increment, int destination_increment, 586 uint8_t source_width, uint8_t destination_width, 587 uint8_t transfer_unit_size, 588 enum Dma_jz4780_request_type type, 589 l4_addr_t desc_vaddr, 590 l4re_dma_space_dma_addr_t desc_paddr) 591 { 592 return static_cast<Dma_jz4780_channel *>(dma_channel)->transfer(source, 593 destination, count, source_increment, destination_increment, source_width, 594 destination_width, transfer_unit_size, type, desc_vaddr, desc_paddr); 595 } 596 597 unsigned int jz4780_dma_wait(void *dma_channel) 598 { 599 return static_cast<Dma_jz4780_channel *>(dma_channel)->wait(); 600 }