1 /* 2 * GPIO driver for Ingenic X1600. 3 * (See below for additional copyright and licensing notices.) 4 * 5 * Copyright (C) 2017, 2023 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 * 22 * 23 * Subject to other copyrights, being derived from the bcm2835.cc and 24 * omap.cc GPIO driver implementations. 25 * 26 * This file is part of TUD:OS and distributed under the terms of the 27 * GNU General Public License 2. 28 * Please see the COPYING-GPL-2 file for details. 29 */ 30 31 #include <l4/sys/icu.h> 32 #include <l4/util/util.h> 33 #include <l4/devices/hw_mmio_register_block.h> 34 35 #include "gpio-x1600.h" 36 37 /* 38 GPIO register offsets (x in A..D). 39 40 Register summary: 41 42 PxINT 0 (function/GPIO) 1 (interrupt) 43 PxMSK 0 (function) 1 (GPIO) 0 (IRQ enable)/1 (IRQ disable) 44 PxPAT1 0 (function 0/1) 1 (function 2/3) 0 (output) 1 (input) 0 (level trigger) 1 (edge trigger) 45 PxPAT0 0 (function 0) 0 (function 2) 0 (output value 0) 0 (low level) 0 (falling edge) 46 1 (function 1) 1 (function 3) 1 (output value 1) 1 (high level) 1 (rising edge) 47 */ 48 49 enum Regs 50 { 51 Pin_level = 0x000, // PxPINL (read-only) 52 53 Port_int = 0x010, // PxINT 54 Port_int_set = 0x014, // PxINTS 55 Port_int_clear = 0x018, // PxINTC 56 57 Irq_mask = 0x020, // PxMSK (for PxINT == 1) 58 Irq_mask_set = 0x024, // PxMSKS 59 Irq_mask_clear = 0x028, // PxMSKC 60 Port_gpio = 0x020, // PxMSK (for PxINT == 0) 61 Port_gpio_set = 0x024, // PxMSKS 62 Port_gpio_clear = 0x028, // PxMSKC 63 64 Port_trigger = 0x030, // PxPAT1 (for PxINT == 1) 65 Port_trigger_set = 0x034, // PxPAT1S 66 Port_trigger_clear = 0x038, // PxPAT1C 67 Port_dir = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 1) 68 Port_dir_set = 0x034, // PxPAT1S 69 Port_dir_clear = 0x038, // PxPAT1C 70 Port_group1 = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 0) 71 Port_group1_set = 0x034, // PxPAT1S 72 Port_group1_clear = 0x038, // PxPAT1C 73 74 Port_level = 0x040, // PxPAT0 (for PxINT == 1) 75 Port_level_set = 0x044, // PxPAT0S 76 Port_level_clear = 0x048, // PxPAT0C 77 Port_data = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 1, PxPAT1 == 0) 78 Port_data_set = 0x044, // PxPAT0S 79 Port_data_clear = 0x048, // PxPAT0C 80 Port_group0 = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 0) 81 Port_group0_set = 0x044, // PxPAT0S 82 Port_group0_clear = 0x048, // PxPAT0C 83 84 Irq_flag = 0x050, // PxFLG (read-only) 85 Irq_flag_clear = 0x058, // PxFLGC 86 87 // Only the following registers differ from the JZ4780. The dual-edge 88 // registers being added to the X1600, with the pull-up/down registers being 89 // relocated and their sense changed from disable to enable. 90 91 Pull_edge = 0x070, // PxEDG 92 Pull_edge_set = 0x074, // PxEDGS 93 Pull_edge_clear = 0x078, // PxEDGC 94 95 Pull_enable = 0x080, // PxPE 96 Pull_enable_set = 0x084, // PxPES 97 Pull_enable_clear = 0x088, // PxPEC 98 99 // The shadow port Z is available at offset 0x700 and supports the INTS, INTC, 100 // MSKS, MSKC, PAT1S, PAT1C, PAT0S, PAT0C registers, along with the following. 101 102 Shadow_transfer = 0x0f0, // PzGID2LD 103 }; 104 105 106 107 // X1600 pull-up/down configuration. 108 109 struct gpio_port gpio_ports[] = { 110 {0xffffffff, 0x00000000}, 111 {0xdffbf7bf, 0x00000000}, 112 {0x987e0000, 0x07000007}, 113 {0x0000003f, 0x00000000} 114 }; 115 116 117 118 // IRQ control for each GPIO pin. 119 120 Gpio_x1600_irq_pin::Gpio_x1600_irq_pin(unsigned pin, Hw::Register_block<32> const ®s, 121 Hw::Register_block<32> const &shadow_regs, 122 uint8_t port_number) 123 : _pin(pin), _regs(regs), _shadow_regs(shadow_regs), _port_number(port_number), 124 _shadow(true) 125 {} 126 127 Gpio_x1600_irq_pin::Gpio_x1600_irq_pin(unsigned pin, Hw::Register_block<32> const ®s) 128 : _pin(pin), _regs(regs), _shadow(false) 129 {} 130 131 void 132 Gpio_x1600_irq_pin::write_reg_pin(unsigned reg) 133 { 134 // Write the pin bit to the register, setting or clearing the pin 135 // depending on the register chosen. 136 137 if (_shadow) 138 _shadow_regs[reg] = _pin_bit(_pin); 139 else 140 _regs[reg] = _pin_bit(_pin); 141 } 142 143 void Gpio_x1600_irq_pin::do_mask() 144 { 145 // Set the interrupt bit in the PxIM register. 146 147 write_reg_pin(Irq_mask_set); 148 } 149 150 void Gpio_x1600_irq_pin::do_unmask() 151 { 152 // Clear the interrupt bit in the PxIM register, first also clearing the 153 // flag bit in the PxFLG register to allow interrupts to be delivered. 154 155 write_reg_pin(Irq_flag_clear); 156 write_reg_pin(Irq_mask_clear); 157 } 158 159 bool Gpio_x1600_irq_pin::do_set_mode(unsigned mode) 160 { 161 // Standard comment found for this method: 162 // this operation touches multiple mmio registers and is thus 163 // not atomic, that's why we first mask the IRQ and if it was 164 // enabled we unmask it after we have changed the mode 165 166 // The X1600 provides a special port Z that allows changes to be made and then 167 // committed atomically using PzGID2LD. 168 169 if (!_shadow && enabled()) 170 do_mask(); 171 172 // Do the PxINT, PxPAT1 and PxPAT0 configuration. 173 174 switch(mode) 175 { 176 case L4_IRQ_F_LEVEL_HIGH: 177 write_reg_pin(Port_int_set); 178 write_reg_pin(Port_trigger_clear); 179 write_reg_pin(Port_level_set); 180 break; 181 case L4_IRQ_F_LEVEL_LOW: 182 write_reg_pin(Port_int_set); 183 write_reg_pin(Port_trigger_clear); 184 write_reg_pin(Port_level_clear); 185 break; 186 case L4_IRQ_F_POS_EDGE: 187 write_reg_pin(Port_int_set); 188 write_reg_pin(Port_trigger_set); 189 write_reg_pin(Port_level_set); 190 break; 191 case L4_IRQ_F_NEG_EDGE: 192 write_reg_pin(Port_int_set); 193 write_reg_pin(Port_trigger_set); 194 write_reg_pin(Port_level_clear); 195 break; 196 197 default: 198 return false; 199 } 200 201 if (_shadow) 202 _shadow_regs[Shadow_transfer] = _port_number; 203 else if (enabled()) 204 do_unmask(); 205 206 return true; 207 } 208 209 int Gpio_x1600_irq_pin::clear() 210 { 211 // Obtain the flag status for the pin, clearing it if set. 212 213 l4_uint32_t e = _regs[Irq_flag] & (1UL << _pin); 214 if (e) 215 _regs[Irq_flag_clear] = e; 216 217 return (e >> _pin); 218 } 219 220 bool Gpio_x1600_irq_pin::enabled() 221 { 222 return true; 223 } 224 225 226 227 // Initialise the GPIO controller. 228 229 Gpio_x1600_chip::Gpio_x1600_chip(l4_addr_t start, uint8_t port_number, 230 bool shadow) 231 : _nr_pins(32), _port_number(port_number), _shadow(shadow) 232 { 233 _start = start + port_number * 0x100; 234 _regs = new Hw::Mmio_register_block<32>(_start); 235 _pull_config = &gpio_ports[port_number]; 236 237 if (_shadow) 238 { 239 _shadow_start = start + 0x700; 240 _shadow_regs = new Hw::Mmio_register_block<32>(_shadow_start); 241 } 242 else 243 _shadow = false; 244 } 245 246 void 247 Gpio_x1600_chip::write_reg_pin(unsigned reg, unsigned pin) 248 { 249 // Write the pin bit to the register, setting or clearing the pin 250 // depending on the register chosen. 251 252 if (_shadow) 253 _shadow_regs[reg] = _pin_bit(pin); 254 else 255 _regs[reg] = _pin_bit(pin); 256 } 257 258 // Return the value of a pin. 259 260 int 261 Gpio_x1600_chip::get(unsigned pin) 262 { 263 if (pin >= _nr_pins) 264 throw -L4_EINVAL; 265 266 l4_uint32_t val = _regs[Pin_level]; 267 return (val >> _pin_shift(pin)) & 1; 268 } 269 270 // Return multiple pin values. 271 272 unsigned 273 Gpio_x1600_chip::multi_get(unsigned offset) 274 { 275 _reg_offset_check(offset); 276 return _regs[Pin_level]; 277 } 278 279 // Set the value of a pin. 280 281 void 282 Gpio_x1600_chip::set(unsigned pin, int value) 283 { 284 if (pin >= _nr_pins) 285 throw -L4_EINVAL; 286 287 l4_uint32_t reg_set = value ? Port_data_set : Port_data_clear; 288 _regs[reg_set] = _pin_bit(pin); 289 } 290 291 // Set multiple pin values. 292 293 void 294 Gpio_x1600_chip::multi_set(Pin_slice const &mask, unsigned data) 295 { 296 _reg_offset_check(mask.offset); 297 if (mask.mask & data) 298 _regs[Port_data_set] = (mask.mask & data); 299 if (mask.mask & ~data) 300 _regs[Port_data_clear] = (mask.mask & ~data); 301 } 302 303 // Set a pin up with the given mode and value (if appropriate). 304 305 void 306 Gpio_x1600_chip::setup(unsigned pin, unsigned mode, int value) 307 { 308 if (pin >= _nr_pins) 309 throw -L4_EINVAL; 310 311 config(pin, mode); 312 313 if (mode == Output) 314 set(pin, value); 315 } 316 317 // Configuration of a pin using the generic input/output/IRQ mode. 318 319 void 320 Gpio_x1600_chip::config(unsigned pin, unsigned mode) 321 { 322 switch (mode) 323 { 324 case Input: 325 write_reg_pin(Port_int_clear, pin); 326 write_reg_pin(Port_gpio_set, pin); 327 write_reg_pin(Port_dir_set, pin); 328 break; 329 case Output: 330 write_reg_pin(Port_int_clear, pin); 331 write_reg_pin(Port_gpio_set, pin); 332 write_reg_pin(Port_dir_clear, pin); 333 break; 334 case Irq: 335 write_reg_pin(Port_int_set, pin); 336 // Other details depend on the actual trigger mode. 337 break; 338 default: 339 break; 340 } 341 342 if (_shadow) 343 _shadow_regs[Shadow_transfer] = _port_number; 344 } 345 346 // Pull-up/down configuration for a pin. 347 348 void 349 Gpio_x1600_chip::config_pull(unsigned pin, unsigned mode) 350 { 351 if (pin >= _nr_pins) 352 throw -L4_EINVAL; 353 354 switch (mode) 355 { 356 case Pull_none: 357 _regs[Pull_enable_clear] = _pin_bit(pin); 358 break; 359 case Pull_down: 360 if (_pin_bit(pin) & _pull_config->pull_downs) 361 _regs[Pull_enable_set] = _pin_bit(pin); 362 break; 363 case Pull_up: 364 if (_pin_bit(pin) & _pull_config->pull_ups) 365 _regs[Pull_enable_set] = _pin_bit(pin); 366 break; 367 default: 368 // Invalid pull-up/down mode for pin. 369 throw -L4_EINVAL; 370 } 371 } 372 373 // Pin function configuration. 374 375 void 376 Gpio_x1600_chip::config_pad(unsigned pin, unsigned func, unsigned value) 377 { 378 if (pin >= _nr_pins) 379 throw -L4_EINVAL; 380 381 if (value > 3) 382 throw -L4_EINVAL; 383 384 switch (func) 385 { 386 // Support two different outputs. 387 388 case Hw::Gpio_chip::Function_gpio: 389 write_reg_pin(Port_int_clear, pin); 390 write_reg_pin(Port_gpio_set, pin); 391 write_reg_pin(value & 1 ? Port_data_set : Port_data_clear, pin); 392 break; 393 394 // Support four different device functions. 395 396 case Hw::Gpio_chip::Function_alt: 397 write_reg_pin(Port_int_clear, pin); 398 write_reg_pin(Port_gpio_clear, pin); 399 write_reg_pin(value & 2 ? Port_group1_set : Port_group1_clear, pin); 400 write_reg_pin(value & 1 ? Port_group0_set : Port_group0_clear, pin); 401 break; 402 default: 403 throw -L4_EINVAL; 404 } 405 406 if (_shadow) 407 _shadow_regs[Shadow_transfer] = _port_number; 408 } 409 410 // Obtain a pin's configuration from a register in the supplied value. 411 412 void 413 Gpio_x1600_chip::config_get(unsigned pin, unsigned reg, unsigned *value) 414 { 415 if (pin >= _nr_pins) 416 throw -L4_EINVAL; 417 418 *value = (_regs[reg] >> _pin_shift(pin)) & 1; 419 } 420 421 // Return function and function-specific configuration for a pin. 422 423 void 424 Gpio_x1600_chip::config_pad_get(unsigned pin, unsigned *func, unsigned *value) 425 { 426 unsigned direction, gpio, group0, group1, interrupt, level, trigger; 427 428 config_get(pin, Port_int, &interrupt); 429 430 if (interrupt) 431 { 432 config_get(pin, Port_trigger, &trigger); 433 config_get(pin, Port_level, &level); 434 435 *func = Hw::Gpio_chip::Function_irq; 436 *value = (trigger ? (level ? L4_IRQ_F_POS_EDGE : L4_IRQ_F_NEG_EDGE) 437 : (level ? L4_IRQ_F_LEVEL_HIGH : L4_IRQ_F_LEVEL_LOW)); 438 return; 439 } 440 441 config_get(pin, Port_gpio, &gpio); 442 443 if (gpio) 444 { 445 config_get(pin, Port_dir, &direction); 446 447 *func = Hw::Gpio_chip::Function_gpio; 448 *value = direction ? Input : Output; 449 return; 450 } 451 452 *func = Hw::Gpio_chip::Function_alt; 453 454 config_get(pin, Port_group0, &group0); 455 config_get(pin, Port_group1, &group1); 456 457 *value = (group1 << 1) | group0; 458 } 459 460 // Obtain an IRQ abstraction for a pin. 461 462 Hw::Gpio_irq_pin * 463 Gpio_x1600_chip::get_irq(unsigned pin) 464 { 465 if (pin >= _nr_pins) 466 throw -L4_EINVAL; 467 468 if (_shadow) 469 return new Gpio_x1600_irq_pin(pin, _regs, _shadow_regs, _port_number); 470 else 471 return new Gpio_x1600_irq_pin(pin, _regs); 472 } 473 474 // Pin function configuration for multiple pins. 475 476 void 477 Gpio_x1600_chip::multi_config_pad(Pin_slice const &mask, unsigned func, unsigned val) 478 { 479 unsigned m = mask.mask; 480 for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1) 481 if (m & 1) 482 config_pad(pin, func, val); 483 } 484 485 // Set up multiple pins with the given mode. 486 487 void 488 Gpio_x1600_chip::multi_setup(Pin_slice const &mask, unsigned mode, unsigned outvalues) 489 { 490 unsigned m = mask.mask; 491 for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1, outvalues >>= 1) 492 if (m & 1) 493 setup(pin, mode, outvalues & 1); 494 } 495 496 497 498 // C language interface functions. 499 500 void *x1600_gpio_init(l4_addr_t start, uint8_t port_number) 501 { 502 return (void *) new Gpio_x1600_chip(start, port_number, false); 503 } 504 505 void *x1600_gpio_init_shadow(l4_addr_t start, uint8_t port_number) 506 { 507 return (void *) new Gpio_x1600_chip(start, port_number, true); 508 } 509 510 void x1600_gpio_setup(void *gpio, unsigned pin, unsigned mode, int value) 511 { 512 static_cast<Gpio_x1600_chip *>(gpio)->setup(pin, mode, value); 513 } 514 515 void x1600_gpio_config_pull(void *gpio, unsigned pin, unsigned mode) 516 { 517 static_cast<Gpio_x1600_chip *>(gpio)->config_pull(pin, mode); 518 } 519 520 void x1600_gpio_config_pad(void *gpio, unsigned pin, unsigned func, unsigned value) 521 { 522 static_cast<Gpio_x1600_chip *>(gpio)->config_pad(pin, func, value); 523 } 524 525 void x1600_gpio_config_get(void *gpio, unsigned pin, unsigned reg, unsigned *value) 526 { 527 static_cast<Gpio_x1600_chip *>(gpio)->config_get(pin, reg, value); 528 } 529 530 void x1600_gpio_config_pad_get(void *gpio, unsigned pin, unsigned *func, unsigned *value) 531 { 532 static_cast<Gpio_x1600_chip *>(gpio)->config_pad_get(pin, func, value); 533 } 534 535 void x1600_gpio_multi_setup(void *gpio, Pin_slice const *mask, unsigned mode, unsigned outvalues) 536 { 537 static_cast<Gpio_x1600_chip *>(gpio)->multi_setup(*mask, mode, outvalues); 538 } 539 540 void x1600_gpio_multi_config_pad(void *gpio, Pin_slice const *mask, unsigned func, unsigned value) 541 { 542 static_cast<Gpio_x1600_chip *>(gpio)->multi_config_pad(*mask, func, value); 543 } 544 545 void x1600_gpio_multi_set(void *gpio, Pin_slice const *mask, unsigned data) 546 { 547 static_cast<Gpio_x1600_chip *>(gpio)->multi_set(*mask, data); 548 } 549 550 unsigned x1600_gpio_multi_get(void *gpio, unsigned offset) 551 { 552 return static_cast<Gpio_x1600_chip *>(gpio)->multi_get(offset); 553 } 554 555 int x1600_gpio_get(void *gpio, unsigned pin) 556 { 557 return static_cast<Gpio_x1600_chip *>(gpio)->get(pin); 558 } 559 560 void x1600_gpio_set(void *gpio, unsigned pin, int value) 561 { 562 static_cast<Gpio_x1600_chip *>(gpio)->set(pin, value); 563 } 564 565 void *x1600_gpio_get_irq(void *gpio, unsigned pin) 566 { 567 return (void *) static_cast<Gpio_x1600_chip *>(gpio)->get_irq(pin); 568 } 569 570 bool x1600_gpio_irq_set_mode(void *gpio_irq, unsigned mode) 571 { 572 return static_cast<Hw::Gpio_irq_pin *>(gpio_irq)->do_set_mode(mode); 573 }