1 /* 2 * MSC (MMC/SD controller) peripheral support. 3 * 4 * Copyright (C) 2024 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/hw_mmio_register_block.h> 23 #include <l4/sys/irq.h> 24 #include <l4/util/util.h> 25 26 #include <stdio.h> 27 #include <string.h> 28 29 #include "msc-common.h" 30 31 32 33 // Register locations for each channel. 34 35 enum Regs : unsigned 36 { 37 Msc_control = 0x000, // MSC_CTRL 38 Msc_status = 0x004, // MSC_STAT 39 Msc_clock_rate = 0x008, // MSC_CLKRT 40 Msc_command_data_control = 0x00c, // MSC_CMDAT 41 Msc_response_timeout = 0x010, // MSC_RESTO 42 Msc_read_timeout = 0x014, // MSC_RDTO 43 Msc_block_length = 0x018, // MSC_BLKLEN 44 Msc_block_count = 0x01c, // MSC_NOB 45 Msc_block_success_count = 0x020, // MSC_SNOB 46 Msc_interrupt_mask = 0x024, // MSC_IMASK 47 Msc_interrupt_flag = 0x028, // MSC_IFLG/MSC_IREG 48 Msc_command_index = 0x02c, // MSC_CMD 49 Msc_command_argument = 0x030, // MSC_ARG 50 Msc_response_fifo = 0x034, // MSC_RES 51 Msc_recv_data_fifo = 0x038, // MSC_RXFIFO 52 Msc_trans_data_fifo = 0x03c, // MSC_TXFIFO 53 54 // JZ4780/X1600 only. 55 56 Msc_low_power_mode = 0x040, // MSC_LPM 57 Msc_dma_control = 0x044, // MSC_DMAC 58 Msc_dma_descriptor_address = 0x048, // MSC_DMANDA 59 Msc_dma_data_address = 0x04c, // MSC_DMADA 60 Msc_dma_data_length = 0x050, // MSC_DMALEN 61 Msc_dma_command = 0x054, // MSC_DMACMD 62 Msc_control2 = 0x058, // MSC_CTRL2 63 Msc_rtfifo_data_counter = 0x05c, // MSC_RTCNT 64 65 // Channel block size/offset. 66 67 Msc_channel_offset = 0x10000, 68 }; 69 70 // Field definitions. 71 72 enum Control_bits : unsigned 73 { 74 // JZ4780/X1600 only. 75 76 Control_send_ccsd = 0x8000, // SEND_CCSD 77 Control_send_ccsd_automatically = 0x4000, // SEND_CCSD 78 79 // Common. 80 81 Control_exit_multiple = 0x0080, // EXIT_MULTIPLE 82 Control_exit_transfer = 0x0040, // EXIT_TRANSFER 83 Control_start_read_wait = 0x0020, // START_READ_WAIT 84 Control_stop_read_wait = 0x0010, // STOP_READ_WAIT 85 Control_reset = 0x0008, // RESET 86 Control_start_operation = 0x0004, // START_OP 87 88 Control_clock_control_field_mask = 0x3, // CLOCK_CTRL 89 Control_clock_control_start = 2, 90 Control_clock_control_stop = 1, 91 Control_clock_control_field_shift = 0, 92 }; 93 94 enum Control2_bits : unsigned 95 { 96 // JZ4780/X1600 only. 97 98 Control2_pin_level_polarity_field_mask = 0x1f, // PIP 99 Control2_pin_level_polarity_field_shift = 24, 100 101 // JZ4780 only. 102 103 Control2_reset_enable = 0x00800000, // RST_EN 104 105 // JZ4780/X1600 only. 106 107 Control2_stop_read_operation_mode = 0x00000010, // STPRM 108 109 // JZ4780 only. 110 111 Control2_signal_voltage_change = 0x00000008, // SVC 112 113 // JZ4780/X1600 only. 114 115 Control2_speed_mode_field_mask = 0x7, // SMS 116 Control2_speed_mode_default = 0, // = 0 117 Control2_speed_mode_high = 1, // = 1 118 Control2_speed_mode_sdr12 = 2, // = 2 119 Control2_speed_mode_sdr25 = 3, // = 3 120 Control2_speed_mode_sdr50 = 4, // = 4 121 Control2_speed_mode_field_shift = 0, 122 }; 123 124 enum Status_bits : unsigned 125 { 126 // JZ4780/X1600 only. 127 128 Status_auto_cmd12_done = 0x80000000, // AUTO_CMD12_DONE 129 130 // JZ4780 only. 131 132 Status_auto_cmd23_done = 0x40000000, // AUTO_CMD23_DONE 133 Status_signal_voltage_change = 0x20000000, // SVS 134 135 // JZ4780/X1600 only. 136 137 Status_pin_level_field_mask = 0x1f, // PIN_LEVEL 138 Status_pin_level_field_shift = 24, 139 140 Status_boot_crc_error = 0x00100000, // BCE 141 Status_boot_data_end = 0x00080000, // BDE 142 Status_boot_ack_error = 0x00040000, // BAE 143 Status_boot_ack_received = 0x00020000, // BAR 144 Status_dma_end = 0x00010000, // DMAEND 145 146 // Common. 147 148 Status_resetting = 0x8000, // IS_RESETTING 149 Status_sdio_interrupt_active = 0x4000, // SDIO_INT_ACTIVE 150 Status_programming_done = 0x2000, // PRG_DONE 151 Status_data_transfer_done = 0x1000, // DATA_TRAN_DONE 152 Status_end_command_response = 0x0800, // END_CMD_RES 153 Status_data_fifo_almost_full = 0x0400, // DATA_FIFO_AFULL 154 Status_read_wait = 0x0200, // IS_READWAIT 155 Status_clock_enabled = 0x0100, // CLK_EN 156 Status_data_fifo_full = 0x0080, // DATA_FIFO_FULL 157 Status_data_fifo_empty = 0x0040, // DATA_FIFO_EMPTY 158 Status_response_crc_error = 0x0020, // CRC_RES_ERR 159 Status_read_crc_error = 0x0010, // CRC_READ_ERROR 160 Status_write_crc_error_no_status = 0x0008, // CRC_WRITE_ERROR (2) 161 Status_write_crc_error_data = 0x0004, // CRC_WRITE_ERROR (1) 162 Status_timeout_response = 0x0002, // TIME_OUT_RES 163 Status_timeout_read = 0x0001, // TIME_OUT_READ 164 }; 165 166 enum Clock_rate_bits : unsigned 167 { 168 Clock_rate_field_mask = 0x7, // CLK_RATE 169 Clock_rate_field_shift = 0, 170 }; 171 172 enum Command_data_control_bits : unsigned 173 { 174 // JZ4780/X1600 only. 175 176 Cdc_ccs_expected = 0x80000000, // CCS_EXPECTED 177 Cdc_read_ce_ata = 0x40000000, // READ_CEATA 178 Cdc_disable_boot = 0x08000000, // DIS_BOOT 179 Cdc_expect_boot_ack = 0x02000000, // EXP_BOOT_ACK 180 Cdc_alternative_boot_mode = 0x01000000, // BOOT_MODE 181 182 // JZ4780 only. 183 184 Cdc_auto_cmd23 = 0x00040000, // AUTO_CMD23 185 186 // JZ4780/X1600 only. 187 188 Cdc_sdio_interrupt_2cycle = 0x00020000, // SDIO_PRDT 189 Cdc_auto_cmd12 = 0x00010000, // AUTO_CMD12 190 191 Cdc_recv_fifo_level_field_mask = 0x3, // RTRG 192 Cdc_fifo_level_16 = 0, 193 Cdc_fifo_level_32 = 1, 194 Cdc_fifo_level_64 = 2, 195 Cdc_fifo_level_96 = 3, 196 Cdc_recv_fifo_level_field_shift = 14, 197 198 Cdc_trans_fifo_level_field_mask = 0x3, // TTRG 199 Cdc_trans_fifo_level_field_shift = 12, 200 201 // Common. 202 203 Cdc_io_abort = 0x0800, // IO_ABORT 204 205 Cdc_bus_width_field_mask = 0x3, // BUS_WIDTH 206 Cdc_bus_width_field_1bit = 0, // = 0 207 Cdc_bus_width_field_4bit = 2, // = 2 208 Cdc_bus_width_field_shift = 9, 209 210 // JZ4740 only. 211 212 Cdc_dma_enable = 0x0100, // DMA_EN 213 Cdc_dma_disable = 0x0000, 214 215 // Common. 216 217 Cdc_init_sequence = 0x0080, // INIT 218 219 Cdc_expect_busy = 0x0040, // BUSY 220 Cdc_do_not_expect_busy = 0x0000, 221 222 Cdc_stream_block = 0x0020, // STREAM_BLOCK 223 Cdc_not_stream_block = 0x0000, 224 225 Cdc_write_operation = 0x0010, // WRITE_READ 226 Cdc_read_operation = 0x0000, 227 228 Cdc_data_with_command = 0x0008, // DATA_EN 229 Cdc_no_data_with_command = 0x0000, 230 231 Cdc_response_format_field_mask = 0x7, // RESPONSE_FORMAT 232 Cdc_response_format_field_shift = 0, 233 }; 234 235 enum Response_timeout_bits : unsigned 236 { 237 // NOTE: 16-bit value in the JZ4780. 238 // NOTE: 32-bit value in the X1600. 239 240 Response_timeout_mask = 0x000000ff, // RES_TO 241 }; 242 243 enum Read_timeout_bits : unsigned 244 { 245 // NOTE: 16-bit value prior to the JZ4780/X1600. 246 247 Read_timeout_mask = 0xffffffff, // READ_TO 248 }; 249 250 enum Block_length_bits : unsigned 251 { 252 // NOTE: 16-bit value in the JZ4780/X1600. 253 254 Block_length_mask = 0x00000fff, // BLK_LEN 255 }; 256 257 enum Block_count_bits : unsigned 258 { 259 Block_count_mask = 0x0000ffff, // NOB/SNOB 260 }; 261 262 // Interrupt mask/flag bits. 263 264 enum Interrupt_bits : unsigned 265 { 266 // X1600 only. 267 268 Int_dma_data_done = 0x80000000, // DMA_DATA_DONE 269 270 // JZ4780 only. 271 272 Int_auto_cmd23_done = 0x40000000, // AUTO_CMD23_DONE 273 Int_signal_voltage_change = 0x20000000, // SVS 274 275 // JZ4780/X1600 only. 276 277 Int_pin_level_field_mask = 0x1f, // PIN_LEVEL 278 Int_pin_level_field_shift = 24, 279 280 // X1600 only. 281 282 Int_write_request_all_done = 0x00800000, // WR_ALL_DONE 283 284 // JZ4780/X1600 only. 285 286 Int_boot_crc_error = 0x00100000, // BCE 287 Int_boot_data_end = 0x00080000, // BDE 288 Int_boot_ack_error = 0x00040000, // BAE 289 Int_boot_ack_received = 0x00020000, // BAR 290 Int_dma_end = 0x00010000, // DMAEND 291 Int_auto_cmd12_done = 0x00008000, // AUTO_CMD12_DONE 292 Int_data_fifo_full = 0x00004000, // DATA_FIFO_FULL 293 Int_data_fifo_empty = 0x00002000, // DATA_FIFO_EMP 294 Int_crc_response_error = 0x00001000, // CRC_RES_ERR 295 Int_crc_read_error = 0x00000800, // CRC_READ_ERR 296 Int_crc_write_error = 0x00000400, // CRC_WRITE_ERR 297 Int_response_timeout = 0x00000200, // TIME_OUT_RES 298 Int_read_timeout = 0x00000100, // TIME_OUT_READ 299 300 // Common. 301 302 Int_sdio = 0x80, // SDIO 303 Int_trans_fifo_write_request = 0x40, // TXFIFO_WR_REQ 304 Int_recv_fifo_read_request = 0x20, // RXFIFO_RD_REQ 305 Int_end_command_response = 0x04, // END_CMD_RES 306 Int_programming_done = 0x02, // PRG_DONE 307 Int_data_transfer_done = 0x01, // DATA_TRAN_DONE 308 }; 309 310 enum Command_index_bits : unsigned 311 { 312 Command_index_mask = 0x0000003f, // CMD_INDEX 313 }; 314 315 enum Command_argument_bits : unsigned 316 { 317 Command_argument_mask = 0xffffffff, // ARG 318 }; 319 320 enum Response_fifo_bits : unsigned 321 { 322 Response_fifo_mask = 0x0000ffff, // DATA 323 }; 324 325 enum Recv_data_fifo_bits : unsigned 326 { 327 Recv_data_fifo_mask = 0xffffffff, // DATA 328 }; 329 330 enum Trans_data_fifo_bits : unsigned 331 { 332 Trans_data_fifo_mask = 0xffffffff, // DATA 333 }; 334 335 enum Low_power_mode_bits : unsigned 336 { 337 Low_power_mode_enable = 0x00000001, // LPM 338 }; 339 340 enum Dma_control_bits : unsigned 341 { 342 Dma_mode_specify_transfer_length = 0x80, // MODE_SEL 343 344 Dma_address_offset_field_mask = 0x3, // AOFST 345 Dma_address_offset_field_shift = 5, 346 347 Dma_align_enable = 0x10, // ALIGNEN 348 349 Dma_burst_type_field_mask = 0x3, // INCR 350 Dma_burst_type_incr16 = 0, 351 Dma_burst_type_incr32 = 1, 352 Dma_burst_type_incr64 = 2, 353 Dma_burst_type_field_shift = 2, 354 355 Dma_select_common_dma = 0x02, // DMASEL 356 Dma_select_special_dma = 0x00, 357 358 Dma_enable = 0x01, // DMAEN 359 Dma_disable = 0x00, 360 }; 361 362 363 364 // Command indexes. 365 366 enum Command_index : unsigned 367 { 368 Command_go_idle_state = 0, 369 Command_send_op_cond = 1, 370 Command_all_send_cid = 2, 371 Command_send_relative_addr = 3, // SD 372 Command_set_relative_addr = 3, // MMC 373 Command_set_dsr = 4, 374 Command_io_send_op_cond = 5, // SDIO 375 Command_select_deselect_card = 7, 376 Command_send_if_cond = 8, 377 Command_send_csd = 9, 378 Command_send_cid = 10, 379 Command_read_dat_until_stop = 11, 380 Command_stop_transmission = 12, 381 Command_send_status = 13, 382 Command_go_inactive_state = 15, 383 Command_set_blocklen = 16, 384 Command_read_single_block = 17, 385 Command_read_multiple_block = 18, 386 Command_write_dat_until_stop = 20, 387 Command_set_block_count = 23, 388 Command_write_block = 24, 389 Command_write_multiple_block = 25, 390 Command_program_cid = 26, 391 Command_program_csd = 27, 392 Command_set_write_prot = 28, 393 Command_clr_write_prot = 29, 394 Command_send_write_prot = 30, 395 Command_tag_sector_start = 32, 396 Command_tag_sector_end = 33, 397 Command_untag_sector = 34, 398 Command_tag_erase_group_start = 35, 399 Command_tag_erase_group_end = 36, 400 Command_untag_erase_group = 37, 401 Command_erase = 38, 402 Command_fast_io = 39, 403 Command_go_irq_state = 40, 404 Command_lock_unlock = 42, 405 Command_io_rw_direct = 52, // SDIO 406 Command_app_cmd = 55, 407 Command_gen_cmd = 56, 408 }; 409 410 // Application-specific command indexes, used by first issuing Command_app_cmd. 411 412 enum App_command_index : unsigned 413 { 414 App_command_set_bus_width = 6, 415 App_command_sd_status = 13, 416 App_command_send_num_wr_blocks = 22, 417 App_command_set_wr_block_erase_count = 23, 418 App_command_sd_send_op_cond = 41, 419 App_command_set_clr_card_detect = 42, 420 App_command_send_scr = 51, 421 App_command_read_ocr = 58, 422 }; 423 424 enum Bus_width_bits : unsigned 425 { 426 Bus_width_1bit = 0, 427 Bus_width_4bit = 2, 428 }; 429 430 // Command response sizes in 16-bit units. 431 432 enum Response_sizes : unsigned 433 { 434 Response_size_R1 = 3, 435 Response_size_R2 = 8, // omits the CRC and end bit 436 Response_size_R3 = 3, 437 Response_size_R4 = 3, 438 Response_size_R5 = 3, 439 Response_size_R6 = 3, 440 Response_size_R7 = 3, 441 }; 442 443 // SD_SEND_OP_COND argument flags. 444 445 enum Ocr_argument_flags : unsigned 446 { 447 Ocr_high_capacity_storage = 0x40000000, 448 }; 449 450 // SD_SEND_OP_COND response flags (R3). 451 452 enum Ocr_response_flags : unsigned 453 { 454 Ocr_card_powered_up = 0x80000000, 455 }; 456 457 // R1 status flags. 458 459 enum R1_status_flags : unsigned 460 { 461 R1_status_error_mask = 0xffff0000, 462 }; 463 464 465 466 // MMC response structures. 467 468 struct R1 469 { 470 uint8_t end_crc; 471 uint32_t status; 472 uint8_t index:6, trans_start:2; 473 } __attribute__((packed)); 474 475 struct R2 476 { 477 // uint8_t end_crc; (not retrieved) 478 479 union 480 { 481 uint8_t raw[15]; 482 struct CID cid; 483 struct CSD csd; 484 } payload; 485 486 uint8_t reserved_trans_start; 487 } __attribute__((packed)); 488 489 struct R3 490 { 491 uint8_t end_reserved; 492 uint32_t ocr; 493 uint8_t reserved_trans_start; 494 } __attribute__((packed)); 495 496 // SDIO response structures. 497 498 struct R4 499 { 500 uint8_t end_reserved; 501 uint32_t ocr:24, stuff:3, memory_present:1, number_io_functions:3, ready:1; 502 uint8_t reserved_trans_start; 503 } __attribute__((packed)); 504 505 struct R5 506 { 507 uint8_t end_crc; 508 uint8_t data; 509 uint8_t out_of_range:1, invalid_function_number:1, reserved:1, error:1, 510 io_current_state:2, illegal_command:1, crc_error:1; 511 uint16_t stuff; 512 uint8_t index:6, trans_start:2; 513 } __attribute__((packed)); 514 515 struct R6 516 { 517 uint8_t end_crc; 518 uint16_t status; 519 uint16_t rca; 520 uint8_t index:6, trans_start:2; 521 } __attribute__((packed)); 522 523 struct R7 524 { 525 uint8_t end_crc; 526 527 union 528 { 529 uint32_t check:8, voltage:4, reserved:20; 530 uint32_t raw; 531 } check_voltage; 532 533 uint8_t index:6, trans_start:2; 534 } __attribute__((packed)); 535 536 537 538 // Command frame: 539 // byte: start (1), direction (1), command (6) 540 // 4 bytes: argument 541 // byte: CRC (7), end (1) 542 543 // IO_RW_DIRECT argument: 544 // Argument MSB to LSB: R/W (1), function number (3), read after write flag (1), 545 // stuff (1), register address (17), stuff (1), 546 // write data or stuff (8) 547 // 0x88000c08: W, function = 0, read after write, register address = 6 (CCCR), 548 // data = 8 (reset) 549 550 const uint32_t Io_rw_direct_reset = 0x88000c08; 551 552 // (IO_)SEND_OP_COND argument and default voltage range expected in R3, R4: 553 // Argument MSB to LSB: stuff (8), voltage range (16), reserved (8) 554 // 0x00ff8000: voltage range 2.7 - 3.6V 555 556 const uint32_t Ocr_default_voltage_range = 0x00ff8000; 557 558 // SEND_IF_COND argument and default voltage range expected in R7: 559 // Argument MSB to LSB: stuff (20), voltage supplied (4), check (8) 560 // 0x000001aa: voltage range 2.7 - 3.6V, check = 0b10101010 561 562 const uint32_t If_cond_default_voltage_range = 0x000001aa; 563 564 565 566 // Channel abstraction. 567 568 Msc_channel::Msc_channel(l4_addr_t msc_start, l4_addr_t addr, l4_cap_idx_t irq) 569 : _msc_start(msc_start), _irq(irq) 570 { 571 _regs = new Hw::Mmio_register_block<32>(addr); 572 } 573 574 Msc_channel::~Msc_channel() 575 { 576 } 577 578 // Utility methods. 579 // NOTE: Also defined in the CPM abstraction, should be consolidated. 580 581 uint32_t 582 Msc_channel::get_field(uint32_t reg, uint32_t mask, uint8_t shift) 583 { 584 return (_regs[reg] & (mask << shift)) >> shift; 585 } 586 587 void 588 Msc_channel::set_field(uint32_t reg, uint32_t mask, uint8_t shift, uint32_t value) 589 { 590 _regs[reg] = (_regs[reg] & (~(mask << shift))) | ((mask & value) << shift); 591 } 592 593 bool 594 Msc_channel::command_will_write(uint8_t index) 595 { 596 // NOTE: Probably incomplete coverage. 597 598 switch (index) 599 { 600 case Command_write_dat_until_stop: return true; 601 case Command_write_block: return true; 602 case Command_write_multiple_block: return true; 603 case Command_program_cid: return true; 604 case Command_program_csd: return true; 605 case Command_lock_unlock: return true; 606 default: return false; 607 } 608 } 609 610 bool 611 Msc_channel::command_with_data(uint8_t index) 612 { 613 // NOTE: Probably incomplete coverage. 614 615 switch (index) 616 { 617 case Command_read_dat_until_stop: return true; 618 case Command_read_single_block: return true; 619 case Command_read_multiple_block: return true; 620 case Command_write_dat_until_stop: return true; 621 case Command_write_block: return true; 622 case Command_write_multiple_block: return true; 623 case Command_program_cid: return true; 624 case Command_program_csd: return true; 625 case Command_lock_unlock: return true; 626 default: return false; 627 } 628 } 629 630 bool 631 Msc_channel::command_uses_busy(uint8_t index) 632 { 633 // NOTE: Probably incomplete coverage. 634 635 switch (index) 636 { 637 case Command_select_deselect_card: return true; 638 case Command_stop_transmission: return true; 639 default: return false; 640 } 641 } 642 643 uint8_t 644 Msc_channel::get_response_format(uint8_t index) 645 { 646 // NOTE: Probably incomplete coverage. 647 648 switch (index) 649 { 650 // Common commands without response. 651 652 case Command_go_idle_state: return 0; 653 case Command_set_dsr: return 0; 654 case Command_go_inactive_state: return 0; 655 656 // Common commands with response. 657 658 case Command_send_op_cond: return 3; 659 case Command_all_send_cid: return 2; 660 case Command_send_csd: return 2; 661 case Command_send_cid: return 2; 662 663 // SDIO only. 664 665 case Command_io_send_op_cond: return 4; 666 case Command_io_rw_direct: return 5; 667 668 // SDMEM only. 669 670 case Command_send_relative_addr: return 6; 671 case Command_send_if_cond: return 7; 672 673 // All other commands. 674 675 default: return 1; 676 } 677 } 678 679 uint8_t 680 Msc_channel::get_app_response_format(uint8_t index) 681 { 682 // NOTE: Probably incomplete coverage. 683 684 switch (index) 685 { 686 // SDMEM only. 687 688 case App_command_sd_send_op_cond: return 3; 689 690 // All other commands. 691 692 default: return 1; 693 } 694 } 695 696 // Read a response directly from the FIFO. 697 698 void 699 Msc_channel::read_response(uint16_t *buffer, uint8_t units) 700 { 701 uint8_t unit = units; 702 703 while (unit > 0) 704 { 705 uint32_t data = _regs[Msc_response_fifo]; 706 707 // Ignore the upper byte of the last unit in small transfers since it is the 708 // lower byte from the previous unit not shifted out of the register. 709 710 unit--; 711 712 if ((unit == 0) && (units == 3)) 713 buffer[unit] = (data & 0xff) << 8; 714 else 715 buffer[unit] = data; 716 } 717 } 718 719 void 720 Msc_channel::ack_irq(uint32_t flags) 721 { 722 // Clear the flags by setting them. 723 724 _regs[Msc_interrupt_flag] = _regs[Msc_interrupt_flag] | flags; 725 } 726 727 void 728 Msc_channel::unmask_irq(uint32_t flags) 729 { 730 ack_irq(flags); 731 732 if (_regs[Msc_interrupt_mask] & flags) 733 _regs[Msc_interrupt_mask] = _regs[Msc_interrupt_mask] & ~flags; 734 } 735 736 void 737 Msc_channel::reset() 738 { 739 _regs[Msc_control] = _regs[Msc_control] | Control_reset; 740 741 // NOTE: X1600 and other recent SoCs only. 742 743 _regs[Msc_control] = _regs[Msc_control] & ~Control_reset; 744 745 // Sufficient for other SoCs... 746 747 while (_regs[Msc_status] & Status_resetting); 748 } 749 750 void 751 Msc_channel::start_clock() 752 { 753 set_field(Msc_control, Control_clock_control_field_mask, 754 Control_clock_control_field_shift, Control_clock_control_start); 755 756 while (!(_regs[Msc_status] & Status_clock_enabled)); 757 } 758 759 void 760 Msc_channel::stop_clock() 761 { 762 set_field(Msc_control, Control_clock_control_field_mask, 763 Control_clock_control_field_shift, Control_clock_control_stop); 764 765 while (_regs[Msc_status] & Status_clock_enabled); 766 } 767 768 uint32_t 769 Msc_channel::get_status() 770 { 771 return _regs[Msc_status]; 772 } 773 774 // Send an application-specific command. 775 776 bool 777 Msc_channel::send_app_command(uint8_t index, uint32_t arg) 778 { 779 if (!send_command(Command_app_cmd, 0, get_app_response_format(index), 780 false, false, false)) 781 return false; 782 783 return send_command(index, arg); 784 } 785 786 // Send a common MMC/SD command. 787 788 bool 789 Msc_channel::send_command(uint8_t index, uint32_t arg) 790 { 791 return send_command(index, arg, get_response_format(index), 792 command_with_data(index), command_will_write(index), 793 command_uses_busy(index)); 794 } 795 796 // Initiate a command having the given index and using the given argument, 797 // employing the specified response format and involving a data transfer if 798 // indicated. 799 800 bool 801 Msc_channel::send_command(uint8_t index, uint32_t arg, uint8_t response_format, 802 bool data, bool write, bool busy) 803 { 804 stop_clock(); 805 806 // Enable DMA for data transfers. 807 // NOTE: Needed for JZ4780 and later SoCs. 808 809 _regs[Msc_dma_control] = (data ? Dma_select_common_dma | Dma_enable : Dma_disable); 810 811 // Set the command index and argument. 812 813 _regs[Msc_command_index] = index; 814 _regs[Msc_command_argument] = arg; 815 816 // Configure the response format and data bus width. 817 818 set_field(Msc_command_data_control, Cdc_response_format_field_mask, 819 Cdc_response_format_field_shift, response_format); 820 821 // NOTE: May need to set the SD bus width. 822 823 set_field(Msc_command_data_control, Cdc_bus_width_field_mask, 824 Cdc_bus_width_field_shift, Cdc_bus_width_field_1bit); 825 826 set_field(Msc_command_data_control, Cdc_recv_fifo_level_field_mask, 827 Cdc_recv_fifo_level_field_shift, Cdc_fifo_level_16); 828 829 set_field(Msc_command_data_control, Cdc_trans_fifo_level_field_mask, 830 Cdc_trans_fifo_level_field_shift, Cdc_fifo_level_16); 831 832 // Set and clear control bits appropriate to the command. 833 // NOTE: Pre-JZ4780 SoCs enable DMA in this register. 834 835 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] | 836 // (data ? Cdc_dma_enable : Cdc_dma_disable) | 837 (busy ? Cdc_expect_busy : Cdc_do_not_expect_busy) | 838 (data ? Cdc_data_with_command : Cdc_no_data_with_command) | 839 (write ? Cdc_write_operation : Cdc_read_operation); 840 841 _regs[Msc_command_data_control] = _regs[Msc_command_data_control] & 842 ~( 843 // (data ? Cdc_dma_disable : Cdc_dma_enable) | 844 (busy ? Cdc_do_not_expect_busy : Cdc_expect_busy) | 845 (data ? Cdc_no_data_with_command : Cdc_data_with_command) | 846 (write ? Cdc_read_operation : Cdc_write_operation) | 847 Cdc_stream_block | Cdc_init_sequence); 848 849 // Unmask interrupts, start the clock, then initiate the command. 850 851 uint32_t flags = Int_end_command_response | Int_response_timeout; 852 853 unmask_irq(flags); 854 start_clock(); 855 856 _regs[Msc_control] = _regs[Msc_control] | Control_start_operation; 857 858 // Wait for command completion. 859 860 if (!wait_for_irq(flags)) 861 return false; 862 863 // Determine whether a timeout occurred. 864 865 bool have_response = !(_regs[Msc_interrupt_flag] & Int_response_timeout); 866 867 // Acknowledge the interrupts and return the status. 868 869 ack_irq(flags); 870 return have_response; 871 } 872 873 void 874 Msc_channel::enable() 875 { 876 // NOTE: X1600 and other recent SoCs only. 877 878 _regs[Msc_low_power_mode] = _regs[Msc_low_power_mode] & ~Low_power_mode_enable; 879 880 stop_clock(); 881 reset(); 882 883 // Slow the clock for initialisation. 884 // NOTE: Should use the CPM module to deduce the appropriate divider value. 885 886 set_field(Msc_clock_rate, Clock_rate_field_mask, Clock_rate_field_shift, 7); 887 888 send_command(Command_go_idle_state, 0); 889 890 if (check_sd()) 891 { 892 init_sdio(); 893 init_sdmem(); 894 } 895 896 init_mmc(); 897 identify_cards(); 898 query_cards(); 899 900 // Restore the clock. 901 // NOTE: Should use the CPM module to deduce the appropriate divider value. 902 903 set_field(Msc_clock_rate, Clock_rate_field_mask, Clock_rate_field_shift, 1); 904 905 _current_rca = 0; 906 } 907 908 // Check the voltage range of the SD card, potentially establishing that it is 909 // a high capacity card. Return false if the voltage range is incompatible. 910 911 bool 912 Msc_channel::check_sd() 913 { 914 uint16_t buffer[Response_size_R7]; 915 struct R7 *r = (struct R7 *) buffer; 916 917 // Send an interface condition command. 918 // A card may not respond to this command. 919 920 if (!send_command(Command_send_if_cond, If_cond_default_voltage_range)) 921 return true; 922 923 read_response(buffer, Response_size_R7); 924 925 // Reject any card not supporting the default voltage range. 926 927 if (r->check_voltage.raw != If_cond_default_voltage_range) 928 return false; 929 930 return true; 931 } 932 933 // Check the voltage range of the SDIO card, inactivating it if incompatible. 934 935 void 936 Msc_channel::init_sdio() 937 { 938 uint16_t buffer[Response_size_R4]; 939 struct R4 *r = (struct R4 *) buffer; 940 uint32_t ocr = 0; 941 942 // Reset any SDIO card or IO unit in a combined memory/IO card. 943 // A non-SDIO card may not respond to this command. 944 945 if (!send_command(Command_io_rw_direct, Io_rw_direct_reset)) 946 return; 947 948 // Attempt to assert the operating conditions. 949 950 do 951 { 952 // Obtain OCR (operating conditions register) values for any IO card. 953 // Without a response, the card may have inactivated itself due to voltage 954 // range incompatibility reasons. 955 956 if (!send_command(Command_io_send_op_cond, ocr)) 957 return; 958 959 read_response(buffer, Response_size_R4); 960 961 // Finish if no IO functions provided. 962 // NOTE: Should only need to check this the first time. 963 964 if (r->number_io_functions == 0) 965 return; 966 967 if (r->ocr != Ocr_default_voltage_range) 968 { 969 ocr = Ocr_default_voltage_range; 970 continue; 971 } 972 } 973 while (!r->ready); 974 } 975 976 void 977 Msc_channel::init_sdmem() 978 { 979 uint16_t buffer[Response_size_R3]; 980 struct R3 *r = (struct R3 *) buffer; 981 982 // Incorporate the HCS bit into the OCR for SDMEM. 983 984 uint32_t ocr = Ocr_high_capacity_storage; 985 986 do 987 { 988 if (!send_app_command(App_command_sd_send_op_cond, ocr)) 989 return; 990 991 read_response(buffer, Response_size_R3); 992 993 if (r->ocr != Ocr_default_voltage_range) 994 { 995 ocr = Ocr_default_voltage_range | Ocr_high_capacity_storage; 996 continue; 997 } 998 } 999 while (!(r->ocr & Ocr_card_powered_up)); 1000 } 1001 1002 void 1003 Msc_channel::init_mmc() 1004 { 1005 // Obtain OCR (operating conditions register) values for each card using 1006 // send_op_cond command variants without argument, or assert operating 1007 // conditions with argument to avoid handling card responses. Where responses 1008 // are solicited, the host must determine a suitable argument and reissue the 1009 // command. 1010 1011 uint16_t buffer[Response_size_R3]; 1012 struct R3 *r = (struct R3 *) buffer; 1013 uint32_t ocr = 0; 1014 1015 do 1016 { 1017 if (!send_command(Command_send_op_cond, ocr)) 1018 return; 1019 1020 read_response(buffer, Response_size_R3); 1021 1022 if (r->ocr != Ocr_default_voltage_range) 1023 { 1024 ocr = Ocr_default_voltage_range; 1025 continue; 1026 } 1027 } 1028 while (!(r->ocr & Ocr_card_powered_up)); 1029 } 1030 1031 void 1032 Msc_channel::identify_cards() 1033 { 1034 uint16_t buffer[Response_size_R2]; 1035 struct R2 *r = (struct R2 *) buffer; 1036 1037 _cards = 0; 1038 1039 while (send_command(Command_all_send_cid, 0)) 1040 { 1041 read_response(buffer, Response_size_R2); 1042 1043 memcpy(&_cid[_cards], r->payload.raw, sizeof(r->payload.raw)); 1044 1045 printf("card: %d\n", _cards); 1046 printf("date: %d %d\n", r->payload.cid.month, r->payload.cid.year); 1047 printf("serial: %d\n", r->payload.cid.serial); 1048 printf("revision: %d\n", r->payload.cid.revision); 1049 printf("name: %c%c%c%c%c\n", r->payload.cid.name[4], r->payload.cid.name[3], 1050 r->payload.cid.name[2], r->payload.cid.name[1], 1051 r->payload.cid.name[0]); 1052 printf("oem: %d\n", r->payload.cid.oem); 1053 printf("manufacturer: %d\n", r->payload.cid.manufacturer); 1054 1055 // Try and obtain a card-issued address. 1056 1057 if (send_command(Command_send_relative_addr, 0)) 1058 { 1059 uint16_t addr_buffer[Response_size_R6]; 1060 struct R6 *ar = (struct R6 *) addr_buffer; 1061 1062 read_response(addr_buffer, Response_size_R6); 1063 1064 memcpy(&_rca[_cards], &ar->rca, sizeof(ar->rca)); 1065 } 1066 1067 // Try and assign an address. 1068 // Employ 1-based relative addressing. 1069 1070 else if (send_command(Command_set_relative_addr, _cards + 1)) 1071 _rca[_cards] = _cards + 1; 1072 1073 // Otherwise, stop identification. 1074 1075 else 1076 return; 1077 1078 _cards++; 1079 } 1080 } 1081 1082 void 1083 Msc_channel::query_cards() 1084 { 1085 uint16_t buffer[Response_size_R2]; 1086 struct R2 *r = (struct R2 *) buffer; 1087 uint8_t card; 1088 1089 for (card = 0; card < _cards; card++) 1090 { 1091 // Employ 1-based relative addressing. 1092 1093 if (!send_command(Command_send_csd, _rca[card] << 16)) 1094 return; 1095 1096 read_response(buffer, Response_size_R2); 1097 1098 memcpy(&_csd[card], r->payload.raw, sizeof(r->payload.raw)); 1099 1100 printf("card: %d\n", card); 1101 printf("csd: %d\n", r->payload.csd.csd); 1102 printf("copy: %s\n", r->payload.csd.copy ? "copied" : "original"); 1103 printf("card command classes: %03x\n", r->payload.csd.card_command_classes); 1104 printf("device (size multiplier): %d %d\n", r->payload.csd.device_size + 1, 1105 1 << (r->payload.csd.device_size_multiplier + 2)); 1106 printf("device size: %d\n", (1 << r->payload.csd.read_blocklen) * 1107 (r->payload.csd.device_size + 1) * 1108 (1 << (r->payload.csd.device_size_multiplier + 2))); 1109 printf("transfer speed: %d MHz\n", r->payload.csd.tran_speed == 0x32 ? 25 : 50); 1110 printf("format group: %d %d\n", r->payload.csd.format, r->payload.csd.format_group); 1111 printf("write time factor: %d\n", 1 << r->payload.csd.write_time_factor); 1112 printf("write protect (temp perm): %s %s\n", r->payload.csd.temp_write_prot ? "yes" : "no", 1113 r->payload.csd.perm_write_prot ? "yes" : "no"); 1114 printf("write protect group (enable size): %s %d\n", r->payload.csd.write_prot_group_enable ? "yes" : "no", 1115 r->payload.csd.write_prot_group_size + 1); 1116 printf("write block (partial length): %s %d\n", r->payload.csd.write_block_partial ? "yes" : "no", 1117 1 << r->payload.csd.write_blocklen); 1118 printf("read block (partial length): %s %d\n", r->payload.csd.read_block_partial ? "yes" : "no", 1119 1 << r->payload.csd.read_blocklen); 1120 printf("erase: sector single: %d %s\n", r->payload.csd.erase_sector_size + 1, 1121 r->payload.csd.erase_single_block_enable ? "yes" : "no"); 1122 printf("misalign: read write: %s %s\n", r->payload.csd.read_block_misalign ? "yes" : "no", 1123 r->payload.csd.write_block_misalign ? "yes" : "no"); 1124 printf("max read current (min max): %d %d\n", r->payload.csd.max_read_current_min, 1125 r->payload.csd.max_read_current_max); 1126 printf("max write current (min max): %d %d\n", r->payload.csd.max_write_current_min, 1127 r->payload.csd.max_write_current_max); 1128 printf("read access time (1 2): %d %d\n", r->payload.csd.data_read_access_time_1, 1129 r->payload.csd.data_read_access_time_2); 1130 printf("DSR: %s\n", r->payload.csd.dsr_implemented ? "yes" : "no"); 1131 } 1132 } 1133 1134 uint32_t 1135 Msc_channel::recv_data(l4re_dma_space_dma_addr_t paddr, uint32_t count) 1136 { 1137 return transfer(_msc_start + Msc_recv_data_fifo, paddr, true, count); 1138 } 1139 1140 uint32_t 1141 Msc_channel::send_data(l4re_dma_space_dma_addr_t paddr, uint32_t count) 1142 { 1143 return transfer(paddr, _msc_start + Msc_trans_data_fifo, false, count); 1144 } 1145 1146 uint32_t 1147 Msc_channel::read_block(uint8_t card, l4re_dma_space_dma_addr_t paddr) 1148 { 1149 uint32_t block_size = 1 << _csd[card].read_blocklen; 1150 uint16_t buffer[Response_size_R1]; 1151 struct R1 *r = (struct R1 *) buffer; 1152 1153 //printf("read_block: card %d -> %d\n", card, _rca[card]); 1154 1155 // Select the requested card. 1156 1157 if (_current_rca != _rca[card]) 1158 { 1159 if (!send_command(Command_select_deselect_card, _rca[card] << 16)) 1160 return 0; 1161 1162 read_response(buffer, Response_size_R1); 1163 1164 if (r->status & R1_status_error_mask) 1165 return 0; 1166 1167 _current_rca = _rca[card]; 1168 } 1169 1170 #if 0 1171 // NOTE: SMEM cards should allow bus width setting. 1172 // NOTE: SDIO cards have their bus width set in CCCR via CMD52. 1173 1174 printf("set bus width -> %s\n", 1175 send_app_command(App_command_set_bus_width, Bus_width_4bit) ? "set" : "not set"); 1176 #endif 1177 1178 if (!send_command(Command_set_blocklen, block_size)) 1179 return 0; 1180 1181 read_response(buffer, Response_size_R1); 1182 1183 if (r->status & R1_status_error_mask) 1184 return 0; 1185 1186 // Apply block count and size properties to the issued command. 1187 1188 _regs[Msc_block_count] = 1; 1189 _regs[Msc_block_length] = block_size; 1190 1191 // NOTE: Support an actual address. 1192 // NOTE: Where CCS = 0, byte addressing is used. Otherwise, block addressing is used. 1193 1194 if (!send_command(Command_read_single_block, 0)) 1195 return 0; 1196 1197 read_response(buffer, Response_size_R1); 1198 1199 if (r->status & R1_status_error_mask) 1200 return 0; 1201 1202 return recv_data(paddr, block_size); 1203 } 1204 1205 // Wait indefinitely for an interrupt request, returning true if one was delivered. 1206 1207 bool 1208 Msc_channel::wait_for_irq(uint32_t flags) 1209 { 1210 return !l4_error(l4_irq_receive(_irq, L4_IPC_NEVER)) && 1211 (_regs[Msc_interrupt_flag] & flags); 1212 } 1213 1214 // Wait up to the given timeout (in microseconds) for an interrupt request, 1215 // returning true if one was delivered. 1216 1217 bool 1218 Msc_channel::wait_for_irq(uint32_t flags, unsigned int timeout) 1219 { 1220 return !l4_error(l4_irq_receive(_irq, l4_timeout(L4_IPC_TIMEOUT_NEVER, 1221 l4util_micros2l4to(timeout)))) && 1222 (_regs[Msc_interrupt_flag] & flags); 1223 } 1224 1225 1226 1227 // Peripheral abstraction. 1228 1229 Msc_chip::Msc_chip(l4_addr_t msc_start, l4_addr_t start, l4_addr_t end) 1230 : _msc_start(msc_start), _start(start), _end(end) 1231 { 1232 }