1 /* 2 * I2C support for the JZ4780 and X1600. 3 * 4 * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-common.h> 23 24 #include <l4/sys/icu.h> 25 #include <l4/util/util.h> 26 #include <sys/time.h> 27 28 29 30 /* NOTE: The X1600 is very similar to the JZ4780 with the registers 31 renamed to I2C from SMB, with a few high speed registers, the 32 I2C_RINTST, I2C_TXFLR and I2C_RXFLR registers, and a few other 33 registers added, with I2C_SDAHD appearing at a different location. */ 34 35 enum Regs 36 { 37 I2c_control = 0x000, // I2C_CON 38 I2c_target_address = 0x004, // I2C_TAR 39 I2c_slave_address = 0x008, // I2C_SAR 40 I2c_master_code = 0x00c, // I2C_HS_MADDR 41 I2c_data_command = 0x010, // I2C_DC 42 Std_high_count = 0x014, // I2C_SHCNT 43 Std_low_count = 0x018, // I2C_SLCNT 44 Fast_high_count = 0x01c, // I2C_FHCNT 45 Fast_low_count = 0x020, // I2C_FLCNT 46 Int_status = 0x02c, // I2C_INTST (read-only) 47 Int_mask = 0x030, // I2C_INTM 48 Rx_fifo_thold = 0x038, // I2C_RXTL 49 Tx_fifo_thold = 0x03c, // I2C_TXTL 50 Int_combined_clear = 0x040, // I2C_CINT (read-only) 51 Int_rx_uf_clear = 0x044, // I2C_CRXUF (read-only) 52 Int_rx_of_clear = 0x048, // I2C_CRXOF (read-only) 53 Int_tx_of_clear = 0x04c, // I2C_CTXOF (read-only) 54 Int_rd_req_clear = 0x050, // I2C_CRXREQ (read-only) 55 Int_tx_abort_clear = 0x054, // I2C_CTXABT (read-only) 56 Int_rx_done_clear = 0x058, // I2C_CRXDN (read-only) 57 Int_activity_clear = 0x05c, // I2C_CACT (read-only) 58 Int_stop_clear = 0x060, // I2C_CSTP (read-only) 59 Int_start_clear = 0x064, // I2C_CSTT (read-only) 60 Int_call_clear = 0x068, // I2C_CGC (read-only) 61 I2c_enable = 0x06c, // I2C_ENB 62 I2c_status = 0x070, // I2C_ST (read-only) 63 I2c_sda_hold_time = 0x07c, // I2C_SDAHD 64 Trans_abort_status = 0x080, // I2C_ABTSRC (read-only) 65 I2c_dma_ctrl = 0x088, // I2C_DMACR 66 I2c_trans_data_lvl = 0x08c, // I2C_DMATDLR 67 I2c_recv_data_lvl = 0x090, // I2C_DMARDLR 68 I2c_sda_setup_time = 0x094, // I2C_SDASU 69 I2c_ack_call = 0x098, // I2C_ACKGC 70 I2c_enable_status = 0x09c, // I2C_ENBST (read-only) 71 72 // JZ4780 variation... 73 74 I2c_sda_hold_time_jz4780 = 0x0d0, // I2C_SDAHD 75 76 // X1600 only... 77 78 High_high_count = 0x024, // I2C_HHCNT 79 High_low_count = 0x028, // I2C_HLCNT 80 Int_raw_status = 0x034, // I2C_RINTST (read-only) 81 Tx_fifo_count = 0x074, // I2C_TXFLR (read-only) 82 Rx_fifo_count = 0x078, // I2C_RXFLR (read-only) 83 Slv_data_nack = 0x084, // I2CSDNACK 84 I2c_spike_suppress = 0x0a0, // I2C_FSPKLEN 85 86 // Register block spacing. 87 88 I2c_block_offset = 0x1000 89 }; 90 91 enum I2c_control_bits : unsigned 92 { 93 I2c_stop_hold = 0x80, // STPHLD (JZ4780 only) 94 I2c_no_stop_hold = 0x00, // absent STPHLD field 95 96 I2c_disable_slave = 0x40, // SLVDIS (slave disabled) 97 I2c_enable_restart = 0x20, // RESTART 98 I2c_master_10bit = 0x10, // MATP (read-only) 99 I2c_slave_10bit = 0x08, // SATP 100 I2c_speed_mode_mask = 0x06, // SPEED 101 I2c_enable_master = 0x01, // MD (master enabled) 102 I2c_speed_bit = 1, // SPD 103 }; 104 105 enum I2c_speed_mode_values : unsigned 106 { 107 I2c_speed_standard = 1, 108 I2c_speed_fast = 2, 109 110 // X1600 only... 111 112 I2c_speed_high = 3, 113 }; 114 115 enum I2c_enable_bits : unsigned 116 { 117 I2c_enable_enabled = 0x01, // I2CEN 118 }; 119 120 enum I2c_status_bits : unsigned 121 { 122 I2c_status_master_act = 0x20, // MSTACT (master active) 123 I2c_status_rx_nempty = 0x08, // RFNE (read queue not empty) 124 I2c_status_tx_empty = 0x04, // TFE (write queue empty) 125 I2c_status_tx_nfull = 0x02, // TFNF (write queue not full) 126 I2c_status_active = 0x01, // ACT (device active as master or slave) 127 }; 128 129 enum I2c_target_bits : unsigned 130 { 131 I2c_target_master_10bit = 0x1000, 132 I2c_target_special = 0x0800, // SPECIAL: perform general call or start byte 133 I2c_target_start_byte = 0x0400, // Special: start byte (1) or general call (0) 134 I2c_target_10bits = 0x3ff, // Mask for 10-bit address 135 I2c_target_7bits = 0x7f, // Mask for 7-bit address 136 }; 137 138 enum I2c_hold_control_bits : unsigned 139 { 140 // JZ4780... 141 142 I2c_hold_enable = 0x100, // HDENB 143 I2c_hold_disable = 0x000, // HDENB 144 I2c_hold_mask_jz4780 = 0xff, 145 146 // The X1600 loses the hold enable flag and widens the hold time field. 147 148 I2c_hold_mask = 0xffff, 149 }; 150 151 enum I2c_setup_control_bits : unsigned 152 { 153 I2c_setup_mask = 0x0ff, // SDASU 154 }; 155 156 enum I2c_command_bits : unsigned 157 { 158 // X1600 only... 159 160 I2c_command_restart = 0x400, // RESTART: explicit restart before next byte 161 I2c_command_stop = 0x200, // STOP: explicit stop after next byte 162 I2c_command_no_stop = 0x000, 163 164 // Common fields. 165 166 I2c_command_read = 0x100, // CMD 167 I2c_command_write = 0x000, // CMD 168 }; 169 170 enum I2c_fifo_bits : unsigned 171 { 172 I2c_fifo_limit = 64, // RXTL, TXTL (256 noted in field description) 173 }; 174 175 enum Int_bits : unsigned 176 { 177 Int_call = 0x800, // IGC (general call received) 178 Int_start = 0x400, // ISTT (start/restart condition occurred) 179 Int_stop = 0x200, // ISTP (stop condition occurred) 180 Int_activity = 0x100, // IACT (bus activity interrupt) 181 Int_rx_done = 0x080, // RXDN (read from master device done) 182 Int_tx_abort = 0x040, // TXABT (transmit abort) 183 Int_rd_req = 0x020, // RDREQ (read request from master device) 184 Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) 185 Int_tx_of = 0x008, // TXOF (overflow when writing to queue) 186 Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) 187 Int_rx_of = 0x002, // RXOF (overflow from device) 188 Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) 189 }; 190 191 192 193 // Initialise a channel. 194 195 I2c_channel::I2c_channel(l4_addr_t start, 196 enum Clock_identifiers clock, 197 Cpm_chip *cpm, 198 uint32_t frequency) 199 : _clock(clock), _cpm(cpm), _frequency(frequency) 200 { 201 _regs = new Hw::Mmio_register_block<32>(start); 202 _cpm->start_clock(clock); 203 } 204 205 // Enable the channel. 206 207 void 208 I2c_channel::enable() 209 { 210 _regs[I2c_enable] = I2c_enable_enabled; 211 while (!(_regs[I2c_enable_status] & I2c_enable_enabled)); 212 } 213 214 // Disable the channel. 215 216 void 217 I2c_channel::disable() 218 { 219 _regs[I2c_enable] = 0; 220 while (_regs[I2c_enable_status] & I2c_enable_enabled); 221 } 222 223 // Return the configured frequency. 224 225 uint32_t 226 I2c_channel::get_frequency() 227 { 228 return _frequency; 229 } 230 231 // Set the frequency-related peripheral parameters. 232 233 void 234 I2c_channel::set_frequency() 235 { 236 // The I2C device clock is known as I2C_DEV_CLK here and is scaled to kHz in 237 // order to keep the numbers easily representable, as is the bus frequency. 238 239 uint32_t i2c_dev_clk = _cpm->get_frequency(_clock) / 1000; 240 241 // Note that this is not I2C_DEV_CLK but the actual I2C bus frequency. 242 243 uint32_t i2c_clk = _frequency / 1000; 244 245 // Select the appropriate speed. 246 247 unsigned int speed = (i2c_clk <= 100) ? I2c_speed_standard : 248 (!high_speed_mode() || (i2c_clk <= 400)) ? I2c_speed_fast : 249 I2c_speed_high; 250 251 // NOTE: Permit broader configuration elsewhere. 252 253 _regs[I2c_control] = (speed << I2c_speed_bit) | 254 I2c_disable_slave | 255 I2c_enable_restart | 256 I2c_enable_master | 257 (stop_hold() ? I2c_stop_hold : I2c_no_stop_hold); 258 259 // According to the programming manual, if the device clock period is 260 // T{I2C_DEV_CLK} then the I2C clock period is... 261 262 // T{SCL} = T{SCL_high} + T{SCL_low} 263 264 // Where... 265 266 // T{SCL_low} = T{I2C_DEV_CLK} * (#cycles for low signal) 267 // T{SCL_high} = T{I2C_DEV_CLK} * (#cycles for high signal) 268 269 // Since, with minimum periods being defined... 270 271 // T{SCL} >= T{min_SCL} 272 // T{SCL_low} >= T{min_SCL_low} 273 // T{SCL_high} >= T{min_SCL_high} 274 // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} 275 276 // Then the following applies... 277 278 // T{I2C_DEV_CLK} * (#cycles for low signal)) >= T{min_SCL_low} 279 // T{I2C_DEV_CLK} * (#cycles for high signal) >= T{min_SCL_high} 280 281 // To work with different clock speeds while maintaining the low-to-high 282 // ratios: 283 284 // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} 285 // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) 286 287 // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} 288 // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) 289 290 // Constraints are given with respect to the high and low count registers. 291 292 // #cycles for high signal = I2CxHCNT + 8 293 // #cycles for low signal = I2CxLCNT + 1 294 295 // From earlier, this yields... 296 297 // T{I2C_DEV_CLK} * (I2CxLCNT + 1) >= T{min_SCL_low} 298 // T{I2C_DEV_CLK} * (I2CxHCNT + 8) >= T{min_SCL_high} 299 300 // Rearranging... 301 302 // I2CxLCNT >= (T{min_SCL_low} / T{I2C_DEV_CLK}) - 1 303 // >= T{min_SCL_low} * I2C_DEV_CLK - 1 304 305 // I2CxHCNT >= (T{min_SCL_high} / T{I2C_DEV_CLK}) - 8 306 // >= T{min_SCL_high} * I2C_DEV_CLK - 8 307 308 // Introducing the definitions for the high and low periods... 309 310 // I2CxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 1 311 // >= (T{min_SCL_low} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 1 312 313 // I2CxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 8 314 // >= (T{min_SCL_high} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 8 315 316 uint32_t high_reg, low_reg; 317 uint32_t high_count, low_count; 318 319 // Level hold times: 320 321 // Standard Fast High 322 // SCL low 4.7us 1.3us 0.5us 323 // SCL high 4.0us 0.6us 0.26us + 324 // SCL period 8.7us 1.9us 0.76us = 325 326 // See: UM10204 "I2C-bus specification and user manual" 327 // Table 10: t{LOW} and t{HIGH} 328 329 if (i2c_clk <= 100) // 100 kHz 330 { 331 low_count = (i2c_dev_clk * 47) / (i2c_clk * 87) - 1; 332 high_count = (i2c_dev_clk * 40) / (i2c_clk * 87) - 8; 333 low_reg = Std_low_count; 334 high_reg = Std_high_count; 335 } 336 else if (!high_speed_mode() || (i2c_clk <= 400)) // 400 kHz 337 { 338 low_count = (i2c_dev_clk * 13) / (i2c_clk * 19) - 1; 339 high_count = (i2c_dev_clk * 6) / (i2c_clk * 19) - 8; 340 low_reg = Fast_low_count; 341 high_reg = Fast_high_count; 342 } 343 else // > 400 kHz 344 { 345 // Note how the frequencies are scaled to accommodate the extra precision 346 // required. 347 348 low_count = (i2c_dev_clk / 10 * 50) / (i2c_clk / 10 * 76) - 1; 349 high_count = (i2c_dev_clk / 10 * 26) / (i2c_clk / 10 * 76) - 8; 350 low_reg = High_low_count; 351 high_reg = High_high_count; 352 } 353 354 // Minimum counts are 8 and 6 for low and high respectively. 355 356 _regs[low_reg] = low_count < 8 ? 8 : low_count; 357 _regs[high_reg] = high_count < 6 ? 6 : high_count; 358 359 // Data hold and setup times: 360 361 // Standard Fast High 362 // t{HD;DAT} 300ns 300ns 300ns 363 // t{SU;DAT} 250ns 100ns 50ns 364 365 // See: UM10204 "I2C-bus specification and user manual" 366 // Table 10: t{HD;DAT} and t{SU;DAT}, also note [3] 367 368 // T{delay} = (I2CSDAHD + 2) * T{I2C_DEV_CLK} 369 // I2CSDAHD = T{delay} / T{I2C_DEV_CLK} - 2 370 // I2CSDAHD = I2C_DEV_CLK * T{delay} - 2 371 372 // Since the device clock is in kHz (scaled down by 1000) and the times are 373 // given in ns (scaled up by 1000000000), a division of 1000000 is introduced. 374 375 int32_t hold_count = (i2c_dev_clk * 300) / 1000000 - 1; 376 uint32_t hold_mask = (uint32_t) (hold_enable() ? I2c_hold_mask_jz4780 : I2c_hold_mask); 377 uint32_t hold_reg = hold_enable() ? I2c_sda_hold_time_jz4780 : I2c_sda_hold_time; 378 379 _regs[hold_reg] = ((hold_count >= 0) && hold_enable() ? I2c_hold_enable : I2c_hold_disable) | 380 (hold_count < 0 ? 0 : 381 (uint32_t) hold_count < hold_mask ? (uint32_t) hold_count : hold_mask); 382 383 // I2C_SDASU is apparently not used in master mode. 384 385 // T{delay} = (I2CSDASU - 1) * T{I2C_DEV_CLK} 386 // I2CSDASU = T{delay} / T{I2C_DEV_CLK} + 1 387 // I2CSDASU = I2C_DEV_CLK * T{delay} + 1 388 389 uint32_t setup_count; 390 391 if (i2c_clk <= 100) 392 setup_count = (i2c_dev_clk * 250) / 1000000 + 1; 393 else if (!high_speed_mode() || (i2c_clk <= 400)) 394 setup_count = (i2c_dev_clk * 100) / 1000000 + 1; 395 else 396 setup_count = (i2c_dev_clk * 50) / 1000000 + 1; 397 398 _regs[I2c_sda_setup_time] = (setup_count < I2c_setup_mask ? setup_count : I2c_setup_mask); 399 } 400 401 // Set the target address and enable transfer. 402 // NOTE: Only supporting 7-bit addresses currently. 403 404 void 405 I2c_channel::set_target(uint8_t address) 406 { 407 disable(); 408 set_frequency(); 409 _regs[I2c_target_address] = address & I2c_target_7bits; 410 init_parameters(); 411 enable(); 412 } 413 414 415 416 // Reset interrupt flags upon certain conditions. 417 418 void 419 I2c_channel::reset_flags() 420 { 421 volatile uint32_t r; 422 423 _regs[Int_mask] = 0; 424 425 // Read from the register to clear interrupts. 426 427 r = _regs[Int_combined_clear]; 428 (void) r; 429 } 430 431 // Initialise interrupt flags and queue thresholds for reading and writing. 432 433 void 434 I2c_channel::init_parameters() 435 { 436 // Handle read queue conditions for data, write queue conditions for commands. 437 438 reset_flags(); 439 440 _regs[Tx_fifo_thold] = 0; // write when 0 in queue 441 } 442 443 444 445 // Return whether the device is active. 446 447 int 448 I2c_channel::active() 449 { 450 return _regs[I2c_status] & I2c_status_master_act; 451 } 452 453 // Return whether data is available to receive. 454 455 int 456 I2c_channel::have_input() 457 { 458 return _regs[I2c_status] & I2c_status_rx_nempty; 459 } 460 461 // Return whether data is queued for sending. 462 463 int 464 I2c_channel::have_output() 465 { 466 return !(_regs[I2c_status] & I2c_status_tx_empty); 467 } 468 469 // Return whether data can be queued for sending. 470 471 int 472 I2c_channel::can_send() 473 { 474 return _regs[I2c_status] & I2c_status_tx_nfull; 475 } 476 477 // Return whether a receive operation has failed. 478 479 int 480 I2c_channel::read_failed() 481 { 482 return _regs[Int_status] & Int_rx_of; 483 } 484 485 // Return whether a send operation has failed. 486 487 int 488 I2c_channel::write_failed() 489 { 490 return _regs[Int_status] & Int_tx_abort; 491 } 492 493 int 494 I2c_channel::read_done() 495 { 496 return _pos == _total; 497 } 498 499 int 500 I2c_channel::write_done() 501 { 502 return (_reqpos == _total) && !have_output(); 503 } 504 505 unsigned 506 I2c_channel::have_read() 507 { 508 return _pos; 509 } 510 511 unsigned 512 I2c_channel::have_written() 513 { 514 return _reqpos; 515 } 516 517 int 518 I2c_channel::failed() 519 { 520 return _fail; 521 } 522 523 524 525 // Handle differences in stop condition management, producing the stop command 526 // field for the X1600. 527 528 uint32_t 529 I2c_channel::stop_command() 530 { 531 if (stop_hold()) 532 return 0; 533 534 return _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 535 } 536 537 // Send read commands for empty queue entries. 538 539 void 540 I2c_channel::queue_reads() 541 { 542 unsigned int remaining = _total - _reqpos; 543 unsigned int queued = _reqpos - _pos; 544 unsigned int can_queue = I2c_fifo_limit - queued; 545 546 // Keep the number of reads in progress below the length of the read queue. 547 548 if (!can_queue) 549 return; 550 551 // At most, only queue as many reads as are remaining. 552 553 if (remaining < can_queue) 554 can_queue = remaining; 555 556 // Queue read requests for any remaining queue entries. 557 558 while (can_queue && can_send()) 559 { 560 _regs[I2c_data_command] = I2c_command_read | stop_command(); 561 _reqpos++; 562 can_queue--; 563 } 564 565 /* Extra read request on JZ4780. */ 566 567 if (stop_hold() && _stop) 568 stop(); 569 570 // Update the threshold to be notified of any reduced remaining amount. 571 572 set_read_threshold(); 573 } 574 575 // Send write commands for empty queue entries. 576 577 void 578 I2c_channel::queue_writes() 579 { 580 unsigned int remaining = _total - _reqpos; 581 unsigned int can_queue = I2c_fifo_limit; 582 583 if (remaining < can_queue) 584 can_queue = remaining; 585 586 // Queue write requests for any remaining queue entries. 587 588 while (can_queue && can_send()) 589 { 590 _regs[I2c_data_command] = I2c_command_write | _buf[_reqpos] | stop_command(); 591 _reqpos++; 592 can_queue--; 593 } 594 } 595 596 // Store read command results from the queue. 597 598 void 599 I2c_channel::store_reads() 600 { 601 // Read any input and store it in the buffer. 602 603 while (have_input() && (_pos < _reqpos)) 604 { 605 _buf[_pos] = _regs[I2c_data_command] & 0xff; 606 _pos++; 607 } 608 } 609 610 void 611 I2c_channel::set_read_threshold() 612 { 613 unsigned int queued = _reqpos - _pos; 614 615 if (!queued) 616 return; 617 618 // Read all expected. 619 620 _regs[Rx_fifo_thold] = queued - 1; 621 } 622 623 // Read from the target device. 624 625 void 626 I2c_channel::start_read(uint8_t buf[], unsigned int total, int stop) 627 { 628 _buf = buf; 629 _total = total; 630 _pos = 0; 631 _reqpos = 0; 632 _fail = 0; 633 _stop = stop; 634 635 reset_flags(); 636 637 _regs[Int_mask] = Int_rx_full | // read condition (reading needed) 638 Int_rx_of | // abort condition 639 Int_tx_abort; // general abort condition 640 641 // Perform initial read requests. 642 643 read(); 644 } 645 646 void 647 I2c_channel::read() 648 { 649 // Test for the general transfer abort condition. 650 651 if (read_failed() || write_failed()) 652 { 653 _fail = 1; 654 _regs[Int_mask] = 0; 655 disable(); 656 enable(); 657 return; 658 } 659 660 if (_regs[Int_status] & Int_rx_full) 661 store_reads(); 662 663 // Always attempt to queue more read requests. 664 665 queue_reads(); 666 } 667 668 // Write to the target device. 669 670 void 671 I2c_channel::start_write(uint8_t buf[], unsigned int total, int stop) 672 { 673 _buf = buf; 674 _total = total; 675 _reqpos = 0; 676 _fail = 0; 677 _stop = stop; 678 679 reset_flags(); 680 681 // Enable interrupts for further writes. 682 683 _regs[Int_mask] = Int_tx_empty | // write condition (writing needed) 684 Int_tx_abort; // abort condition 685 686 // Perform initial writes. 687 688 write(); 689 } 690 691 void 692 I2c_channel::write() 693 { 694 if (write_failed()) 695 { 696 _fail = 1; 697 _regs[Int_mask] = 0; 698 disable(); 699 enable(); 700 return; 701 } 702 703 if (_regs[Int_status] & Int_tx_empty) 704 queue_writes(); 705 } 706 707 // Explicitly stop communication. 708 709 void 710 I2c_channel::stop() 711 { 712 _regs[I2c_control] = _regs[I2c_control] & ~I2c_stop_hold; 713 } 714 715 716 717 // Initialise the I2C controller. 718 719 I2c_chip::I2c_chip(l4_addr_t start, l4_addr_t end, 720 Cpm_chip *cpm, 721 uint32_t frequency) 722 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 723 { 724 } 725 726 // Obtain a channel object. 727 728 I2c_channel * 729 I2c_chip::get_channel(uint8_t channel) 730 { 731 l4_addr_t block = _start + channel * I2c_block_offset; 732 733 // NOTE: Defining all the possible clocks. 734 735 enum Clock_identifiers clocks[] = {Clock_i2c0, Clock_i2c1, Clock_i2c2, Clock_i2c3, Clock_i2c4}; 736 737 if (channel < num_channels()) 738 return _get_channel(block, clocks[channel], _cpm, _frequency); 739 else 740 throw -L4_EINVAL; 741 }