# HG changeset patch # User Paul Boddie # Date 1698448545 -7200 # Node ID 398898e77d36cc5269502a4729761b66f978d8d2 # Parent f1df79717f9e53408ae4eaf860c626793525be90 Adopted a 64-bit frequency type. Fixed PLL update operations. Added the VPU clock for the JZ4780. diff -r f1df79717f9e -r 398898e77d36 pkg/devices/include/clocks.h --- a/pkg/devices/include/clocks.h Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/devices/include/clocks.h Sat Oct 28 01:15:45 2023 +0200 @@ -90,6 +90,7 @@ Clock_udc, Clock_uhc, Clock_uprt, + Clock_vpu, Clock_identifier_count, /* not a clock: limit for array definition */ Clock_undefined, /* not a clock: special value */ }; diff -r f1df79717f9e -r 398898e77d36 pkg/devices/lib/cpm/include/cpm-common.h --- a/pkg/devices/lib/cpm/include/cpm-common.h Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/devices/lib/cpm/include/cpm-common.h Sat Oct 28 01:15:45 2023 +0200 @@ -161,7 +161,7 @@ // Clock source frequency. - uint32_t get_frequency(Cpm_regs ®s); + uint64_t get_frequency(Cpm_regs ®s); }; @@ -227,6 +227,10 @@ { Field _enable, _stable, _bypass; + // Frequency change sequence state. + + bool _enabled = false; + // PLL_specific control. int have_pll(Cpm_regs ®s); @@ -245,6 +249,9 @@ void pll_bypass(Cpm_regs ®s); void pll_engage(Cpm_regs ®s); + void change_disable(Cpm_regs ®s); + void change_enable(Cpm_regs ®s); + void wait_busy(Cpm_regs ®s); int have_clock(Cpm_regs ®s); void start_clock(Cpm_regs ®s); @@ -262,8 +269,8 @@ // Output frequency. - virtual uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency) = 0; - virtual int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) = 0; + virtual uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency) = 0; + virtual int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) = 0; // Other operations. @@ -298,8 +305,8 @@ // Output frequency. - uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); - int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); + uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency); + int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency); // Other operations. @@ -351,8 +358,8 @@ // Output frequency. - uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); - int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); + uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency); + int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency); // Other operations. @@ -384,8 +391,8 @@ // Output frequency. - uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency); - int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency); + uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency); + int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency); // Other operations. @@ -413,7 +420,7 @@ // Output frequency. - virtual uint32_t get_frequency(Cpm_regs ®s) = 0; + virtual uint64_t get_frequency(Cpm_regs ®s) = 0; }; @@ -433,7 +440,7 @@ // Output frequency. - uint32_t get_frequency(Cpm_regs ®s); + uint64_t get_frequency(Cpm_regs ®s); }; @@ -443,10 +450,10 @@ class Clock_passive : public Clock_base { protected: - uint32_t _frequency; + uint64_t _frequency; public: - explicit Clock_passive(uint32_t frequency) + explicit Clock_passive(uint64_t frequency) : _frequency(frequency) { } @@ -461,7 +468,7 @@ // Output frequency. - uint32_t get_frequency(Cpm_regs ®s); + uint64_t get_frequency(Cpm_regs ®s); }; @@ -506,11 +513,11 @@ // Clock source frequency. - virtual uint32_t get_source_frequency(Cpm_regs ®s); + virtual uint64_t get_source_frequency(Cpm_regs ®s); // Output frequency. - virtual uint32_t get_frequency(Cpm_regs ®s); + virtual uint64_t get_frequency(Cpm_regs ®s); }; @@ -535,8 +542,8 @@ // Output frequency. - uint32_t get_frequency(Cpm_regs ®s); - virtual int set_frequency(Cpm_regs ®s, uint32_t frequency); + virtual uint64_t get_frequency(Cpm_regs ®s); + virtual int set_frequency(Cpm_regs ®s, uint64_t frequency); }; @@ -563,8 +570,8 @@ // Output frequency. - uint32_t get_frequency(Cpm_regs ®s); - int set_frequency(Cpm_regs ®s, uint32_t frequency); + uint64_t get_frequency(Cpm_regs ®s); + int set_frequency(Cpm_regs ®s, uint64_t frequency); }; diff -r f1df79717f9e -r 398898e77d36 pkg/devices/lib/cpm/include/cpm-jz4780.h --- a/pkg/devices/lib/cpm/include/cpm-jz4780.h Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/devices/lib/cpm/include/cpm-jz4780.h Sat Oct 28 01:15:45 2023 +0200 @@ -63,9 +63,9 @@ enum Clock_identifiers jz4780_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock); void jz4780_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source); -uint32_t jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock); +uint64_t jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock); -uint32_t jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock); -int jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency); +uint64_t jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock); +int jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency); EXTERN_C_END diff -r f1df79717f9e -r 398898e77d36 pkg/devices/lib/cpm/include/cpm-x1600.h --- a/pkg/devices/lib/cpm/include/cpm-x1600.h Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/devices/lib/cpm/include/cpm-x1600.h Sat Oct 28 01:15:45 2023 +0200 @@ -63,9 +63,9 @@ enum Clock_identifiers x1600_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock); void x1600_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source); -uint32_t x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock); +uint64_t x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock); -uint32_t x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock); -int x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency); +uint64_t x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock); +int x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency); EXTERN_C_END diff -r f1df79717f9e -r 398898e77d36 pkg/devices/lib/cpm/src/common.cc --- a/pkg/devices/lib/cpm/src/common.cc Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/devices/lib/cpm/src/common.cc Sat Oct 28 01:15:45 2023 +0200 @@ -128,7 +128,7 @@ // Clock source frequencies. -uint32_t +uint64_t Source::get_frequency(Cpm_regs ®s) { enum Clock_identifiers input = get_source_clock(regs); @@ -266,8 +266,29 @@ void Control_pll::wait_busy(Cpm_regs ®s) { - if (pll_enabled(regs) && !pll_bypassed(regs)) - while (!have_pll(regs)); + // NOTE: Could wait for some kind of stable or "lock" signal, but the chips + // provide all sorts of differing signals. + + (void) regs; +} + +void +Control_pll::change_disable(Cpm_regs ®s) +{ + if (_enabled) + start_clock(regs); +} + +void +Control_pll::change_enable(Cpm_regs ®s) +{ + // NOTE: Since the X1600 manual warns of changing the frequency while enabled, + // it is easier to just stop and then start the PLL again. + + _enabled = have_clock(regs); + + if (_enabled) + stop_clock(regs); } @@ -298,14 +319,14 @@ // Output clock frequencies. -uint32_t -Divider::get_frequency(Cpm_regs ®s, uint32_t source_frequency) +uint64_t +Divider::get_frequency(Cpm_regs ®s, uint64_t source_frequency) { return source_frequency / get_divider(regs); } int -Divider::set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) +Divider::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) { set_divider(regs, (uint32_t) round((double) source_frequency / (double) frequency)); return 1; @@ -464,15 +485,15 @@ _output_divider1.set_field(regs, d1); } -uint32_t -Divider_pll::get_frequency(Cpm_regs ®s, uint32_t source_frequency) +uint64_t +Divider_pll::get_frequency(Cpm_regs ®s, uint64_t source_frequency) { return (source_frequency * get_multiplier(regs)) / (get_input_divider(regs) * get_output_divider(regs)); } int -Divider_pll::set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) +Divider_pll::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) { double intermediate_multiplier, intermediate_input_divider; uint32_t output_min, output_max, output0, output1; @@ -515,7 +536,7 @@ // output frequency to obtain an intermediate frequency using the proposed // divider. - uint32_t intermediate_frequency = frequency * output_divider; + double intermediate_frequency = frequency * output_divider; // Calculate the required multiplier and divider. @@ -595,8 +616,8 @@ return _divider_D.get_field(regs); } -uint32_t -Divider_i2s::get_frequency(Cpm_regs ®s, uint32_t source_frequency) +uint64_t +Divider_i2s::get_frequency(Cpm_regs ®s, uint64_t source_frequency) { /* NOTE: Assuming that this is the formula, given that the manual does not really describe how D is used. */ @@ -606,7 +627,7 @@ } int -Divider_i2s::set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) +Divider_i2s::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) { double m, n; @@ -718,7 +739,7 @@ // Output clock frequencies. -uint32_t +uint64_t Clock_null::get_frequency(Cpm_regs ®s) { (void) regs; @@ -750,7 +771,7 @@ // Output clock frequencies. -uint32_t +uint64_t Clock_passive::get_frequency(Cpm_regs ®s) { (void) regs; @@ -818,7 +839,7 @@ // Clock source frequencies. -uint32_t +uint64_t Clock_active::get_source_frequency(Cpm_regs ®s) { return _source.get_frequency(regs); @@ -826,7 +847,7 @@ // Output clock frequencies. -uint32_t +uint64_t Clock_active::get_frequency(Cpm_regs ®s) { return get_source_frequency(regs); @@ -842,14 +863,14 @@ // Output clock frequencies. -uint32_t +uint64_t Clock_divided_base::get_frequency(Cpm_regs ®s) { return _get_divider().get_frequency(regs, get_source_frequency(regs)); } int -Clock_divided_base::set_frequency(Cpm_regs ®s, uint32_t frequency) +Clock_divided_base::set_frequency(Cpm_regs ®s, uint64_t frequency) { _get_control().change_enable(regs); int result = _get_divider().set_frequency(regs, get_source_frequency(regs), frequency); @@ -884,7 +905,7 @@ { } -uint32_t +uint64_t Pll::get_frequency(Cpm_regs ®s) { if (!_control.pll_bypassed(regs)) @@ -894,7 +915,7 @@ } int -Pll::set_frequency(Cpm_regs ®s, uint32_t frequency) +Pll::set_frequency(Cpm_regs ®s, uint64_t frequency) { int result = Clock_divided_base::set_frequency(regs, frequency); _control.pll_engage(regs); diff -r f1df79717f9e -r 398898e77d36 pkg/devices/lib/cpm/src/jz4780.cc --- a/pkg/devices/lib/cpm/src/jz4780.cc Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Sat Oct 28 01:15:45 2023 +0200 @@ -426,9 +426,11 @@ clock_uhc(Source(mux_usb, Clock_source_uhc), Control(Clock_gate_uhc, Clock_change_enable_uhc, Clock_busy_uhc), - Divider(Clock_divider_uhc)); + Divider(Clock_divider_uhc)), - + clock_vpu(Source(mux_core, Clock_source_vpu), + Control(Clock_gate_vpu, Clock_change_enable_vpu, Clock_busy_vpu), + Divider(Clock_divider_vpu)); const double jz4780_pll_intermediate_min = 300000000, jz4780_pll_intermediate_max = 1500000000; @@ -525,6 +527,7 @@ &clock_none, // Clock_udc &clock_uhc, &clock_none, // Clock_uprt + &clock_vpu, }; @@ -600,20 +603,20 @@ static_cast(cpm)->set_source_clock(clock, source); } -uint32_t +uint64_t jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) { return static_cast(cpm)->get_source_frequency(clock); } -uint32_t +uint64_t jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) { return static_cast(cpm)->get_frequency(clock); } int -jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) +jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency) { return static_cast(cpm)->set_frequency(clock, frequency); } diff -r f1df79717f9e -r 398898e77d36 pkg/devices/lib/cpm/src/x1600.cc --- a/pkg/devices/lib/cpm/src/x1600.cc Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/devices/lib/cpm/src/x1600.cc Sat Oct 28 01:15:45 2023 +0200 @@ -463,6 +463,7 @@ &clock_none, // Clock_udc &clock_none, // Clock_uhc &clock_none, // Clock_uprt + &clock_none, // Clock_vpu }; @@ -544,20 +545,20 @@ static_cast(cpm)->set_source_clock(clock, source); } -uint32_t +uint64_t x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock) { return static_cast(cpm)->get_source_frequency(clock); } -uint32_t +uint64_t x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock) { return static_cast(cpm)->get_frequency(clock); } int -x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency) +x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency) { return static_cast(cpm)->set_frequency(clock, frequency); } diff -r f1df79717f9e -r 398898e77d36 pkg/landfall-examples/ci20_cpm/ci20_cpm.c --- a/pkg/landfall-examples/ci20_cpm/ci20_cpm.c Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/landfall-examples/ci20_cpm/ci20_cpm.c Sat Oct 28 01:15:45 2023 +0200 @@ -1,7 +1,7 @@ /* * (c) 2008-2009 Adam Lackorzynski * economic rights: Technische Universität Dresden (Germany) - * Copyright (C) 2017, 2018, 2021 Paul Boddie + * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie * * This file is part of TUD:OS and distributed under the terms of the * GNU General Public License 2. @@ -130,59 +130,54 @@ /* Read information from the clock and power management unit. */ printf("Main source: %d\n", jz4780_cpm_get_source(cpm, Clock_main)); - printf(" Main frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_main)); - printf("APLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_A)); - printf("EPLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_E)); - printf("MPLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_M)); - printf("VPLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V)); - printf("CPU frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_cpu)); + printf(" Main frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_main)); + printf("APLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_A)); + printf("EPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_E)); + printf("MPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_M)); + printf("VPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V)); + printf("CPU frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_cpu)); printf("Memory source: %d\n", jz4780_cpm_get_source(cpm, Clock_ddr)); - printf(" Memory source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_ddr)); - printf(" Memory frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_ddr)); + printf(" Memory source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_ddr)); + printf(" Memory frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_ddr)); printf("APB source: %d\n", jz4780_cpm_get_source(cpm, Clock_pclock)); - printf(" APB source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_pclock)); - printf(" Slow peripheral (APB) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pclock)); + printf(" APB source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_pclock)); + printf(" Slow peripheral (APB) frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pclock)); printf("AHB0 source: %d\n", jz4780_cpm_get_source(cpm, Clock_hclock0)); - printf(" AHB0 source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock0)); - printf(" Fast peripheral (AHB0) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hclock0)); + printf(" AHB0 source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock0)); + printf(" Fast peripheral (AHB0) frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_hclock0)); printf("AHB2 source: %d\n", jz4780_cpm_get_source(cpm, Clock_hclock2)); - printf(" AHB2 source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock2)); - printf(" Fast peripheral (AHB2) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hclock2)); + printf(" AHB2 source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock2)); + printf(" Fast peripheral (AHB2) frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_hclock2)); printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd)); - printf(" LCD source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd)); - printf(" LCD frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd)); - printf(" LCD pixel clock frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0)); + printf(" LCD source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd)); + printf(" LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd)); + printf(" LCD pixel clock frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0)); /* Attempt to set the pixel clock frequency. */ jz4780_cpm_set_frequency(cpm, Clock_lcd_pixel0, 108000000); printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd)); - printf(" LCD source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd)); - printf(" LCD frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd)); - printf(" LCD pixel clock frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0)); + printf(" LCD source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd)); + printf(" LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd)); + printf(" LCD pixel clock frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0)); - /* Attempt to set the peripheral clock frequency. */ + /* Change the pixel clock source. */ - jz4780_cpm_set_source(cpm, Clock_pclock, 1); + jz4780_cpm_set_source_clock(cpm, Clock_lcd_pixel0, Clock_pll_V); - printf("APB source: %d\n", jz4780_cpm_get_source(cpm, Clock_pclock)); - printf(" APB source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_pclock)); - printf(" Slow peripheral (APB) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pclock)); - printf("AHB2 source: %d\n", jz4780_cpm_get_source(cpm, Clock_hclock2)); - printf(" AHB2 source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock2)); - printf(" Fast peripheral (AHB2) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hclock2)); - - /* Attempt to set the MPLL output to EXCLK divided by 4. */ + printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd)); + printf(" LCD source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd)); + printf(" LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd)); + printf(" LCD pixel clock frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0)); - jz4780_cpm_set_parameters(cpm, Clock_pll_M, 3, (uint32_t []) {1, 4, 1}); + /* Attempt to set the VPLL output to EXCLK divided by 4. */ + + jz4780_cpm_set_parameters(cpm, Clock_pll_V, 3, (uint32_t []) {1, 4, 1}); - printf("APB source: %d\n", jz4780_cpm_get_source(cpm, Clock_pclock)); - printf(" APB source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_pclock)); - printf(" Slow peripheral (APB) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pclock)); - printf("AHB2 source: %d\n", jz4780_cpm_get_source(cpm, Clock_hclock2)); - printf(" AHB2 source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock2)); - printf(" Fast peripheral (AHB2) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hclock2)); + printf("VPLL source: %d\n", jz4780_cpm_get_source(cpm, Clock_pll_V)); + printf(" VPLL source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_pll_V)); + printf(" VPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V)); return 0; } diff -r f1df79717f9e -r 398898e77d36 pkg/landfall-examples/ci20_hdmi_i2c/ci20_hdmi_i2c.c --- a/pkg/landfall-examples/ci20_hdmi_i2c/ci20_hdmi_i2c.c Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/landfall-examples/ci20_hdmi_i2c/ci20_hdmi_i2c.c Sat Oct 28 01:15:45 2023 +0200 @@ -272,13 +272,13 @@ cpm = jz4780_cpm_init(cpm_base); - printf("VPLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V)); - printf("HDMI frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hdmi)); + printf("VPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V)); + printf("HDMI frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_hdmi)); jz4780_cpm_stop_clock(cpm, Clock_hdmi); jz4780_cpm_set_frequency(cpm, Clock_hdmi, 27000000); - printf("HDMI frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hdmi)); + printf("HDMI frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_hdmi)); jz4780_cpm_start_clock(cpm, Clock_hdmi); @@ -339,7 +339,7 @@ /* Test initialisation with a frequency appropriate for the test panel. */ printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd)); - printf("LCD frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0)); + printf("LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0)); printf("Desired frequency: %d\n", jz4740_lcd_get_pixel_clock(lcd)); jz4780_cpm_stop_clock(cpm, Clock_lcd); @@ -347,7 +347,7 @@ jz4780_cpm_set_frequency(cpm, Clock_lcd_pixel0, jz4740_lcd_get_pixel_clock(lcd)); printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd)); - printf("LCD frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0)); + printf("LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0)); /* With the LCD pixel clock set up, bring up the HDMI. */ diff -r f1df79717f9e -r 398898e77d36 pkg/landfall-examples/ci20_i2c/ci20_i2c.c --- a/pkg/landfall-examples/ci20_i2c/ci20_i2c.c Sat Oct 28 00:28:42 2023 +0200 +++ b/pkg/landfall-examples/ci20_i2c/ci20_i2c.c Sat Oct 28 01:15:45 2023 +0200 @@ -404,7 +404,7 @@ /* Attempt to set the PCLK source to SCLK_A. */ jz4780_cpm_set_source_clock(cpm, Clock_pclock, Clock_main); - printf("Peripheral clock: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pclock)); + printf("Peripheral clock: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pclock)); /* Obtain I2C reference. */