# HG changeset patch # User Paul Boddie # Date 1694798974 -7200 # Node ID b876c7d44aaa34a87b867e82c4630bc12dca8470 # Parent bf4aa4a70eb0191224dceb104466af6e5424c6e5 Consolidated register field information into field definitions. diff -r bf4aa4a70eb0 -r b876c7d44aaa pkg/devices/lib/cpm/src/x1600.cc --- a/pkg/devices/lib/cpm/src/x1600.cc Fri Sep 15 17:55:43 2023 +0200 +++ b/pkg/devices/lib/cpm/src/x1600.cc Fri Sep 15 19:29:34 2023 +0200 @@ -38,21 +38,21 @@ Clock_gate1 = 0x028, // CLKGR1 Sleep_control = 0x024, // OPCR (oscillator and power control) Clock_status = 0x0d4, // CPCSR - Ddr_divider = 0x02c, // DDRCDR - Mac_divider = 0x054, // MACCDR - I2s_divider0 = 0x060, // I2SCDR - I2s_divider1 = 0x070, // I2S1CDR - Lcd_divider = 0x064, // LPCDR - Msc_divider0 = 0x068, // MSC0CDR - Msc_divider1 = 0x0a4, // MSC1CDR - Sfc_divider = 0x074, // SFCCDR - Ssi_divider = 0x05c, // SSICDR - Cim_divider = 0x078, // CIMCDR - Pwm_divider = 0x06c, // PWMCDR - Can_divider0 = 0x0a0, // CAN0CDR - Can_divider1 = 0x0a8, // CAN1CDR - Cdbus_divider = 0x0ac, // CDBUSCDR - Macphy0_divider = 0x0e4, // MPHY0C + Divider_ddr = 0x02c, // DDRCDR + Divider_mac = 0x054, // MACCDR + Divider0_i2s0 = 0x060, // I2SCDR + Divider1_i2s0 = 0x070, // I2S1CDR + Divider_lcd = 0x064, // LPCDR + Divider_msc0 = 0x068, // MSC0CDR + Divider_msc1 = 0x0a4, // MSC1CDR + Divider_sfc = 0x074, // SFCCDR + Divider_ssi = 0x05c, // SSICDR + Divider_cim = 0x078, // CIMCDR + Divider_pwm = 0x06c, // PWMCDR + Divider_can0 = 0x0a0, // CAN0CDR + Divider_can1 = 0x0a8, // CAN1CDR + Divider_cdbus = 0x0ac, // CDBUSCDR + Divider_macphy0 = 0x0e4, // MPHY0C Cpm_interrupt = 0x0b0, // CPM_INTR Cpm_interrupt_en = 0x0b4, // CPM_INTRE Cpm_swi = 0x0bc, // CPM_SFTINT @@ -72,32 +72,6 @@ Pll_fraction_E = 0x08c, // CPEPACR }; -enum Clock_source_bits : unsigned -{ - // Clock_control - - Clock_source_main = 30, // SEL_SRC (output to SCLK_A) - Clock_source_cpu = 28, // SEL_CPLL (output to CCLK) - Clock_source_hclock0 = 26, // SEL_H0PLL (output to AHB0) - Clock_source_hclock2 = 24, // SEL_H2PLL (output to AHB2) - - // Divider registers - - Clock_source_can0 = 30, // CA0CS - Clock_source_can1 = 30, // CA1CS - Clock_source_cdbus = 30, // CDCS - Clock_source_cim = 30, // CIMPCS - Clock_source_ddr = 30, // DCS - Clock_source_i2s = 31, // I2PCS - Clock_source_lcd = 30, // LPCS - Clock_source_mac = 30, // MACPCS - Clock_source_msc0 = 30, // MPCS - Clock_source_msc1 = 30, // MPCS - Clock_source_pwm = 30, // PWMPCS - Clock_source_sfc = 30, // SFCS - Clock_source_ssi = 30, // SPCS -}; - enum Clock_source_values : unsigned { Source_mME_main = 0, @@ -109,115 +83,6 @@ Source_mask = 0x3, }; -enum Clock_gate_bits : unsigned -{ - // Clock_control - - Clock_gate_main = 23, // GATE_SCLKA - - // Clock_gate0 - - Clock_gate_ddr = 31, // DDR - Clock_gate_ahb0 = 29, // AHB0 - Clock_gate_apb0 = 28, // APB0 - Clock_gate_rtc = 27, // RTC - Clock_gate_aes = 24, // AES - Clock_gate_lcd_pixel = 23, // LCD - Clock_gate_cim = 22, // CIM - Clock_gate_dma = 21, // PDMA - Clock_gate_ost = 20, // OST - Clock_gate_ssi0 = 19, // SSI0 - Clock_gate_timer = 18, // TCU - Clock_gate_dtrng = 17, // DTRNG - Clock_gate_uart2 = 16, // UART2 - Clock_gate_uart1 = 15, // UART1 - Clock_gate_uart0 = 14, // UART0 - Clock_gate_sadc = 13, // SADC - Clock_gate_audio = 11, // AUDIO - Clock_gate_ssi_slv = 10, // SSI_SLV - Clock_gate_i2c1 = 8, // I2C1 - Clock_gate_i2c0 = 7, // I2C0 - Clock_gate_msc1 = 5, // MSC1 - Clock_gate_msc0 = 4, // MSC0 - Clock_gate_otg = 3, // OTG - Clock_gate_sfc = 2, // SFC - Clock_gate_efuse = 1, // EFUSE - Clock_gate_nemc = 0, // NEMC - - // Clock_gate1 - - Clock_gate_arb = 30, // ARB - Clock_gate_mipi_csi = 28, // MIPI_CSI - Clock_gate_intc = 26, // INTC - Clock_gate_gmac0 = 23, // GMAC0 - Clock_gate_uart3 = 16, // UART3 - Clock_gate_i2s0_tx = 9, // I2S0_dev_tclk - Clock_gate_i2s0_rx = 8, // I2S0_dev_rclk - Clock_gate_hash = 6, // HASH - Clock_gate_pwm = 5, // PWM - Clock_gate_cdbus = 2, // CDBUS - Clock_gate_can1 = 1, // CAN1 - Clock_gate_can0 = 0, // CAN0 -}; - -enum Clock_change_enable_bits : unsigned -{ - Clock_change_enable_cpu = 22, - Clock_change_enable_ahb0 = 21, - Clock_change_enable_ahb2 = 20, - Clock_change_enable_ddr = 29, - Clock_change_enable_mac = 29, - Clock_change_enable_i2s = 29, - Clock_change_enable_lcd = 29, - Clock_change_enable_msc0 = 29, - Clock_change_enable_msc1 = 29, - Clock_change_enable_sfc = 29, - Clock_change_enable_ssi = 29, - Clock_change_enable_cim = 29, - Clock_change_enable_pwm = 29, - Clock_change_enable_can0 = 29, - Clock_change_enable_can1 = 29, - Clock_change_enable_cdbus = 29, -}; - -enum Clock_busy_bits : unsigned -{ - Clock_busy_cpu = 0, - Clock_busy_ddr = 28, - Clock_busy_mac = 28, - Clock_busy_lcd = 28, - Clock_busy_msc0 = 28, - Clock_busy_msc1 = 28, - Clock_busy_sfc = 28, - Clock_busy_ssi = 28, - Clock_busy_cim = 28, - Clock_busy_pwm = 28, - Clock_busy_can0 = 28, - Clock_busy_can1 = 28, - Clock_busy_cdbus = 28, -}; - -enum Clock_divider_bits : unsigned -{ - Clock_divider_can0 = 0, // CAN0CDR - Clock_divider_can1 = 0, // CAN1CDR - Clock_divider_cdbus = 0, // CDBUSCDR - Clock_divider_cim = 0, // CIMCDR - Clock_divider_cpu = 0, // CDIV - Clock_divider_ddr = 0, // DDRCDR - Clock_divider_hclock0 = 8, // H0DIV (fast AHB peripherals) - Clock_divider_hclock2 = 12, // H2DIV (fast AHB peripherals) - Clock_divider_l2cache = 4, // L2CDIV - Clock_divider_lcd = 0, // LPCDR - Clock_divider_mac = 0, // MACCDR - Clock_divider_msc0 = 0, // MSC0CDR - Clock_divider_msc1 = 0, // MSC1CDR - Clock_divider_pclock = 16, // PDIV (slow APB peripherals) - Clock_divider_pwm = 0, // PWMCDR - Clock_divider_sfc = 0, // SFCCDR - Clock_divider_ssi = 0, // SSICDR -}; - enum Pll_bits : unsigned { // Pll_control_A, Pll_control_M, Pll_control_E @@ -406,158 +271,269 @@ +// Register field definitions. + +Field Clock_source_main (Clock_control, 3, 30); // SEL_SRC (output to SCLK_A) +Field Clock_source_cpu (Clock_control, 3, 28); // SEL_CPLL (output to CCLK) +Field Clock_source_hclock0 (Clock_control, 3, 26); // SEL_H0PLL (output to AHB0) +Field Clock_source_hclock2 (Clock_control, 3, 24); // SEL_H2PLL (output to AHB2) +Field Clock_source_can0 (Divider_can0, 3, 30); // CA0CS +Field Clock_source_can1 (Divider_can1, 3, 30); // CA1CS +Field Clock_source_cdbus (Divider_cdbus, 3, 30); // CDCS +Field Clock_source_cim (Divider_cim, 3, 30); // CIMPCS +Field Clock_source_ddr (Divider_ddr, 3, 30); // DCS +Field Clock_source_i2s (Divider0_i2s0, 1, 31); // I2PCS +Field Clock_source_lcd (Divider_lcd, 3, 30); // LPCS +Field Clock_source_mac (Divider_mac, 3, 30); // MACPCS +Field Clock_source_msc0 (Divider_msc0, 3, 30); // MPCS +Field Clock_source_msc1 (Divider_msc1, 3, 30); // MPCS +Field Clock_source_pwm (Divider_pwm, 3, 30); // PWMPCS +Field Clock_source_sfc (Divider_sfc, 3, 30); // SFCS +Field Clock_source_ssi (Divider_ssi, 3, 30); // SPCS + +Field Clock_busy_cpu (Clock_status, 1, 0); +Field Clock_busy_ddr (Divider_ddr, 1, 28); +Field Clock_busy_mac (Divider_mac, 1, 28); +Field Clock_busy_lcd (Divider_lcd, 1, 28); +Field Clock_busy_msc0 (Divider_msc0, 1, 28); +Field Clock_busy_msc1 (Divider_msc1, 1, 28); +Field Clock_busy_sfc (Divider_sfc, 1, 28); +Field Clock_busy_ssi (Divider_ssi, 1, 28); +Field Clock_busy_cim (Divider_cim, 1, 28); +Field Clock_busy_pwm (Divider_pwm, 1, 28); +Field Clock_busy_can0 (Divider_can0, 1, 28); +Field Clock_busy_can1 (Divider_can1, 1, 28); +Field Clock_busy_cdbus (Divider_cdbus, 1, 28); + +Field Clock_change_enable_cpu (Clock_control, 1, 22); +Field Clock_change_enable_ahb0 (Clock_control, 1, 21); +Field Clock_change_enable_ahb2 (Clock_control, 1, 20); +Field Clock_change_enable_ddr (Divider_ddr, 1, 29); +Field Clock_change_enable_mac (Divider_mac, 1, 29); +Field Clock_change_enable_i2s (Divider0_i2s0, 1, 29); +Field Clock_change_enable_lcd (Divider_lcd, 1, 29); +Field Clock_change_enable_msc0 (Divider_msc0, 1, 29); +Field Clock_change_enable_msc1 (Divider_msc1, 1, 29); +Field Clock_change_enable_sfc (Divider_sfc, 1, 29); +Field Clock_change_enable_ssi (Divider_ssi, 1, 29); +Field Clock_change_enable_cim (Divider_cim, 1, 29); +Field Clock_change_enable_pwm (Divider_pwm, 1, 29); +Field Clock_change_enable_can0 (Divider_can0, 1, 29); +Field Clock_change_enable_can1 (Divider_can1, 1, 29); +Field Clock_change_enable_cdbus (Divider_cdbus, 1, 29); + +Field Clock_divider_can0 (Divider_can0, 0xff, 0); // CAN0CDR +Field Clock_divider_can1 (Divider_can1, 0xff, 0); // CAN1CDR +Field Clock_divider_cdbus (Divider_cdbus, 0xff, 0); // CDBUSCDR +Field Clock_divider_cim (Divider_cim, 0xff, 0); // CIMCDR +Field Clock_divider_cpu (Clock_control, 0x0f, 0); // CDIV +Field Clock_divider_ddr (Divider_ddr, 0x0f, 0); // DDRCDR +Field Clock_divider_hclock0 (Clock_control, 0x0f, 8); // H0DIV (fast AHB peripherals) +Field Clock_divider_hclock2 (Clock_control, 0x0f, 12); // H2DIV (fast AHB peripherals) +Field Clock_divider_l2cache (Clock_control, 0x0f, 4); // L2CDIV +Field Clock_divider_lcd (Divider_lcd, 0xff, 0); // LPCDR +Field Clock_divider_mac (Divider_mac, 0xff, 0); // MACCDR +Field Clock_divider_msc0 (Divider_msc0, 0xff, 0); // MSC0CDR +Field Clock_divider_msc1 (Divider_msc1, 0xff, 0); // MSC1CDR +Field Clock_divider_pclock (Clock_control, 0x0f, 16); // PDIV (slow APB peripherals) +Field Clock_divider_pwm (Divider_pwm, 0x0f, 0); // PWMCDR +Field Clock_divider_sfc (Divider_sfc, 0xff, 0); // SFCCDR +Field Clock_divider_ssi (Divider_ssi, 0xff, 0); // SSICDR + +Field Clock_gate_main (Clock_control, 1, 23); // GATE_SCLKA +Field Clock_gate_ddr (Clock_gate0, 1, 31); // DDR +Field Clock_gate_ahb0 (Clock_gate0, 1, 29); // AHB0 +Field Clock_gate_apb0 (Clock_gate0, 1, 28); // APB0 +Field Clock_gate_rtc (Clock_gate0, 1, 27); // RTC +Field Clock_gate_aes (Clock_gate0, 1, 24); // AES +Field Clock_gate_lcd_pixel (Clock_gate0, 1, 23); // LCD +Field Clock_gate_cim (Clock_gate0, 1, 22); // CIM +Field Clock_gate_dma (Clock_gate0, 1, 21); // PDMA +Field Clock_gate_ost (Clock_gate0, 1, 20); // OST +Field Clock_gate_ssi0 (Clock_gate0, 1, 19); // SSI0 +Field Clock_gate_timer (Clock_gate0, 1, 18); // TCU +Field Clock_gate_dtrng (Clock_gate0, 1, 17); // DTRNG +Field Clock_gate_uart2 (Clock_gate0, 1, 16); // UART2 +Field Clock_gate_uart1 (Clock_gate0, 1, 15); // UART1 +Field Clock_gate_uart0 (Clock_gate0, 1, 14); // UART0 +Field Clock_gate_sadc (Clock_gate0, 1, 13); // SADC +Field Clock_gate_audio (Clock_gate0, 1, 11); // AUDIO +Field Clock_gate_ssi_slv (Clock_gate0, 1, 10); // SSI_SLV +Field Clock_gate_i2c1 (Clock_gate0, 1, 8); // I2C1 +Field Clock_gate_i2c0 (Clock_gate0, 1, 7); // I2C0 +Field Clock_gate_msc1 (Clock_gate0, 1, 5); // MSC1 +Field Clock_gate_msc0 (Clock_gate0, 1, 4); // MSC0 +Field Clock_gate_otg (Clock_gate0, 1, 3); // OTG +Field Clock_gate_sfc (Clock_gate0, 1, 2); // SFC +Field Clock_gate_efuse (Clock_gate0, 1, 1); // EFUSE +Field Clock_gate_nemc (Clock_gate0, 1, 0); // NEMC +Field Clock_gate_arb (Clock_gate1, 1, 30); // ARB +Field Clock_gate_mipi_csi (Clock_gate1, 1, 28); // MIPI_CSI +Field Clock_gate_intc (Clock_gate1, 1, 26); // INTC +Field Clock_gate_gmac0 (Clock_gate1, 1, 23); // GMAC0 +Field Clock_gate_uart3 (Clock_gate1, 1, 16); // UART3 +Field Clock_gate_i2s0_tx (Clock_gate1, 1, 9); // I2S0_dev_tclk +Field Clock_gate_i2s0_rx (Clock_gate1, 1, 8); // I2S0_dev_rclk +Field Clock_gate_hash (Clock_gate1, 1, 6); // HASH +Field Clock_gate_pwm (Clock_gate1, 1, 5); // PWM +Field Clock_gate_cdbus (Clock_gate1, 1, 2); // CDBUS +Field Clock_gate_can1 (Clock_gate1, 1, 1); // CAN1 +Field Clock_gate_can0 (Clock_gate1, 1, 0); // CAN0 + + + // Clock instances. #define Clock_inputs(...) ((enum Clock_identifiers []) {__VA_ARGS__}) Clock clock_ahb2_apb(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), - Field(Clock_control, 3, Clock_source_hclock2)); + Clock_source_hclock2); Clock clock_aic_bitclk; Clock clock_aic_pclk; Clock clock_can0(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external), - Field(Can_divider0, 3, Clock_source_can0), - Field(Clock_gate1, 1, Clock_gate_can0), - Field(Can_divider0, 1, Clock_change_enable_can0), - Field(Can_divider0, 1, Clock_busy_can0), - Field(Can_divider0, 0xff, Clock_divider_can0)); + Clock_source_can0, + Clock_gate_can0, + Clock_change_enable_can0, + Clock_busy_can0, + Clock_divider_can0); Clock clock_can1(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external), - Field(Can_divider1, 3, Clock_source_can1), - Field(Clock_gate1, 1, Clock_gate_can1), - Field(Can_divider1, 1, Clock_change_enable_can1), - Field(Can_divider1, 1, Clock_busy_can1), - Field(Can_divider1, 0xff, Clock_divider_can1)); + Clock_source_can1, + Clock_gate_can1, + Clock_change_enable_can1, + Clock_busy_can1, + Clock_divider_can1); Clock clock_cdbus(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Cdbus_divider, 3, Clock_source_cdbus), - Field(Clock_gate1, 1, Clock_gate_cdbus), - Field(Cdbus_divider, 1, Clock_change_enable_cdbus), - Field(Cdbus_divider, 1, Clock_busy_cdbus), - Field(Cdbus_divider, 0xff, Clock_divider_cdbus)); + Clock_source_cdbus, + Clock_gate_cdbus, + Clock_change_enable_cdbus, + Clock_busy_cdbus, + Clock_divider_cdbus); Clock clock_cim(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Cim_divider, 3, Clock_source_cim), - Field(Clock_gate0, 1, Clock_gate_cim), - Field(Cim_divider, 1, Clock_change_enable_cim), - Field(Cim_divider, 1, Clock_busy_cim), - Field(Cim_divider, 0xff, Clock_divider_cim)); + Clock_source_cim, + Clock_gate_cim, + Clock_change_enable_cim, + Clock_busy_cim, + Clock_divider_cim); Clock clock_cpu(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), - Field(Clock_control, 3, Clock_source_cpu), + Clock_source_cpu, Gate_undefined, - Field(Clock_control, 1, Clock_change_enable_cpu), - Field(Clock_status, 1, Clock_busy_cpu), - Field(Clock_control, 0x0f, Clock_divider_cpu)); + Clock_change_enable_cpu, + Clock_busy_cpu, + Clock_divider_cpu); Clock clock_ddr(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), - Field(Ddr_divider, 3, Clock_source_ddr), - Field(Clock_gate0, 1, Clock_gate_ddr), - Field(Ddr_divider, 1, Clock_change_enable_ddr), - Field(Ddr_divider, 1, Clock_busy_ddr), - Field(Ddr_divider, 0x0f, Clock_divider_ddr)); + Clock_source_ddr, + Clock_gate_ddr, + Clock_change_enable_ddr, + Clock_busy_ddr, + Clock_divider_ddr); Clock clock_dma(1, Clock_inputs(Clock_pclock), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_dma)); + Clock_gate_dma); Clock clock_emac; Clock clock_external; Clock clock_hclock0(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), - Field(Clock_control, 3, Clock_source_hclock0), - Field(Clock_gate0, 1, Clock_gate_ahb0), - Field(Clock_control, 1, Clock_change_enable_ahb0), + Clock_source_hclock0, + Clock_gate_ahb0, + Clock_change_enable_ahb0, Busy_undefined, - Field(Clock_control, 0x0f, Clock_divider_hclock0)); + Clock_divider_hclock0); Clock clock_hclock2(1, Clock_inputs(Clock_ahb2_apb), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_apb0), - Field(Clock_control, 1, Clock_change_enable_ahb2), + Clock_gate_apb0, + Clock_change_enable_ahb2, Busy_undefined, - Field(Clock_control, 0x0f, Clock_divider_hclock2)); + Clock_divider_hclock2); Clock clock_hdmi; Clock clock_i2c(1, Clock_inputs(Clock_pclock), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_i2c0)); + Clock_gate_i2c0); Clock clock_i2c0(1, Clock_inputs(Clock_pclock), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_i2c0)); + Clock_gate_i2c0); Clock clock_i2c1(1, Clock_inputs(Clock_pclock), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_i2c1)); + Clock_gate_i2c1); Clock clock_i2s; Clock clock_i2s0_rx(2, Clock_inputs(Clock_main, Clock_pll_E), - Field(I2s_divider0, 1, Clock_source_i2s), - Field(Clock_gate1, 1, Clock_gate_i2s0_rx), - Field(I2s_divider0, 1, Clock_change_enable_i2s)); + Clock_source_i2s, + Clock_gate_i2s0_rx, + Clock_change_enable_i2s); Clock clock_i2s0_tx(2, Clock_inputs(Clock_main, Clock_pll_E), - Field(I2s_divider0, 1, Clock_source_i2s), - Field(Clock_gate1, 1, Clock_gate_i2s0_tx), - Field(I2s_divider0, 1, Clock_change_enable_i2s)); + Clock_source_i2s, + Clock_gate_i2s0_tx, + Clock_change_enable_i2s); Clock clock_kbc; Clock clock_lcd; Clock clock_lcd_pixel(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Lcd_divider, 3, Clock_source_lcd), - Field(Clock_gate0, 1, Clock_gate_lcd_pixel), - Field(Lcd_divider, 1, Clock_change_enable_lcd), - Field(Lcd_divider, 1, Clock_busy_lcd), - Field(Lcd_divider, 0xff, Clock_divider_lcd)); + Clock_source_lcd, + Clock_gate_lcd_pixel, + Clock_change_enable_lcd, + Clock_busy_lcd, + Clock_divider_lcd); Clock clock_mac(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Mac_divider, 3, Clock_source_mac), - Field(Clock_gate1, 1, Clock_gate_gmac0), - Field(Mac_divider, 1, Clock_change_enable_mac), - Field(Mac_divider, 1, Clock_busy_mac), - Field(Mac_divider, 0xff, Clock_divider_mac)); + Clock_source_mac, + Clock_gate_gmac0, + Clock_change_enable_mac, + Clock_busy_mac, + Clock_divider_mac); Clock clock_main(3, Clock_inputs(Clock_none, Clock_external, Clock_pll_A), - Field(Clock_control, 3, Clock_source_main), - Field(Clock_control, 1, Clock_gate_main)); + Clock_source_main, + Clock_gate_main); Clock clock_msc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Msc_divider0, 3, Clock_source_msc0), - Field(Clock_gate0, 1, Clock_gate_msc0), - Field(Msc_divider0, 1, Clock_change_enable_msc0), - Field(Msc_divider0, 1, Clock_busy_msc0), - Field(Msc_divider0, 0xff, Clock_divider_msc0)); + Clock_source_msc0, + Clock_gate_msc0, + Clock_change_enable_msc0, + Clock_busy_msc0, + Clock_divider_msc0); Clock clock_msc0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Msc_divider0, 3, Clock_source_msc0), - Field(Clock_gate0, 1, Clock_gate_msc0), - Field(Msc_divider0, 1, Clock_change_enable_msc0), - Field(Msc_divider0, 1, Clock_busy_msc0), - Field(Msc_divider0, 0xff, Clock_divider_msc0)); + Clock_source_msc0, + Clock_gate_msc0, + Clock_change_enable_msc0, + Clock_busy_msc0, + Clock_divider_msc0); Clock clock_msc1(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Msc_divider1, 3, Clock_source_msc1), - Field(Clock_gate0, 1, Clock_gate_msc1), - Field(Msc_divider1, 1, Clock_change_enable_msc1), - Field(Msc_divider1, 1, Clock_busy_msc1), - Field(Msc_divider1, 0xff, Clock_divider_msc1)); + Clock_source_msc1, + Clock_gate_msc1, + Clock_change_enable_msc1, + Clock_busy_msc1, + Clock_divider_msc1); Clock clock_none; Clock clock_pclock(1, Clock_inputs(Clock_ahb2_apb), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_apb0), + Clock_gate_apb0, Change_enable_undefined, Busy_undefined, - Field(Clock_control, 0x0f, Clock_divider_pclock)); + Clock_divider_pclock); Pll clock_pll_A(1, Clock_inputs(Clock_external), Pll_control_A, Pll_bypass_A); @@ -569,29 +545,29 @@ Pll_control_M, Pll_bypass_M); Clock clock_pwm(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Pwm_divider, 3, Clock_source_pwm), - Field(Clock_gate1, 1, Clock_gate_pwm), - Field(Pwm_divider, 1, Clock_change_enable_pwm), - Field(Pwm_divider, 1, Clock_busy_pwm), - Field(Pwm_divider, 0x0f, Clock_divider_pwm)); + Clock_source_pwm, + Clock_gate_pwm, + Clock_change_enable_pwm, + Clock_busy_pwm, + Clock_divider_pwm); Clock clock_pwm0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Pwm_divider, 3, Clock_source_pwm), - Field(Clock_gate1, 1, Clock_gate_pwm), - Field(Pwm_divider, 1, Clock_change_enable_pwm), - Field(Pwm_divider, 1, Clock_busy_pwm), - Field(Pwm_divider, 0x0f, Clock_divider_pwm)); + Clock_source_pwm, + Clock_gate_pwm, + Clock_change_enable_pwm, + Clock_busy_pwm, + Clock_divider_pwm); Clock clock_pwm1; Clock clock_scc; Clock clock_sfc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Sfc_divider, 3, Clock_source_sfc), - Field(Clock_gate0, 1, Clock_gate_sfc), - Field(Sfc_divider, 1, Clock_change_enable_sfc), - Field(Sfc_divider, 1, Clock_busy_sfc), - Field(Sfc_divider, 0xff, Clock_divider_sfc)); + Clock_source_sfc, + Clock_gate_sfc, + Clock_change_enable_sfc, + Clock_busy_sfc, + Clock_divider_sfc); Clock clock_smb0; @@ -604,31 +580,31 @@ Clock clock_smb4; Clock clock_ssi(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Field(Ssi_divider, 3, Clock_source_ssi), - Field(Clock_gate0, 1, Clock_gate_ssi0), - Field(Ssi_divider, 1, Clock_change_enable_ssi), - Field(Ssi_divider, 1, Clock_busy_ssi), - Field(Ssi_divider, 0xff, Clock_divider_ssi)); + Clock_source_ssi, + Clock_gate_ssi0, + Clock_change_enable_ssi, + Clock_busy_ssi, + Clock_divider_ssi); Clock clock_timer(1, Clock_inputs(Clock_pclock), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_timer)); + Clock_gate_timer); Clock clock_uart0(1, Clock_inputs(Clock_external), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_uart0)); + Clock_gate_uart0); Clock clock_uart1(1, Clock_inputs(Clock_external), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_uart1)); + Clock_gate_uart1); Clock clock_uart2(1, Clock_inputs(Clock_external), Source_undefined, - Field(Clock_gate0, 1, Clock_gate_uart2)); + Clock_gate_uart2); Clock clock_uart3(1, Clock_inputs(Clock_external), Source_undefined, - Field(Clock_gate1, 1, Clock_gate_uart3)); + Clock_gate_uart3); Clock clock_udc;