# HG changeset patch # User Paul Boddie # Date 1694793343 -7200 # Node ID bf4aa4a70eb0191224dceb104466af6e5424c6e5 # Parent 1dc8b79654efb0a8c13dca159db9263b8c00b7f7 Introduced a register field abstraction to simplify clock abstractions. diff -r 1dc8b79654ef -r bf4aa4a70eb0 pkg/devices/lib/cpm/src/x1600.cc --- a/pkg/devices/lib/cpm/src/x1600.cc Fri Sep 15 00:31:43 2023 +0200 +++ b/pkg/devices/lib/cpm/src/x1600.cc Fri Sep 15 17:55:43 2023 +0200 @@ -70,10 +70,6 @@ Pll_fraction_A = 0x084, // CPAPACR Pll_fraction_M = 0x088, // CPMPACR Pll_fraction_E = 0x08c, // CPEPACR - - // Special value - - Reg_undefined = 0xfff, }; enum Clock_source_bits : unsigned @@ -100,10 +96,6 @@ Clock_source_pwm = 30, // PWMPCS Clock_source_sfc = 30, // SFCS Clock_source_ssi = 30, // SPCS - - // Special value - - Clock_source_undefined = 32, }; enum Clock_source_values : unsigned @@ -166,10 +158,6 @@ Clock_gate_cdbus = 2, // CDBUS Clock_gate_can1 = 1, // CAN1 Clock_gate_can0 = 0, // CAN0 - - // Special value - - Clock_gate_undefined = 32, }; enum Clock_change_enable_bits : unsigned @@ -190,10 +178,6 @@ Clock_change_enable_can0 = 29, Clock_change_enable_can1 = 29, Clock_change_enable_cdbus = 29, - - // Special value - - Clock_change_enable_undefined = 32, }; enum Clock_busy_bits : unsigned @@ -211,10 +195,6 @@ Clock_busy_can0 = 28, Clock_busy_can1 = 28, Clock_busy_cdbus = 28, - - // Special value - - Clock_busy_undefined = 32, }; enum Clock_divider_bits : unsigned @@ -236,10 +216,6 @@ Clock_divider_pwm = 0, // PWMCDR Clock_divider_sfc = 0, // SFCCDR Clock_divider_ssi = 0, // SSICDR - - // Special value - - Clock_divider_undefined = 32, }; enum Pll_bits : unsigned @@ -263,6 +239,37 @@ +// Register field abstraction. + +class Field +{ + uint32_t reg; + uint32_t mask; + uint8_t bit; + bool defined; + +public: + explicit Field() + : defined(false) + { + } + + explicit Field(uint32_t reg, uint32_t mask, uint32_t bit) + : reg(reg), mask(mask), bit(bit), defined(true) + { + } + + uint32_t get_field(Cpm_regs ®s); + void set_field(Cpm_regs ®s, uint32_t value); + bool is_defined() { return defined; } +}; + +// Undefined fields. + +Field Source_undefined, Gate_undefined, Change_enable_undefined, Busy_undefined, Divider_undefined; + + + // Common clock abstraction. class Clock_base @@ -273,16 +280,13 @@ int num_inputs; enum Clock_identifiers *inputs; - uint32_t source_reg; - enum Clock_source_bits source_bit; + Field _source; public: explicit Clock_base(int num_inputs = 0, enum Clock_identifiers inputs[] = NULL, - uint32_t source_reg = Reg_undefined, - enum Clock_source_bits source_bit = Clock_source_undefined) - : num_inputs(num_inputs), inputs(inputs), - source_reg(source_reg), source_bit(source_bit) + Field source = Source_undefined) + : num_inputs(num_inputs), inputs(inputs), _source(source) { } @@ -364,15 +368,7 @@ class Clock : public Clock_base { - uint32_t gate_reg; - enum Clock_gate_bits gate_bit; - uint32_t change_enable_reg; - enum Clock_change_enable_bits change_enable_bit; - uint32_t busy_reg; - enum Clock_busy_bits busy_bit; - uint32_t divider_reg; - enum Clock_divider_bits divider_bit; - uint32_t divider_mask; + Field _gate, _change_enable, _busy, _divider; // Clock control. @@ -381,24 +377,14 @@ void wait_busy(Cpm_regs ®s); public: - explicit Clock(int num_inputs = 0, - enum Clock_identifiers inputs[] = NULL, - uint32_t source_reg = Reg_undefined, - enum Clock_source_bits source_bit = Clock_source_undefined, - uint32_t gate_reg = Reg_undefined, - enum Clock_gate_bits gate_bit = Clock_gate_undefined, - uint32_t change_enable_reg = Reg_undefined, - enum Clock_change_enable_bits change_enable_bit = Clock_change_enable_undefined, - uint32_t busy_reg = Reg_undefined, - enum Clock_busy_bits busy_bit = Clock_busy_undefined, - uint32_t divider_reg = Reg_undefined, - enum Clock_divider_bits divider_bit = Clock_divider_undefined, - uint32_t divider_mask = 0) - : Clock_base(num_inputs, inputs, source_reg, source_bit), - gate_reg(gate_reg), gate_bit(gate_bit), - change_enable_reg(change_enable_reg), change_enable_bit(change_enable_bit), - busy_reg(busy_reg), busy_bit(busy_bit), - divider_reg(divider_reg), divider_bit(divider_bit), divider_mask(divider_mask) + explicit Clock(int num_inputs = 0, enum Clock_identifiers inputs[] = NULL, + Field source = Source_undefined, + Field gate = Gate_undefined, + Field change_enable = Change_enable_undefined, + Field busy = Busy_undefined, + Field divider = Divider_undefined) + : Clock_base(num_inputs, inputs, source), + _gate(gate), _change_enable(change_enable), _busy(busy), _divider(divider) { } @@ -425,153 +411,153 @@ #define Clock_inputs(...) ((enum Clock_identifiers []) {__VA_ARGS__}) Clock clock_ahb2_apb(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), - Clock_control, Clock_source_hclock2); + Field(Clock_control, 3, Clock_source_hclock2)); Clock clock_aic_bitclk; Clock clock_aic_pclk; Clock clock_can0(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external), - Can_divider0, Clock_source_can0, - Clock_gate1, Clock_gate_can0, - Can_divider0, Clock_change_enable_can0, - Can_divider0, Clock_busy_can0, - Can_divider0, Clock_divider_can0, 0xff); + Field(Can_divider0, 3, Clock_source_can0), + Field(Clock_gate1, 1, Clock_gate_can0), + Field(Can_divider0, 1, Clock_change_enable_can0), + Field(Can_divider0, 1, Clock_busy_can0), + Field(Can_divider0, 0xff, Clock_divider_can0)); Clock clock_can1(4, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external), - Can_divider1, Clock_source_can1, - Clock_gate1, Clock_gate_can1, - Can_divider1, Clock_change_enable_can1, - Can_divider1, Clock_busy_can1, - Can_divider1, Clock_divider_can1, 0xff); + Field(Can_divider1, 3, Clock_source_can1), + Field(Clock_gate1, 1, Clock_gate_can1), + Field(Can_divider1, 1, Clock_change_enable_can1), + Field(Can_divider1, 1, Clock_busy_can1), + Field(Can_divider1, 0xff, Clock_divider_can1)); Clock clock_cdbus(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Cdbus_divider, Clock_source_cdbus, - Clock_gate1, Clock_gate_cdbus, - Cdbus_divider, Clock_change_enable_cdbus, - Cdbus_divider, Clock_busy_cdbus, - Cdbus_divider, Clock_divider_cdbus, 0xff); + Field(Cdbus_divider, 3, Clock_source_cdbus), + Field(Clock_gate1, 1, Clock_gate_cdbus), + Field(Cdbus_divider, 1, Clock_change_enable_cdbus), + Field(Cdbus_divider, 1, Clock_busy_cdbus), + Field(Cdbus_divider, 0xff, Clock_divider_cdbus)); Clock clock_cim(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Cim_divider, Clock_source_cim, - Clock_gate0, Clock_gate_cim, - Cim_divider, Clock_change_enable_cim, - Cim_divider, Clock_busy_cim, - Cim_divider, Clock_divider_cim, 0xff); + Field(Cim_divider, 3, Clock_source_cim), + Field(Clock_gate0, 1, Clock_gate_cim), + Field(Cim_divider, 1, Clock_change_enable_cim), + Field(Cim_divider, 1, Clock_busy_cim), + Field(Cim_divider, 0xff, Clock_divider_cim)); Clock clock_cpu(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), - Clock_control, Clock_source_cpu, - Reg_undefined, Clock_gate_undefined, - Clock_control, Clock_change_enable_cpu, - Clock_status, Clock_busy_cpu, - Clock_control, Clock_divider_cpu, 0x0f); + Field(Clock_control, 3, Clock_source_cpu), + Gate_undefined, + Field(Clock_control, 1, Clock_change_enable_cpu), + Field(Clock_status, 1, Clock_busy_cpu), + Field(Clock_control, 0x0f, Clock_divider_cpu)); Clock clock_ddr(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), - Ddr_divider, Clock_source_ddr, - Clock_gate0, Clock_gate_ddr, - Ddr_divider, Clock_change_enable_ddr, - Ddr_divider, Clock_busy_ddr, - Ddr_divider, Clock_divider_ddr, 0x0f); + Field(Ddr_divider, 3, Clock_source_ddr), + Field(Clock_gate0, 1, Clock_gate_ddr), + Field(Ddr_divider, 1, Clock_change_enable_ddr), + Field(Ddr_divider, 1, Clock_busy_ddr), + Field(Ddr_divider, 0x0f, Clock_divider_ddr)); Clock clock_dma(1, Clock_inputs(Clock_pclock), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_dma); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_dma)); Clock clock_emac; Clock clock_external; Clock clock_hclock0(3, Clock_inputs(Clock_none, Clock_main, Clock_pll_M), - Clock_control, Clock_source_hclock0, - Clock_gate0, Clock_gate_ahb0, - Clock_control, Clock_change_enable_ahb0, - Reg_undefined, Clock_busy_undefined, - Clock_control, Clock_divider_hclock0, 0x0f); + Field(Clock_control, 3, Clock_source_hclock0), + Field(Clock_gate0, 1, Clock_gate_ahb0), + Field(Clock_control, 1, Clock_change_enable_ahb0), + Busy_undefined, + Field(Clock_control, 0x0f, Clock_divider_hclock0)); Clock clock_hclock2(1, Clock_inputs(Clock_ahb2_apb), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_apb0, - Clock_control, Clock_change_enable_ahb2, - Reg_undefined, Clock_busy_undefined, - Clock_control, Clock_divider_hclock2, 0x0f); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_apb0), + Field(Clock_control, 1, Clock_change_enable_ahb2), + Busy_undefined, + Field(Clock_control, 0x0f, Clock_divider_hclock2)); Clock clock_hdmi; Clock clock_i2c(1, Clock_inputs(Clock_pclock), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_i2c0); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_i2c0)); Clock clock_i2c0(1, Clock_inputs(Clock_pclock), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_i2c0); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_i2c0)); Clock clock_i2c1(1, Clock_inputs(Clock_pclock), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_i2c1); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_i2c1)); Clock clock_i2s; Clock clock_i2s0_rx(2, Clock_inputs(Clock_main, Clock_pll_E), - I2s_divider0, Clock_source_i2s, - Clock_gate1, Clock_gate_i2s0_rx, - I2s_divider0, Clock_change_enable_i2s); + Field(I2s_divider0, 1, Clock_source_i2s), + Field(Clock_gate1, 1, Clock_gate_i2s0_rx), + Field(I2s_divider0, 1, Clock_change_enable_i2s)); Clock clock_i2s0_tx(2, Clock_inputs(Clock_main, Clock_pll_E), - I2s_divider0, Clock_source_i2s, - Clock_gate1, Clock_gate_i2s0_tx, - I2s_divider0, Clock_change_enable_i2s); + Field(I2s_divider0, 1, Clock_source_i2s), + Field(Clock_gate1, 1, Clock_gate_i2s0_tx), + Field(I2s_divider0, 1, Clock_change_enable_i2s)); Clock clock_kbc; Clock clock_lcd; Clock clock_lcd_pixel(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Lcd_divider, Clock_source_lcd, - Clock_gate0, Clock_gate_lcd_pixel, - Lcd_divider, Clock_change_enable_lcd, - Lcd_divider, Clock_busy_lcd, - Lcd_divider, Clock_divider_lcd, 0xff); + Field(Lcd_divider, 3, Clock_source_lcd), + Field(Clock_gate0, 1, Clock_gate_lcd_pixel), + Field(Lcd_divider, 1, Clock_change_enable_lcd), + Field(Lcd_divider, 1, Clock_busy_lcd), + Field(Lcd_divider, 0xff, Clock_divider_lcd)); Clock clock_mac(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Mac_divider, Clock_source_mac, - Clock_gate1, Clock_gate_gmac0, - Mac_divider, Clock_change_enable_mac, - Mac_divider, Clock_busy_mac, - Mac_divider, Clock_divider_mac, 0xff); + Field(Mac_divider, 3, Clock_source_mac), + Field(Clock_gate1, 1, Clock_gate_gmac0), + Field(Mac_divider, 1, Clock_change_enable_mac), + Field(Mac_divider, 1, Clock_busy_mac), + Field(Mac_divider, 0xff, Clock_divider_mac)); Clock clock_main(3, Clock_inputs(Clock_none, Clock_external, Clock_pll_A), - Clock_control, Clock_source_main, - Clock_control, Clock_gate_main); + Field(Clock_control, 3, Clock_source_main), + Field(Clock_control, 1, Clock_gate_main)); Clock clock_msc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Msc_divider0, Clock_source_msc0, - Clock_gate0, Clock_gate_msc0, - Msc_divider0, Clock_change_enable_msc0, - Msc_divider0, Clock_busy_msc0, - Msc_divider0, Clock_divider_msc0, 0xff); + Field(Msc_divider0, 3, Clock_source_msc0), + Field(Clock_gate0, 1, Clock_gate_msc0), + Field(Msc_divider0, 1, Clock_change_enable_msc0), + Field(Msc_divider0, 1, Clock_busy_msc0), + Field(Msc_divider0, 0xff, Clock_divider_msc0)); Clock clock_msc0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Msc_divider0, Clock_source_msc0, - Clock_gate0, Clock_gate_msc0, - Msc_divider0, Clock_change_enable_msc0, - Msc_divider0, Clock_busy_msc0, - Msc_divider0, Clock_divider_msc0, 0xff); + Field(Msc_divider0, 3, Clock_source_msc0), + Field(Clock_gate0, 1, Clock_gate_msc0), + Field(Msc_divider0, 1, Clock_change_enable_msc0), + Field(Msc_divider0, 1, Clock_busy_msc0), + Field(Msc_divider0, 0xff, Clock_divider_msc0)); Clock clock_msc1(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Msc_divider1, Clock_source_msc1, - Clock_gate0, Clock_gate_msc1, - Msc_divider1, Clock_change_enable_msc1, - Msc_divider1, Clock_busy_msc1, - Msc_divider1, Clock_divider_msc1, 0xff); + Field(Msc_divider1, 3, Clock_source_msc1), + Field(Clock_gate0, 1, Clock_gate_msc1), + Field(Msc_divider1, 1, Clock_change_enable_msc1), + Field(Msc_divider1, 1, Clock_busy_msc1), + Field(Msc_divider1, 0xff, Clock_divider_msc1)); Clock clock_none; Clock clock_pclock(1, Clock_inputs(Clock_ahb2_apb), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_apb0, - Reg_undefined, Clock_change_enable_undefined, - Reg_undefined, Clock_busy_undefined, - Clock_control, Clock_divider_pclock, 0x0f); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_apb0), + Change_enable_undefined, + Busy_undefined, + Field(Clock_control, 0x0f, Clock_divider_pclock)); Pll clock_pll_A(1, Clock_inputs(Clock_external), Pll_control_A, Pll_bypass_A); @@ -583,29 +569,29 @@ Pll_control_M, Pll_bypass_M); Clock clock_pwm(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Pwm_divider, Clock_source_pwm, - Clock_gate1, Clock_gate_pwm, - Pwm_divider, Clock_change_enable_pwm, - Pwm_divider, Clock_busy_pwm, - Pwm_divider, Clock_divider_pwm, 0x0f); + Field(Pwm_divider, 3, Clock_source_pwm), + Field(Clock_gate1, 1, Clock_gate_pwm), + Field(Pwm_divider, 1, Clock_change_enable_pwm), + Field(Pwm_divider, 1, Clock_busy_pwm), + Field(Pwm_divider, 0x0f, Clock_divider_pwm)); Clock clock_pwm0(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Pwm_divider, Clock_source_pwm, - Clock_gate1, Clock_gate_pwm, - Pwm_divider, Clock_change_enable_pwm, - Pwm_divider, Clock_busy_pwm, - Pwm_divider, Clock_divider_pwm, 0x0f); + Field(Pwm_divider, 3, Clock_source_pwm), + Field(Clock_gate1, 1, Clock_gate_pwm), + Field(Pwm_divider, 1, Clock_change_enable_pwm), + Field(Pwm_divider, 1, Clock_busy_pwm), + Field(Pwm_divider, 0x0f, Clock_divider_pwm)); Clock clock_pwm1; Clock clock_scc; Clock clock_sfc(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Sfc_divider, Clock_source_sfc, - Clock_gate0, Clock_gate_sfc, - Sfc_divider, Clock_change_enable_sfc, - Sfc_divider, Clock_busy_sfc, - Sfc_divider, Clock_divider_sfc, 0xff); + Field(Sfc_divider, 3, Clock_source_sfc), + Field(Clock_gate0, 1, Clock_gate_sfc), + Field(Sfc_divider, 1, Clock_change_enable_sfc), + Field(Sfc_divider, 1, Clock_busy_sfc), + Field(Sfc_divider, 0xff, Clock_divider_sfc)); Clock clock_smb0; @@ -618,31 +604,31 @@ Clock clock_smb4; Clock clock_ssi(3, Clock_inputs(Clock_main, Clock_pll_M, Clock_pll_E), - Ssi_divider, Clock_source_ssi, - Clock_gate0, Clock_gate_ssi0, - Ssi_divider, Clock_change_enable_ssi, - Ssi_divider, Clock_busy_ssi, - Ssi_divider, Clock_divider_ssi, 0xff); + Field(Ssi_divider, 3, Clock_source_ssi), + Field(Clock_gate0, 1, Clock_gate_ssi0), + Field(Ssi_divider, 1, Clock_change_enable_ssi), + Field(Ssi_divider, 1, Clock_busy_ssi), + Field(Ssi_divider, 0xff, Clock_divider_ssi)); Clock clock_timer(1, Clock_inputs(Clock_pclock), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_timer); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_timer)); Clock clock_uart0(1, Clock_inputs(Clock_external), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_uart0); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_uart0)); Clock clock_uart1(1, Clock_inputs(Clock_external), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_uart1); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_uart1)); Clock clock_uart2(1, Clock_inputs(Clock_external), - Reg_undefined, Clock_source_undefined, - Clock_gate0, Clock_gate_uart2); + Source_undefined, + Field(Clock_gate0, 1, Clock_gate_uart2)); Clock clock_uart3(1, Clock_inputs(Clock_external), - Reg_undefined, Clock_source_undefined, - Clock_gate1, Clock_gate_uart3); + Source_undefined, + Field(Clock_gate1, 1, Clock_gate_uart3)); Clock clock_udc; @@ -736,6 +722,26 @@ +// Field methods. + +uint32_t +Field::get_field(Cpm_regs ®s) +{ + if (defined) + return regs.get_field(reg, mask, bit); + else + return 0; +} + +void +Field::set_field(Cpm_regs ®s, uint32_t value) +{ + if (defined) + regs.set_field(reg, mask, bit, value); +} + + + // Clock control. int @@ -778,8 +784,8 @@ uint8_t Clock_base::get_source(Cpm_regs ®s) { - if (source_bit != Clock_source_undefined) - return regs.get_field(source_reg, Source_mask, source_bit); + if (_source.is_defined()) + return _source.get_field(regs); else return 0; } @@ -787,10 +793,10 @@ void Clock_base::set_source(Cpm_regs ®s, uint8_t source) { - if (source_bit == Clock_source_undefined) + if (_source.is_defined()) return; - regs.set_field(source_reg, Source_mask, source_bit, source); + _source.set_field(regs, source); } // Clock source frequencies. @@ -959,22 +965,22 @@ void Clock::change_disable(Cpm_regs ®s) { - if (change_enable_bit != Clock_change_enable_undefined) - regs.set_field(change_enable_reg, 1, change_enable_bit, 0); + if (_change_enable.is_defined()) + _change_enable.set_field(regs, 0); } void Clock::change_enable(Cpm_regs ®s) { - if (change_enable_bit != Clock_change_enable_undefined) - regs.set_field(change_enable_reg, 1, change_enable_bit, 1); + if (_change_enable.is_defined()) + _change_enable.set_field(regs, 1); } int Clock::have_clock(Cpm_regs ®s) { - if (gate_bit != Clock_gate_undefined) - return !regs.get_field(gate_reg, 1, gate_bit); + if (_gate.is_defined()) + return !_gate.get_field(regs); else return true; } @@ -982,22 +988,22 @@ void Clock::start_clock(Cpm_regs ®s) { - if (gate_bit != Clock_gate_undefined) - regs.set_field(gate_reg, 1, gate_bit, 0); + if (_gate.is_defined()) + _gate.set_field(regs, 0); } void Clock::stop_clock(Cpm_regs ®s) { - if (gate_bit != Clock_gate_undefined) - regs.set_field(gate_reg, 1, gate_bit, 1); + if (_gate.is_defined()) + _gate.set_field(regs, 1); } void Clock::wait_busy(Cpm_regs ®s) { - if (busy_bit != Clock_busy_undefined) - while (regs.get_field(busy_reg, 1, busy_bit)); + if (_busy.is_defined()) + while (_busy.get_field(regs)); } @@ -1007,8 +1013,8 @@ uint32_t Clock::get_divider(Cpm_regs ®s) { - if (divider_bit != Clock_divider_undefined) - return regs.get_field(divider_reg, divider_mask, divider_bit) + 1; + if (_divider.is_defined()) + return _divider.get_field(regs) + 1; else return 1; } @@ -1016,11 +1022,11 @@ void Clock::set_divider(Cpm_regs ®s, uint32_t division) { - if (divider_bit == Clock_divider_undefined) + if (_divider.is_defined()) return; change_enable(regs); - regs.set_field(divider_reg, divider_mask, divider_bit, division - 1); + _divider.set_field(regs, division - 1); wait_busy(regs); change_disable(regs); }