# HG changeset patch # User Paul Boddie # Date 1712183496 -7200 # Node ID f2cac5d96acd27ddbdef6d8d32014e8cb143a5f0 # Parent 2bb8d340c0c03e3e0001a33f12c6e77067eb0858 Introduced support for testing and updating divider register stop bits. Some clocks may have been left in a stopped configuration using this bit. diff -r 2bb8d340c0c0 -r f2cac5d96acd pkg/devices/lib/cpm/include/cpm-common.h --- a/pkg/devices/lib/cpm/include/cpm-common.h Thu Apr 04 00:26:27 2024 +0200 +++ b/pkg/devices/lib/cpm/include/cpm-common.h Thu Apr 04 00:31:36 2024 +0200 @@ -1,7 +1,7 @@ /* * Common clock functionality. * - * Copyright (C) 2023 Paul Boddie + * Copyright (C) 2023, 2024 Paul Boddie * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -189,19 +189,20 @@ class Control : public Control_base { - Field _gate, _change_enable, _busy; + Field _gate, _change_enable, _busy, _stop; public: explicit Control(Field gate, Field change_enable = Field::undefined, - Field busy = Field::undefined) - : _gate(gate), _change_enable(change_enable), _busy(busy) + Field busy = Field::undefined, + Field stop = Field::undefined) + : _gate(gate), _change_enable(change_enable), _busy(busy), _stop(stop) { } explicit Control() : _gate(Field::undefined), _change_enable(Field::undefined), - _busy(Field::undefined) + _busy(Field::undefined), _stop(Field::undefined) { } diff -r 2bb8d340c0c0 -r f2cac5d96acd pkg/devices/lib/cpm/src/common.cc --- a/pkg/devices/lib/cpm/src/common.cc Thu Apr 04 00:26:27 2024 +0200 +++ b/pkg/devices/lib/cpm/src/common.cc Thu Apr 04 00:31:36 2024 +0200 @@ -1,7 +1,7 @@ /* * Common clock functionality. * - * Copyright (C) 2023 Paul Boddie + * Copyright (C) 2023, 2024 Paul Boddie * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -164,10 +164,19 @@ int Control::have_clock(Cpm_regs ®s) { + bool enabled_via_gate, enabled_via_stop; + if (_gate.is_defined()) - return _gate.get_field(regs) == _gate.get_asserted(); + enabled_via_gate = _gate.get_field(regs) == _gate.get_asserted(); else - return true; + enabled_via_gate = true; + + if (_stop.is_defined()) + enabled_via_stop = _stop.get_field(regs) == _stop.get_asserted(); + else + enabled_via_stop = true; + + return enabled_via_gate && enabled_via_stop; } void @@ -175,6 +184,9 @@ { if (_gate.is_defined()) _gate.set_field(regs, _gate.get_asserted()); + + if (_stop.is_defined()) + _stop.set_field(regs, _stop.get_asserted()); } void @@ -182,6 +194,9 @@ { if (_gate.is_defined()) _gate.set_field(regs, _gate.get_deasserted()); + + if (_stop.is_defined()) + _stop.set_field(regs, _stop.get_deasserted()); } void diff -r 2bb8d340c0c0 -r f2cac5d96acd pkg/devices/lib/cpm/src/x1600.cc --- a/pkg/devices/lib/cpm/src/x1600.cc Thu Apr 04 00:26:27 2024 +0200 +++ b/pkg/devices/lib/cpm/src/x1600.cc Thu Apr 04 00:31:36 2024 +0200 @@ -102,6 +102,19 @@ Clock_source_sfc (Divider_sfc, 3, 30), // SFCS Clock_source_ssi (Divider_ssi, 3, 30), // SPCS + Clock_stop_ddr (Divider_ddr, 1, 27, true), + Clock_stop_mac (Divider_mac, 1, 27, true), + Clock_stop_lcd (Divider_lcd, 1, 27, true), + Clock_stop_msc0 (Divider_msc0, 1, 27, true), + Clock_stop_msc1 (Divider_msc1, 1, 27, true), + Clock_stop_sfc (Divider_sfc, 1, 27, true), + Clock_stop_ssi (Divider_ssi, 1, 27, true), + Clock_stop_cim (Divider_cim, 1, 27, true), + Clock_stop_pwm (Divider_pwm, 1, 27, true), + Clock_stop_can0 (Divider_can0, 1, 27, true), + Clock_stop_can1 (Divider_can1, 1, 27, true), + Clock_stop_cdbus (Divider_cdbus, 1, 27, true), + Clock_busy_cpu (Clock_status, 1, 0), Clock_busy_hclock0 (Clock_status, 1, 1), Clock_busy_hclock2 (Clock_status, 1, 2), @@ -321,19 +334,23 @@ static Clock_divided clock_can0(Source(mux_bus, Clock_source_can0), - Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0), + Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0, + Clock_stop_can0), Divider(Clock_divider_can0)), clock_can1(Source(mux_bus, Clock_source_can1), - Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1), + Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1, + Clock_stop_can1), Divider(Clock_divider_can1)), clock_cdbus(Source(mux_dev, Clock_source_cdbus), - Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus), + Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus, + Clock_stop_cdbus), Divider(Clock_divider_cdbus)), clock_cim(Source(mux_dev, Clock_source_cim), - Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim), + Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim, + Clock_stop_cim), Divider(Clock_divider_cim)), clock_cpu(Source(mux_core, Clock_source_cpu), @@ -341,7 +358,8 @@ Divider(Clock_divider_cpu)), clock_ddr(Source(mux_core, Clock_source_ddr), - Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr), + Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr, + Clock_stop_ddr), Divider(Clock_divider_ddr)), clock_hclock0(Source(mux_core, Clock_source_hclock0), @@ -355,33 +373,40 @@ Divider(Clock_divider_l2cache)), clock_lcd_pixel(Source(mux_dev, Clock_source_lcd), - Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd), + Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd, + Clock_stop_lcd), Divider(Clock_divider_lcd)), clock_mac(Source(mux_dev, Clock_source_mac), - Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac), + Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac, + Clock_stop_mac), Divider(Clock_divider_mac)), clock_msc0(Source(mux_dev, Clock_source_msc0), - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0), + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0, + Clock_stop_msc0), Divider(Clock_divider_msc0, 2)), clock_msc1(Source(mux_dev, Clock_source_msc1), - Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1), + Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1, + Clock_stop_msc1), Divider(Clock_divider_msc1, 2)), clock_pclock((Source(mux_hclock2_pclock)), (Divider(Clock_divider_pclock))), clock_pwm0(Source(mux_dev, Clock_source_pwm), - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm), + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm, + Clock_stop_pwm), Divider(Clock_divider_pwm)), clock_sfc(Source(mux_dev, Clock_source_sfc), - Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc), + Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc, + Clock_stop_sfc), Divider(Clock_divider_sfc)), clock_ssi0(Source(mux_dev, Clock_source_ssi), - Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi), + Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi, + Clock_stop_ssi), Divider(Clock_divider_ssi)); static Clock_divided_fixed