1.1 --- a/pkg/devices/lib/dma/include/dma-generic.h Wed Jun 05 13:51:55 2024 +0200
1.2 +++ b/pkg/devices/lib/dma/include/dma-generic.h Thu Jun 06 23:57:07 2024 +0200
1.3 @@ -66,6 +66,10 @@
1.4 (void) channel;
1.5 }
1.6
1.7 + virtual void clear_errors()
1.8 + {
1.9 + }
1.10 +
1.11 virtual bool error()
1.12 {
1.13 return false;
2.1 --- a/pkg/devices/lib/dma/include/dma-jz4730.h Wed Jun 05 13:51:55 2024 +0200
2.2 +++ b/pkg/devices/lib/dma/include/dma-jz4730.h Thu Jun 06 23:57:07 2024 +0200
2.3 @@ -148,6 +148,8 @@
2.4
2.5 void ack_irq();
2.6
2.7 + void clear_errors();
2.8 +
2.9 bool completed();
2.10
2.11 bool error();
3.1 --- a/pkg/devices/lib/dma/include/dma-jz4780.h Wed Jun 05 13:51:55 2024 +0200
3.2 +++ b/pkg/devices/lib/dma/include/dma-jz4780.h Thu Jun 06 23:57:07 2024 +0200
3.3 @@ -1,7 +1,7 @@
3.4 /*
3.5 * DMA support for the JZ4780.
3.6 *
3.7 - * Copyright (C) 2021, 2023 Paul Boddie <paul@boddie.org.uk>
3.8 + * Copyright (C) 2021, 2023, 2024 Paul Boddie <paul@boddie.org.uk>
3.9 *
3.10 * This program is free software; you can redistribute it and/or
3.11 * modify it under the terms of the GNU General Public License as
3.12 @@ -133,6 +133,8 @@
3.13
3.14 void ack_irq();
3.15
3.16 + void clear_errors();
3.17 +
3.18 bool completed();
3.19
3.20 bool error();
3.21 @@ -167,6 +169,8 @@
3.22
3.23 void ack_irq(uint8_t channel);
3.24
3.25 + void clear_errors();
3.26 +
3.27 bool error();
3.28
3.29 bool halted();
4.1 --- a/pkg/devices/lib/dma/include/dma-x1600.h Wed Jun 05 13:51:55 2024 +0200
4.2 +++ b/pkg/devices/lib/dma/include/dma-x1600.h Thu Jun 06 23:57:07 2024 +0200
4.3 @@ -1,7 +1,7 @@
4.4 /*
4.5 * DMA support for the X1600.
4.6 *
4.7 - * Copyright (C) 2021, 2023 Paul Boddie <paul@boddie.org.uk>
4.8 + * Copyright (C) 2021, 2023, 2024 Paul Boddie <paul@boddie.org.uk>
4.9 *
4.10 * This program is free software; you can redistribute it and/or
4.11 * modify it under the terms of the GNU General Public License as
4.12 @@ -129,6 +129,8 @@
4.13
4.14 void ack_irq();
4.15
4.16 + void clear_errors();
4.17 +
4.18 bool completed();
4.19
4.20 bool error();
4.21 @@ -162,6 +164,8 @@
4.22
4.23 void ack_irq(uint8_t channel);
4.24
4.25 + void clear_errors();
4.26 +
4.27 bool error();
4.28
4.29 bool halted();
5.1 --- a/pkg/devices/lib/dma/src/jz4730.cc Wed Jun 05 13:51:55 2024 +0200
5.2 +++ b/pkg/devices/lib/dma/src/jz4730.cc Thu Jun 06 23:57:07 2024 +0200
5.3 @@ -251,7 +251,10 @@
5.4 // Ensure an absence of address error and halt conditions globally and in this channel.
5.5
5.6 if (error() || halted())
5.7 - return 0;
5.8 + {
5.9 + printf("Cleared:%s%s\n", error() ? " error" : "", halted() ? " halted" : "");
5.10 + clear_errors();
5.11 + }
5.12
5.13 // Ensure an absence of transaction completed and zero transfer count for this channel.
5.14
5.15 @@ -371,6 +374,14 @@
5.16 _regs[Dma_control_status] = _regs[Dma_control_status] & ~Dma_trans_completed;
5.17 }
5.18
5.19 +// Clear error conditions.
5.20 +
5.21 +void
5.22 +Dma_jz4730_channel::clear_errors()
5.23 +{
5.24 + _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_address_error | Dma_trans_halted);
5.25 +}
5.26 +
5.27 // Return whether a transfer has completed.
5.28
5.29 bool
6.1 --- a/pkg/devices/lib/dma/src/jz4780.cc Wed Jun 05 13:51:55 2024 +0200
6.2 +++ b/pkg/devices/lib/dma/src/jz4780.cc Thu Jun 06 23:57:07 2024 +0200
6.3 @@ -275,7 +275,10 @@
6.4 // Ensure an absence of address error and halt conditions globally and in this channel.
6.5
6.6 if (error() || halted())
6.7 - return 0;
6.8 + {
6.9 + printf("Cleared:%s%s\n", error() ? " error" : "", halted() ? " halted" : "");
6.10 + clear_errors();
6.11 + }
6.12
6.13 // Ensure a zero transfer count for this channel.
6.14
6.15 @@ -427,6 +430,15 @@
6.16 _chip->ack_irq(_channel);
6.17 }
6.18
6.19 +// Clear error conditions.
6.20 +
6.21 +void
6.22 +Dma_jz4780_channel::clear_errors()
6.23 +{
6.24 + _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_address_error | Dma_trans_halted);
6.25 + _chip->clear_errors();
6.26 +}
6.27 +
6.28 // Return whether a transfer has completed.
6.29
6.30 bool
6.31 @@ -510,6 +522,14 @@
6.32 _regs[Dma_irq_pending] = _regs[Dma_irq_pending] & ~(1 << channel);
6.33 }
6.34
6.35 +// Clear error conditions.
6.36 +
6.37 +void
6.38 +Dma_jz4780_chip::clear_errors()
6.39 +{
6.40 + _regs[Dma_control] = _regs[Dma_control] & ~(Dma_control_address_error | Dma_control_trans_halted);
6.41 +}
6.42 +
6.43 // Return whether an address error condition has arisen.
6.44
6.45 bool
7.1 --- a/pkg/devices/lib/dma/src/x1600.cc Wed Jun 05 13:51:55 2024 +0200
7.2 +++ b/pkg/devices/lib/dma/src/x1600.cc Thu Jun 06 23:57:07 2024 +0200
7.3 @@ -259,7 +259,10 @@
7.4 // Ensure an absence of address error and halt conditions globally and in this channel.
7.5
7.6 if (error() || halted())
7.7 - return 0;
7.8 + {
7.9 + printf("Cleared:%s%s\n", error() ? " error" : "", halted() ? " halted" : "");
7.10 + clear_errors();
7.11 + }
7.12
7.13 // Ensure a zero transfer count for this channel.
7.14
7.15 @@ -336,7 +339,8 @@
7.16
7.17 // Enable the channel with descriptor transfer configured if appropriate.
7.18
7.19 - _regs[Dma_control_status] = Dma_no_descriptor_transfer |
7.20 + _regs[Dma_control_status] = (desc_vaddr ? Dma_8word_descriptor :
7.21 + Dma_no_descriptor_transfer) |
7.22 Dma_channel_enable;
7.23
7.24 // Return the number of units to transfer.
7.25 @@ -409,6 +413,15 @@
7.26 _chip->ack_irq(_channel);
7.27 }
7.28
7.29 +// Clear error conditions.
7.30 +
7.31 +void
7.32 +Dma_x1600_channel::clear_errors()
7.33 +{
7.34 + _regs[Dma_control_status] = _regs[Dma_control_status] & ~(Dma_address_error | Dma_trans_halted);
7.35 + _chip->clear_errors();
7.36 +}
7.37 +
7.38 // Return whether a transfer has completed.
7.39
7.40 bool
7.41 @@ -492,6 +505,14 @@
7.42 _regs[Dma_irq_pending] = _regs[Dma_irq_pending] & ~(1UL << channel);
7.43 }
7.44
7.45 +// Clear error conditions.
7.46 +
7.47 +void
7.48 +Dma_x1600_chip::clear_errors()
7.49 +{
7.50 + _regs[Dma_control] = _regs[Dma_control] & ~(Dma_control_address_error | Dma_control_trans_halted);
7.51 +}
7.52 +
7.53 // Return whether an address error condition has arisen.
7.54
7.55 bool