1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/pkg/devices/lib/lcd/include/lcd-jz4740-regs.h Sat Jun 06 01:22:18 2020 +0200
1.3 @@ -0,0 +1,301 @@
1.4 +/*
1.5 + * LCD peripheral support for the JZ4740 and related SoCs.
1.6 + *
1.7 + * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
1.8 + * Copyright (C) 2015, 2016, 2017, 2018,
1.9 + * 2020 Paul Boddie <paul@boddie.org.uk>
1.10 + *
1.11 + * This program is free software; you can redistribute it and/or
1.12 + * modify it under the terms of the GNU General Public License as
1.13 + * published by the Free Software Foundation; either version 2 of
1.14 + * the License, or (at your option) any later version.
1.15 + *
1.16 + * This program is distributed in the hope that it will be useful,
1.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.19 + * GNU General Public License for more details.
1.20 + *
1.21 + * You should have received a copy of the GNU General Public License
1.22 + * along with this program; if not, write to the Free Software
1.23 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
1.24 + * Boston, MA 02110-1301, USA
1.25 + */
1.26 +
1.27 +#pragma once
1.28 +
1.29 +
1.30 +
1.31 +enum Regs : unsigned
1.32 +{
1.33 + Lcd_config = 0x000, // LCD_CFG
1.34 + Lcd_vsync = 0x004, // LCD_VSYNC
1.35 + Lcd_hsync = 0x008, // LCD_HSYNC
1.36 + Virtual_area = 0x00c, // LCD_VAT
1.37 + Display_hlimits = 0x010, // LCD_DAH
1.38 + Display_vlimits = 0x014, // LCD_DAV
1.39 + Lcd_ps = 0x018, // LCD_PS
1.40 + Lcd_cls = 0x01c, // LCD_CLS
1.41 + Lcd_spl = 0x020, // LCD_SPL
1.42 + Lcd_rev = 0x024, // LCD_REV
1.43 + Lcd_control = 0x030, // LCD_CTRL
1.44 + Lcd_status = 0x034, // LCD_STATE
1.45 + Lcd_irq_id = 0x038, // LCD_IID
1.46 + Desc_address_0 = 0x040, // LCD_DA0
1.47 + Source_address_0 = 0x044, // LCD_SA0
1.48 + Frame_id_0 = 0x048, // LCD_FID0
1.49 + Command_0 = 0x04c, // LCD_CMD0
1.50 + Counter_position_0 = 0x068, // LCD_CPOS0
1.51 + Foreground_size_0 = 0x06c, // LCD_DESSIZE0
1.52 + Desc_address_1 = 0x050, // LCD_DA1
1.53 + Source_address_1 = 0x054, // LCD_SA1
1.54 + Frame_id_1 = 0x058, // LCD_FID1
1.55 + Command_1 = 0x05c, // LCD_CMD1
1.56 + Counter_position_1 = 0x078, // LCD_CPOS1
1.57 + Foreground_size_1 = 0x07c, // LCD_DESSIZE1
1.58 + Rgb_control = 0x090, // LCD_RGBC (JZ4780)
1.59 + Alpha_levels = 0x108, // LCD_ALPHA (JZ4780)
1.60 + Priority_level = 0x2c0, // LCD_PCFG
1.61 +
1.62 + // OSD registers.
1.63 +
1.64 + Osd_config = 0x100, // LCD_OSDC
1.65 + Osd_control = 0x104, // LCD_OSDCTRL
1.66 + Osd_status = 0x108, // LCD_OSDS
1.67 +};
1.68 +
1.69 +// Lcd_config descriptions.
1.70 +
1.71 +enum Config_values : unsigned
1.72 +{
1.73 + Config_stn_pins_mask = 0x3,
1.74 + Config_mode_mask = 0xf,
1.75 +};
1.76 +
1.77 +// Field positions for registers employing two values, with the first typically
1.78 +// being the start value and the second being an end value.
1.79 +
1.80 +enum Value_pair_bits : unsigned
1.81 +{
1.82 + Value_first = 16,
1.83 + Value_second = 0,
1.84 +};
1.85 +
1.86 +// Virtual area bits.
1.87 +
1.88 +enum Virtual_area_values : unsigned
1.89 +{
1.90 + Virtual_area_horizontal_size = Value_first, // sum of display and blank regions (dot/pixel clock periods)
1.91 + Virtual_area_vertical_size = Value_second, // sum of display and blank regions (line periods)
1.92 +};
1.93 +
1.94 +// Lcd_control descriptions.
1.95 +
1.96 +enum Control_bits : unsigned
1.97 +{
1.98 + Control_pin_modify = 31, // PINMD (change pin usage from 15..0 to 17..10, 8..1)
1.99 + Control_burst_length = 28, // BST (burst length selection)
1.100 + Control_rgb_mode = 27, // RGB (RGB mode)
1.101 + Control_out_underrun = 26, // OFUP (output FIFO underrun protection)
1.102 + Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection)
1.103 + Control_palette_delay = 16, // PDD (load palette delay counter)
1.104 + Control_dac_loopback_test = 14, // DACTE (DAC loopback test)
1.105 + Control_frame_end_irq_enable = 13, // EOFM (end of frame interrupt enable)
1.106 + Control_frame_start_irq_enable = 12, // SOFM (start of frame interrupt enable)
1.107 + Control_out_underrun_irq_enable = 11, // OFUM (output FIFO underrun interrupt enable)
1.108 + Control_in0_underrun_irq_enable = 10, // IFUM0 (input FIFO 0 underrun interrupt enable)
1.109 + Control_in1_underrun_irq_enable = 9, // IFUM1 (input FIFO 1 underrun interrupt enable)
1.110 + Control_disabled_irq_enable = 8, // LDDM (LCD disable done interrupt enable)
1.111 + Control_quick_disabled_irq_enable = 7, // QDM (LCD quick disable done interrupt enable)
1.112 + Control_endian_select = 6, // BEDN (endian selection)
1.113 + Control_bit_order = 5, // PEDN (bit order in bytes)
1.114 + Control_disable = 4, // DIS (disable controller)
1.115 + Control_enable = 3, // ENA (enable controller)
1.116 + Control_bpp = 0, // BPP (bits per pixel)
1.117 +};
1.118 +
1.119 +enum Burst_length_values : unsigned
1.120 +{
1.121 + Burst_length_4 = 0, // 4 word
1.122 + Burst_length_8 = 1, // 8 word
1.123 + Burst_length_16 = 2, // 16 word
1.124 +
1.125 + // JZ4780 extensions.
1.126 +
1.127 + Burst_length_32 = 3, // 32 word
1.128 + Burst_length_64 = 4, // 64 word
1.129 + Burst_length_mask = 0x7,
1.130 +};
1.131 +
1.132 +enum Rgb_mode_values : unsigned
1.133 +{
1.134 + Rgb_mode_565 = 0,
1.135 + Rgb_mode_555 = 1,
1.136 + Rgb_mode_mask = 0x1,
1.137 +};
1.138 +
1.139 +enum Frc_algorithm_values : unsigned
1.140 +{
1.141 + Frc_greyscales_16 = 0,
1.142 + Frc_greyscales_4 = 1,
1.143 + Frc_greyscales_2 = 2,
1.144 + Frc_greyscales_mask = 0x3,
1.145 +};
1.146 +
1.147 +enum Control_bpp_values : unsigned
1.148 +{
1.149 + Control_bpp_1bpp = 0,
1.150 + Control_bpp_2bpp = 1,
1.151 + Control_bpp_4bpp = 2,
1.152 + Control_bpp_8bpp = 3,
1.153 + Control_bpp_15bpp = 4,
1.154 + Control_bpp_16bpp = 4,
1.155 + Control_bpp_18bpp = 5,
1.156 + Control_bpp_24bpp = 5,
1.157 + Control_bpp_24bpp_comp = 6,
1.158 + Control_bpp_30bpp = 7,
1.159 + Control_bpp_32bpp = 7,
1.160 + Control_bpp_mask = 0x7,
1.161 +};
1.162 +
1.163 +// Command descriptions.
1.164 +
1.165 +enum Command_bits : unsigned
1.166 +{
1.167 + Command_frame_start_irq = 31, // SOFINT (start of frame interrupt)
1.168 + Command_frame_end_irq = 30, // EOFINT (end of frame interrupt)
1.169 + Command_lcm_command = 29, // JZ4780: CMD (LCM command/data via DMA0)
1.170 + Command_palette_buffer = 28, // PAL (descriptor references palette, not display data)
1.171 + Command_frame_compressed = 27, // JZ4780: COMPEN (16/24bpp compression enabled)
1.172 + Command_frame_enable = 26, // JZ4780: FRM_EN
1.173 + Command_field_even = 25, // JZ4780: FIELD_SEL (interlace even field)
1.174 + Command_16x16_block = 24, // JZ4780: 16x16BLOCK (fetch data by 16x16 block)
1.175 + Command_buffer_length = 0, // LEN
1.176 +};
1.177 +
1.178 +enum Command_values : unsigned
1.179 +{
1.180 + Command_buffer_length_mask = 0x00ffffff,
1.181 +};
1.182 +
1.183 +// Status descriptions.
1.184 +
1.185 +enum Status_bits : unsigned
1.186 +{
1.187 + Status_frame_end_irq = 5,
1.188 + Status_frame_start_irq = 4,
1.189 + Status_out_underrun_irq = 3,
1.190 + Status_in0_underrun_irq = 2,
1.191 + Status_in1_underrun_irq = 1,
1.192 + Status_disabled = 0,
1.193 +};
1.194 +
1.195 +// OSD configuration bits (JZ4780).
1.196 +
1.197 +enum Osd_config_bits : unsigned
1.198 +{
1.199 + Osd_config_fg1_pixel_alpha_enable = 17,
1.200 + Osd_config_fg1_frame_start_irq_enable = 15,
1.201 + Osd_config_fg1_frame_end_irq_enable = 14,
1.202 + Osd_config_fg0_frame_start_irq_enable = 11,
1.203 + Osd_config_fg0_frame_end_irq_enable = 10,
1.204 + Osd_config_fg1_enable = 4,
1.205 + Osd_config_fg0_enable = 3,
1.206 + Osd_config_alpha_enable = 2,
1.207 + Osd_config_fg0_pixel_alpha_enable = 1,
1.208 + Osd_config_enable = 0,
1.209 +};
1.210 +
1.211 +enum Osd_control_bits : unsigned
1.212 +{
1.213 + Osd_control_ipu_clock_enable = 15,
1.214 +};
1.215 +
1.216 +// RGB control (JZ4780).
1.217 +
1.218 +enum Rgb_control_bits : unsigned
1.219 +{
1.220 + Rgb_data_padded = 15, // RGBDM
1.221 + Rgb_padding_mode = 14, // DMM
1.222 + Rgb_422 = 8, // 422
1.223 + Rgb_format_enable = 7, // RGBFMT
1.224 + Rgb_odd_line = 4, // OddRGB
1.225 + Rgb_even_line = 0, // EvenRGB
1.226 +};
1.227 +
1.228 +enum Rgb_control_values : unsigned
1.229 +{
1.230 + Rgb_padding_end = 0U << Rgb_padding_mode,
1.231 + Rgb_padding_start = 1U << Rgb_padding_mode,
1.232 + Rgb_odd_line_rgb = 0U << Rgb_odd_line,
1.233 + Rgb_odd_line_rbg = 1U << Rgb_odd_line,
1.234 + Rgb_odd_line_grb = 2U << Rgb_odd_line,
1.235 + Rgb_odd_line_gbr = 3U << Rgb_odd_line,
1.236 + Rgb_odd_line_brg = 4U << Rgb_odd_line,
1.237 + Rgb_odd_line_bgr = 5U << Rgb_odd_line,
1.238 + Rgb_even_line_rgb = 0U << Rgb_even_line,
1.239 + Rgb_even_line_rbg = 1U << Rgb_even_line,
1.240 + Rgb_even_line_grb = 2U << Rgb_even_line,
1.241 + Rgb_even_line_gbr = 3U << Rgb_even_line,
1.242 + Rgb_even_line_brg = 4U << Rgb_even_line,
1.243 + Rgb_even_line_bgr = 5U << Rgb_even_line,
1.244 +};
1.245 +
1.246 +// Alpha levels (JZ4780).
1.247 +
1.248 +enum Alpha_levels_bits : unsigned
1.249 +{
1.250 + Alpha_level_fg1 = 8,
1.251 + Alpha_level_fg0 = 0,
1.252 +};
1.253 +
1.254 +enum Alpha_levels_values : unsigned
1.255 +{
1.256 + Alpha_level_fg1_mask = 0x0000ff00,
1.257 + Alpha_level_fg0_mask = 0x000000ff,
1.258 +};
1.259 +
1.260 +// Priority level.
1.261 +
1.262 +enum Priority_level_bits : unsigned
1.263 +{
1.264 + Priority_mode = 31,
1.265 + Priority_highest_burst = 28,
1.266 + Priority_threshold2 = 18,
1.267 + Priority_threshold1 = 9,
1.268 + Priority_threshold0 = 0,
1.269 +};
1.270 +
1.271 +enum Priority_level_values : unsigned
1.272 +{
1.273 + Priority_mode_dynamic = 0U << Priority_mode,
1.274 + Priority_mode_arbiter = 1U << Priority_mode,
1.275 +};
1.276 +
1.277 +enum Priority_burst_values : unsigned
1.278 +{
1.279 + Priority_burst_4 = 0,
1.280 + Priority_burst_8 = 1,
1.281 + Priority_burst_16 = 2,
1.282 + Priority_burst_32 = 3,
1.283 + Priority_burst_64 = 4,
1.284 + Priority_burst_16_cont = 5,
1.285 + Priority_burst_disable = 7,
1.286 +};
1.287 +
1.288 +// Position descriptor member.
1.289 +
1.290 +enum Position_bits : unsigned
1.291 +{
1.292 + Position_bpp = 27,
1.293 + Position_premultiply_lcd = 26,
1.294 + Position_coefficient = 24,
1.295 + Position_y_position = 12,
1.296 + Position_x_position = 0,
1.297 +};
1.298 +
1.299 +enum Position_values : unsigned
1.300 +{
1.301 + Position_bpp_15_16bpp = 4,
1.302 + Position_bpp_18_24bpp = 5,
1.303 + Position_bpp_30bpp = 7,
1.304 +};
2.1 --- a/pkg/devices/lib/lcd/include/lcd-jz4740.h Sat Jun 06 00:04:50 2020 +0200
2.2 +++ b/pkg/devices/lib/lcd/include/lcd-jz4740.h Sat Jun 06 01:22:18 2020 +0200
2.3 @@ -68,7 +68,7 @@
2.4
2.5 class Lcd_jz4740_chip : public Lcd_chip
2.6 {
2.7 -private:
2.8 +protected:
2.9 Hw::Register_block<32> _regs;
2.10 Jz4740_lcd_panel *_panel;
2.11 int _burst_size;
2.12 @@ -95,14 +95,6 @@
2.13
2.14 uint32_t _status_irq();
2.15
2.16 - /* Priority level threshold value calculation. */
2.17 -
2.18 - uint32_t _priority_transfer();
2.19 -
2.20 - /* Position value calculation. */
2.21 -
2.22 - uint32_t _position_bpp();
2.23 -
2.24 /* Panel mode access. */
2.25
2.26 uint32_t _mode();
2.27 @@ -115,9 +107,9 @@
2.28
2.29 /* Descriptor initialisation. */
2.30
2.31 - void _set_descriptor(struct Jz4740_lcd_descriptor &desc, l4_addr_t source,
2.32 - l4_size_t size, struct Jz4740_lcd_descriptor *next,
2.33 - uint32_t flags = 0, bool frame_enable = true);
2.34 + virtual void _set_descriptor(struct Jz4740_lcd_descriptor &desc, l4_addr_t source,
2.35 + l4_size_t size, struct Jz4740_lcd_descriptor *next,
2.36 + uint32_t flags = 0);
2.37
2.38 public:
2.39 Lcd_jz4740_chip(l4_addr_t addr, Jz4740_lcd_panel *panel);
2.40 @@ -167,9 +159,9 @@
2.41
2.42 /* Configuration. */
2.43
2.44 - void config(struct Jz4740_lcd_descriptor *desc_vaddr,
2.45 - struct Jz4740_lcd_descriptor *desc_paddr,
2.46 - l4_addr_t fb_paddr);
2.47 + virtual void config(struct Jz4740_lcd_descriptor *desc_vaddr,
2.48 + struct Jz4740_lcd_descriptor *desc_paddr,
2.49 + l4_addr_t fb_paddr);
2.50
2.51 /* Interrupt configuration. */
2.52
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
3.2 +++ b/pkg/devices/lib/lcd/include/lcd-jz4780.h Sat Jun 06 01:22:18 2020 +0200
3.3 @@ -0,0 +1,71 @@
3.4 +/*
3.5 + * LCD peripheral support for the JZ4780 and related SoCs.
3.6 + *
3.7 + * Copyright (C) 2018, 2020 Paul Boddie <paul@boddie.org.uk>
3.8 + *
3.9 + * This program is free software; you can redistribute it and/or
3.10 + * modify it under the terms of the GNU General Public License as
3.11 + * published by the Free Software Foundation; either version 2 of
3.12 + * the License, or (at your option) any later version.
3.13 + *
3.14 + * This program is distributed in the hope that it will be useful,
3.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3.17 + * GNU General Public License for more details.
3.18 + *
3.19 + * You should have received a copy of the GNU General Public License
3.20 + * along with this program; if not, write to the Free Software
3.21 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
3.22 + * Boston, MA 02110-1301, USA
3.23 + */
3.24 +
3.25 +#pragma once
3.26 +
3.27 +#include "lcd-jz4740.h"
3.28 +
3.29 +
3.30 +
3.31 +/* C++ language interface. */
3.32 +
3.33 +#ifdef __cplusplus
3.34 +
3.35 +#include <l4/devices/hw_mmio_register_block.h>
3.36 +
3.37 +class Lcd_jz4780_chip : public Lcd_jz4740_chip
3.38 +{
3.39 +protected:
3.40 + /* Priority level threshold value calculation. */
3.41 +
3.42 + uint32_t _priority_transfer();
3.43 +
3.44 + /* Position value calculation. */
3.45 +
3.46 + uint32_t _position_bpp();
3.47 +
3.48 + /* Descriptor initialisation. */
3.49 +
3.50 + void _set_descriptor(struct Jz4740_lcd_descriptor &desc, l4_addr_t source,
3.51 + l4_size_t size, struct Jz4740_lcd_descriptor *next,
3.52 + uint32_t flags = 0, bool frame_enable = true);
3.53 +
3.54 +public:
3.55 + Lcd_jz4780_chip(l4_addr_t addr, Jz4740_lcd_panel *panel);
3.56 +
3.57 + /* Configuration. */
3.58 +
3.59 + void config(struct Jz4740_lcd_descriptor *desc_vaddr,
3.60 + struct Jz4740_lcd_descriptor *desc_paddr,
3.61 + l4_addr_t fb_paddr);
3.62 +};
3.63 +
3.64 +#endif
3.65 +
3.66 +
3.67 +
3.68 +/* C language interface mainly provided by jz4740_lcd functions. */
3.69 +
3.70 +EXTERN_C_BEGIN
3.71 +
3.72 +void *jz4780_lcd_init(l4_addr_t lcd_base, struct Jz4740_lcd_panel *panel);
3.73 +
3.74 +EXTERN_C_END
4.1 --- a/pkg/devices/lib/lcd/src/jz4740/Makefile Sat Jun 06 00:04:50 2020 +0200
4.2 +++ b/pkg/devices/lib/lcd/src/jz4740/Makefile Sat Jun 06 01:22:18 2020 +0200
4.3 @@ -1,10 +1,10 @@
4.4 PKGDIR ?= ../../../..
4.5 L4DIR ?= $(PKGDIR)/../..
4.6
4.7 -TARGET = liblcd_jz4740.o.a liblcd_jz4740.o.so
4.8 +TARGET = liblcd_jz4740.o.a
4.9 PC_FILENAME := libdrivers-lcd-jz4740
4.10
4.11 -SRC_CC := lcd-jz4740.cc
4.12 +SRC_CC := lcd-jz4740.cc lcd-jz4780.cc
4.13
4.14 PRIVATE_INCDIR += $(PKGDIR)/lib/lcd/include
4.15
5.1 --- a/pkg/devices/lib/lcd/src/jz4740/lcd-jz4740.cc Sat Jun 06 00:04:50 2020 +0200
5.2 +++ b/pkg/devices/lib/lcd/src/jz4740/lcd-jz4740.cc Sat Jun 06 01:22:18 2020 +0200
5.3 @@ -29,284 +29,10 @@
5.4
5.5 #include "lcd-jz4740.h"
5.6 #include "lcd-jz4740-config.h"
5.7 +#include "lcd-jz4740-regs.h"
5.8
5.9 #include <stdint.h>
5.10
5.11 -enum Regs : unsigned
5.12 -{
5.13 - Lcd_config = 0x000, // LCD_CFG
5.14 - Lcd_vsync = 0x004, // LCD_VSYNC
5.15 - Lcd_hsync = 0x008, // LCD_HSYNC
5.16 - Virtual_area = 0x00c, // LCD_VAT
5.17 - Display_hlimits = 0x010, // LCD_DAH
5.18 - Display_vlimits = 0x014, // LCD_DAV
5.19 - Lcd_ps = 0x018, // LCD_PS
5.20 - Lcd_cls = 0x01c, // LCD_CLS
5.21 - Lcd_spl = 0x020, // LCD_SPL
5.22 - Lcd_rev = 0x024, // LCD_REV
5.23 - Lcd_control = 0x030, // LCD_CTRL
5.24 - Lcd_status = 0x034, // LCD_STATE
5.25 - Lcd_irq_id = 0x038, // LCD_IID
5.26 - Desc_address_0 = 0x040, // LCD_DA0
5.27 - Source_address_0 = 0x044, // LCD_SA0
5.28 - Frame_id_0 = 0x048, // LCD_FID0
5.29 - Command_0 = 0x04c, // LCD_CMD0
5.30 - Counter_position_0 = 0x068, // LCD_CPOS0
5.31 - Foreground_size_0 = 0x06c, // LCD_DESSIZE0
5.32 - Desc_address_1 = 0x050, // LCD_DA1
5.33 - Source_address_1 = 0x054, // LCD_SA1
5.34 - Frame_id_1 = 0x058, // LCD_FID1
5.35 - Command_1 = 0x05c, // LCD_CMD1
5.36 - Counter_position_1 = 0x078, // LCD_CPOS1
5.37 - Foreground_size_1 = 0x07c, // LCD_DESSIZE1
5.38 - Rgb_control = 0x090, // LCD_RGBC (JZ4780)
5.39 - Alpha_levels = 0x108, // LCD_ALPHA (JZ4780)
5.40 - Priority_level = 0x2c0, // LCD_PCFG
5.41 -
5.42 - // OSD registers.
5.43 -
5.44 - Osd_config = 0x100, // LCD_OSDC
5.45 - Osd_control = 0x104, // LCD_OSDCTRL
5.46 - Osd_status = 0x108, // LCD_OSDS
5.47 -};
5.48 -
5.49 -// Lcd_config descriptions.
5.50 -
5.51 -enum Config_values : unsigned
5.52 -{
5.53 - Config_stn_pins_mask = 0x3,
5.54 - Config_mode_mask = 0xf,
5.55 -};
5.56 -
5.57 -// Field positions for registers employing two values, with the first typically
5.58 -// being the start value and the second being an end value.
5.59 -
5.60 -enum Value_pair_bits : unsigned
5.61 -{
5.62 - Value_first = 16,
5.63 - Value_second = 0,
5.64 -};
5.65 -
5.66 -// Virtual area bits.
5.67 -
5.68 -enum Virtual_area_values : unsigned
5.69 -{
5.70 - Virtual_area_horizontal_size = Value_first, // sum of display and blank regions (dot/pixel clock periods)
5.71 - Virtual_area_vertical_size = Value_second, // sum of display and blank regions (line periods)
5.72 -};
5.73 -
5.74 -// Lcd_control descriptions.
5.75 -
5.76 -enum Control_bits : unsigned
5.77 -{
5.78 - Control_pin_modify = 31, // PINMD (change pin usage from 15..0 to 17..10, 8..1)
5.79 - Control_burst_length = 28, // BST (burst length selection)
5.80 - Control_rgb_mode = 27, // RGB (RGB mode)
5.81 - Control_out_underrun = 26, // OFUP (output FIFO underrun protection)
5.82 - Control_frc_algorithm = 24, // FRC (STN FRC algorithm selection)
5.83 - Control_palette_delay = 16, // PDD (load palette delay counter)
5.84 - Control_dac_loopback_test = 14, // DACTE (DAC loopback test)
5.85 - Control_frame_end_irq_enable = 13, // EOFM (end of frame interrupt enable)
5.86 - Control_frame_start_irq_enable = 12, // SOFM (start of frame interrupt enable)
5.87 - Control_out_underrun_irq_enable = 11, // OFUM (output FIFO underrun interrupt enable)
5.88 - Control_in0_underrun_irq_enable = 10, // IFUM0 (input FIFO 0 underrun interrupt enable)
5.89 - Control_in1_underrun_irq_enable = 9, // IFUM1 (input FIFO 1 underrun interrupt enable)
5.90 - Control_disabled_irq_enable = 8, // LDDM (LCD disable done interrupt enable)
5.91 - Control_quick_disabled_irq_enable = 7, // QDM (LCD quick disable done interrupt enable)
5.92 - Control_endian_select = 6, // BEDN (endian selection)
5.93 - Control_bit_order = 5, // PEDN (bit order in bytes)
5.94 - Control_disable = 4, // DIS (disable controller)
5.95 - Control_enable = 3, // ENA (enable controller)
5.96 - Control_bpp = 0, // BPP (bits per pixel)
5.97 -};
5.98 -
5.99 -enum Burst_length_values : unsigned
5.100 -{
5.101 - Burst_length_4 = 0, // 4 word
5.102 - Burst_length_8 = 1, // 8 word
5.103 - Burst_length_16 = 2, // 16 word
5.104 -
5.105 - // JZ4780 extensions.
5.106 -
5.107 - Burst_length_32 = 3, // 32 word
5.108 - Burst_length_64 = 4, // 64 word
5.109 - Burst_length_mask = 0x7,
5.110 -};
5.111 -
5.112 -enum Rgb_mode_values : unsigned
5.113 -{
5.114 - Rgb_mode_565 = 0,
5.115 - Rgb_mode_555 = 1,
5.116 - Rgb_mode_mask = 0x1,
5.117 -};
5.118 -
5.119 -enum Frc_algorithm_values : unsigned
5.120 -{
5.121 - Frc_greyscales_16 = 0,
5.122 - Frc_greyscales_4 = 1,
5.123 - Frc_greyscales_2 = 2,
5.124 - Frc_greyscales_mask = 0x3,
5.125 -};
5.126 -
5.127 -enum Control_bpp_values : unsigned
5.128 -{
5.129 - Control_bpp_1bpp = 0,
5.130 - Control_bpp_2bpp = 1,
5.131 - Control_bpp_4bpp = 2,
5.132 - Control_bpp_8bpp = 3,
5.133 - Control_bpp_15bpp = 4,
5.134 - Control_bpp_16bpp = 4,
5.135 - Control_bpp_18bpp = 5,
5.136 - Control_bpp_24bpp = 5,
5.137 - Control_bpp_24bpp_comp = 6,
5.138 - Control_bpp_30bpp = 7,
5.139 - Control_bpp_32bpp = 7,
5.140 - Control_bpp_mask = 0x7,
5.141 -};
5.142 -
5.143 -// Command descriptions.
5.144 -
5.145 -enum Command_bits : unsigned
5.146 -{
5.147 - Command_frame_start_irq = 31, // SOFINT (start of frame interrupt)
5.148 - Command_frame_end_irq = 30, // EOFINT (end of frame interrupt)
5.149 - Command_lcm_command = 29, // JZ4780: CMD (LCM command/data via DMA0)
5.150 - Command_palette_buffer = 28, // PAL (descriptor references palette, not display data)
5.151 - Command_frame_compressed = 27, // JZ4780: COMPEN (16/24bpp compression enabled)
5.152 - Command_frame_enable = 26, // JZ4780: FRM_EN
5.153 - Command_field_even = 25, // JZ4780: FIELD_SEL (interlace even field)
5.154 - Command_16x16_block = 24, // JZ4780: 16x16BLOCK (fetch data by 16x16 block)
5.155 - Command_buffer_length = 0, // LEN
5.156 -};
5.157 -
5.158 -enum Command_values : unsigned
5.159 -{
5.160 - Command_buffer_length_mask = 0x00ffffff,
5.161 -};
5.162 -
5.163 -// Status descriptions.
5.164 -
5.165 -enum Status_bits : unsigned
5.166 -{
5.167 - Status_frame_end_irq = 5,
5.168 - Status_frame_start_irq = 4,
5.169 - Status_out_underrun_irq = 3,
5.170 - Status_in0_underrun_irq = 2,
5.171 - Status_in1_underrun_irq = 1,
5.172 - Status_disabled = 0,
5.173 -};
5.174 -
5.175 -// OSD configuration bits (JZ4780).
5.176 -
5.177 -enum Osd_config_bits : unsigned
5.178 -{
5.179 - Osd_config_fg1_pixel_alpha_enable = 17,
5.180 - Osd_config_fg1_frame_start_irq_enable = 15,
5.181 - Osd_config_fg1_frame_end_irq_enable = 14,
5.182 - Osd_config_fg0_frame_start_irq_enable = 11,
5.183 - Osd_config_fg0_frame_end_irq_enable = 10,
5.184 - Osd_config_fg1_enable = 4,
5.185 - Osd_config_fg0_enable = 3,
5.186 - Osd_config_alpha_enable = 2,
5.187 - Osd_config_fg0_pixel_alpha_enable = 1,
5.188 - Osd_config_enable = 0,
5.189 -};
5.190 -
5.191 -enum Osd_control_bits : unsigned
5.192 -{
5.193 - Osd_control_ipu_clock_enable = 15,
5.194 -};
5.195 -
5.196 -// RGB control (JZ4780).
5.197 -
5.198 -enum Rgb_control_bits : unsigned
5.199 -{
5.200 - Rgb_data_padded = 15, // RGBDM
5.201 - Rgb_padding_mode = 14, // DMM
5.202 - Rgb_422 = 8, // 422
5.203 - Rgb_format_enable = 7, // RGBFMT
5.204 - Rgb_odd_line = 4, // OddRGB
5.205 - Rgb_even_line = 0, // EvenRGB
5.206 -};
5.207 -
5.208 -enum Rgb_control_values : unsigned
5.209 -{
5.210 - Rgb_padding_end = 0U << Rgb_padding_mode,
5.211 - Rgb_padding_start = 1U << Rgb_padding_mode,
5.212 - Rgb_odd_line_rgb = 0U << Rgb_odd_line,
5.213 - Rgb_odd_line_rbg = 1U << Rgb_odd_line,
5.214 - Rgb_odd_line_grb = 2U << Rgb_odd_line,
5.215 - Rgb_odd_line_gbr = 3U << Rgb_odd_line,
5.216 - Rgb_odd_line_brg = 4U << Rgb_odd_line,
5.217 - Rgb_odd_line_bgr = 5U << Rgb_odd_line,
5.218 - Rgb_even_line_rgb = 0U << Rgb_even_line,
5.219 - Rgb_even_line_rbg = 1U << Rgb_even_line,
5.220 - Rgb_even_line_grb = 2U << Rgb_even_line,
5.221 - Rgb_even_line_gbr = 3U << Rgb_even_line,
5.222 - Rgb_even_line_brg = 4U << Rgb_even_line,
5.223 - Rgb_even_line_bgr = 5U << Rgb_even_line,
5.224 -};
5.225 -
5.226 -// Alpha levels (JZ4780).
5.227 -
5.228 -enum Alpha_levels_bits : unsigned
5.229 -{
5.230 - Alpha_level_fg1 = 8,
5.231 - Alpha_level_fg0 = 0,
5.232 -};
5.233 -
5.234 -enum Alpha_levels_values : unsigned
5.235 -{
5.236 - Alpha_level_fg1_mask = 0x0000ff00,
5.237 - Alpha_level_fg0_mask = 0x000000ff,
5.238 -};
5.239 -
5.240 -// Priority level.
5.241 -
5.242 -enum Priority_level_bits : unsigned
5.243 -{
5.244 - Priority_mode = 31,
5.245 - Priority_highest_burst = 28,
5.246 - Priority_threshold2 = 18,
5.247 - Priority_threshold1 = 9,
5.248 - Priority_threshold0 = 0,
5.249 -};
5.250 -
5.251 -enum Priority_level_values : unsigned
5.252 -{
5.253 - Priority_mode_dynamic = 0U << Priority_mode,
5.254 - Priority_mode_arbiter = 1U << Priority_mode,
5.255 -};
5.256 -
5.257 -enum Priority_burst_values : unsigned
5.258 -{
5.259 - Priority_burst_4 = 0,
5.260 - Priority_burst_8 = 1,
5.261 - Priority_burst_16 = 2,
5.262 - Priority_burst_32 = 3,
5.263 - Priority_burst_64 = 4,
5.264 - Priority_burst_16_cont = 5,
5.265 - Priority_burst_disable = 7,
5.266 -};
5.267 -
5.268 -// Position descriptor member.
5.269 -
5.270 -enum Position_bits : unsigned
5.271 -{
5.272 - Position_bpp = 27,
5.273 - Position_premultiply_lcd = 26,
5.274 - Position_coefficient = 24,
5.275 - Position_y_position = 12,
5.276 - Position_x_position = 0,
5.277 -};
5.278 -
5.279 -enum Position_values : unsigned
5.280 -{
5.281 - Position_bpp_15_16bpp = 4,
5.282 - Position_bpp_18_24bpp = 5,
5.283 - Position_bpp_30bpp = 7,
5.284 -};
5.285 -
5.286
5.287
5.288 // Utility functions.
5.289 @@ -348,8 +74,7 @@
5.290 : _panel(panel)
5.291 {
5.292 _regs = new Hw::Mmio_register_block<32>(addr);
5.293 - _burst_size = 64; // 64-word burst size (JZ4780)
5.294 - //_burst_size = 16; // 16-word burst size
5.295 + _burst_size = 16; // 16-word burst size
5.296 }
5.297
5.298 struct Jz4740_lcd_panel *
5.299 @@ -644,25 +369,6 @@
5.300 }
5.301 }
5.302
5.303 -// Return colour depth control value.
5.304 -// JZ4780 position details only.
5.305 -
5.306 -uint32_t
5.307 -Lcd_jz4740_chip::_position_bpp()
5.308 -{
5.309 - uint32_t value;
5.310 -
5.311 - switch (_panel->bpp)
5.312 - {
5.313 - case 15: case 16: value = Position_bpp_15_16bpp; break;
5.314 - case 18: case 24: value = Position_bpp_18_24bpp; break;
5.315 - case 30: value = Position_bpp_30bpp; break;
5.316 - default: value = 0; break;
5.317 - }
5.318 -
5.319 - return value << Position_bpp;
5.320 -}
5.321 -
5.322 // Return a panel-related control value.
5.323
5.324 uint32_t
5.325 @@ -742,28 +448,6 @@
5.326 ((_irq_conditions & Lcd_irq_frame_end) ? (1U << Status_frame_end_irq) : 0);
5.327 }
5.328
5.329 -uint32_t
5.330 -Lcd_jz4740_chip::_priority_transfer()
5.331 -{
5.332 - uint32_t length;
5.333 -
5.334 - switch (_burst_size)
5.335 - {
5.336 - case 4: length = Priority_burst_4; break;
5.337 - case 8: length = Priority_burst_8; break;
5.338 - case 32: length = Priority_burst_32; break;
5.339 - case 64: length = Priority_burst_64; break;
5.340 - case 16:
5.341 - default: length = Priority_burst_16; break;
5.342 - }
5.343 -
5.344 - return Priority_mode_arbiter |
5.345 - (length << Priority_highest_burst) |
5.346 - (511U << Priority_threshold2) |
5.347 - (400U << Priority_threshold1) |
5.348 - (256U << Priority_threshold0);
5.349 -}
5.350 -
5.351 // STN panel-specific initialisation.
5.352
5.353 void
5.354 @@ -861,32 +545,17 @@
5.355 Lcd_jz4740_chip::_set_descriptor(struct Jz4740_lcd_descriptor &desc,
5.356 l4_addr_t source, l4_size_t size,
5.357 struct Jz4740_lcd_descriptor *next,
5.358 - uint32_t flags,
5.359 - bool frame_enable)
5.360 + uint32_t flags)
5.361 {
5.362 // In the command, indicate the number of words from the source for transfer.
5.363
5.364 desc.next = next;
5.365 - desc.source = frame_enable ? source : 0;
5.366 + desc.source = source;
5.367 desc.identifier = source;
5.368 desc.command = ((size / sizeof(uint32_t)) & Command_buffer_length_mask) |
5.369 - (frame_enable ? (1U << Command_frame_enable) : 0) |
5.370 flags;
5.371 -
5.372 - // Initialise "new" descriptor fields.
5.373 -
5.374 - desc.offset = 0;
5.375 - desc.page_width = 0;
5.376 - desc.command_position = (1U << Position_premultiply_lcd) |
5.377 - ((frame_enable ? 1U : 3U) << Position_coefficient) |
5.378 - _position_bpp();
5.379 - desc.fg_size = 0xff000000 |
5.380 - ((_panel->height - 1) << 12) |
5.381 - ((_panel->width - 1) << 0);
5.382 }
5.383
5.384 -
5.385 -
5.386 // Initialise the LCD controller with the memory, panel and framebuffer details.
5.387 // Any palette must be initialised separately using get_palette and init_palette.
5.388
5.389 @@ -895,13 +564,8 @@
5.390 struct Jz4740_lcd_descriptor *desc_paddr,
5.391 l4_addr_t fb_paddr)
5.392 {
5.393 - // NOTE: Remarks in the Ingenic Linux 3.0.8 driver suggest that the JZ4775 and
5.394 - // NOTE: JZ4780 do not support palettes.
5.395 -
5.396 int have_palette = (_panel->bpp <= 8);
5.397
5.398 - bool _have_fg1 = true; // NOTE: To be formalised!
5.399 -
5.400 // Provide the first framebuffer descriptor in single and dual modes.
5.401 // Flip back and forth between any palette and the framebuffer.
5.402
5.403 @@ -913,12 +577,11 @@
5.404 // Provide the second framebuffer descriptor only in dual-panel mode.
5.405 // Only employ this descriptor in the second DMA channel.
5.406
5.407 - if ((get_panels() == 2) || _have_fg1)
5.408 + if (get_panels() == 2)
5.409 _set_descriptor(desc_vaddr[1], get_framebuffer(1, fb_paddr),
5.410 get_aligned_size(),
5.411 desc_paddr + 1,
5.412 - _command_irq(),
5.413 - false);
5.414 + _command_irq());
5.415
5.416 // Initialise palette descriptor details for lower colour depths.
5.417
5.418 @@ -941,7 +604,7 @@
5.419
5.420 // Provide a descriptor for the second DMA channel in dual-panel mode.
5.421
5.422 - if ((get_panels() == 2) || _have_fg1)
5.423 + if (get_panels() == 2)
5.424 _regs[Desc_address_1] = (uint32_t) (desc_paddr + 1);
5.425
5.426 // Initialise panel-related registers.
5.427 @@ -949,19 +612,9 @@
5.428 _init_panel();
5.429
5.430 // Initialise the control and configuration registers.
5.431 - // NOTE: JZ4780 does not support bpp setting here.
5.432
5.433 _regs[Lcd_control] = _control_panel() | _control_bpp() | _control_transfer() | _control_irq();
5.434 _regs[Lcd_config] = _panel->config;
5.435 -
5.436 - // NOTE: JZ4780 only.
5.437 -
5.438 - _regs[Rgb_control] = (1U << Rgb_format_enable) | Rgb_odd_line_rgb | Rgb_even_line_rgb;
5.439 - _regs[Priority_level] = _priority_transfer();
5.440 - _regs[Osd_config] = (1U << Osd_config_enable) |
5.441 - (1U << Osd_config_alpha_enable);
5.442 - _regs[Alpha_levels] = ((255U << Alpha_level_fg1) & Alpha_level_fg1_mask) |
5.443 - ((255U << Alpha_level_fg0) & Alpha_level_fg0_mask);
5.444 }
5.445
5.446 // Set the interrupt for controller-related events.
6.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
6.2 +++ b/pkg/devices/lib/lcd/src/jz4740/lcd-jz4780.cc Sat Jun 06 01:22:18 2020 +0200
6.3 @@ -0,0 +1,192 @@
6.4 +/*
6.5 + * LCD peripheral support for the JZ4740 and related SoCs.
6.6 + *
6.7 + * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc>
6.8 + * Copyright (C) 2015, 2016, 2017, 2018,
6.9 + * 2020 Paul Boddie <paul@boddie.org.uk>
6.10 + *
6.11 + * This program is free software; you can redistribute it and/or
6.12 + * modify it under the terms of the GNU General Public License as
6.13 + * published by the Free Software Foundation; either version 2 of
6.14 + * the License, or (at your option) any later version.
6.15 + *
6.16 + * This program is distributed in the hope that it will be useful,
6.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6.19 + * GNU General Public License for more details.
6.20 + *
6.21 + * You should have received a copy of the GNU General Public License
6.22 + * along with this program; if not, write to the Free Software
6.23 + * Foundation, Inc., 51 Franklin Street, Fifth Floor,
6.24 + * Boston, MA 02110-1301, USA
6.25 + */
6.26 +
6.27 +#include <l4/devices/hw_mmio_register_block.h>
6.28 +#include <l4/sys/cache.h>
6.29 +#include <l4/sys/types.h>
6.30 +
6.31 +#include "lcd-jz4780.h"
6.32 +#include "lcd-jz4740-config.h"
6.33 +#include "lcd-jz4740-regs.h"
6.34 +
6.35 +#include <stdint.h>
6.36 +
6.37 +
6.38 +
6.39 +// JZ4780-specific methods.
6.40 +
6.41 +Lcd_jz4780_chip::Lcd_jz4780_chip(l4_addr_t addr, Jz4740_lcd_panel *panel)
6.42 +: Lcd_jz4740_chip(addr, panel)
6.43 +{
6.44 + _burst_size = 64; // 64-word burst size available in the JZ4780
6.45 +}
6.46 +
6.47 +// Return colour depth control value.
6.48 +// JZ4780 position details only.
6.49 +
6.50 +uint32_t
6.51 +Lcd_jz4780_chip::_position_bpp()
6.52 +{
6.53 + uint32_t value;
6.54 +
6.55 + switch (_panel->bpp)
6.56 + {
6.57 + case 15: case 16: value = Position_bpp_15_16bpp; break;
6.58 + case 18: case 24: value = Position_bpp_18_24bpp; break;
6.59 + case 30: value = Position_bpp_30bpp; break;
6.60 + default: value = 0; break;
6.61 + }
6.62 +
6.63 + return value << Position_bpp;
6.64 +}
6.65 +
6.66 +uint32_t
6.67 +Lcd_jz4780_chip::_priority_transfer()
6.68 +{
6.69 + uint32_t length;
6.70 +
6.71 + switch (_burst_size)
6.72 + {
6.73 + case 4: length = Priority_burst_4; break;
6.74 + case 8: length = Priority_burst_8; break;
6.75 + case 32: length = Priority_burst_32; break;
6.76 + case 64: length = Priority_burst_64; break;
6.77 + case 16:
6.78 + default: length = Priority_burst_16; break;
6.79 + }
6.80 +
6.81 + return Priority_mode_arbiter |
6.82 + (length << Priority_highest_burst) |
6.83 + (511U << Priority_threshold2) |
6.84 + (400U << Priority_threshold1) |
6.85 + (256U << Priority_threshold0);
6.86 +}
6.87 +
6.88 +// Initialise a DMA descriptor for the JZ4780. The principal differences with
6.89 +// earlier SoCs are the "new" descriptor fields which populate additional
6.90 +// registers controlling OSD foreground planes, and the frame enable flag which
6.91 +// allows the descriptors/planes to be disabled and left unused.
6.92 +
6.93 +void
6.94 +Lcd_jz4780_chip::_set_descriptor(struct Jz4740_lcd_descriptor &desc,
6.95 + l4_addr_t source, l4_size_t size,
6.96 + struct Jz4740_lcd_descriptor *next,
6.97 + uint32_t flags,
6.98 + bool frame_enable)
6.99 +{
6.100 + // In the command, indicate the number of words from the source for transfer.
6.101 +
6.102 + desc.next = next;
6.103 + desc.source = frame_enable ? source : 0;
6.104 + desc.identifier = source;
6.105 + desc.command = ((size / sizeof(uint32_t)) & Command_buffer_length_mask) |
6.106 + (frame_enable ? (1U << Command_frame_enable) : 0) |
6.107 + flags;
6.108 +
6.109 + // Initialise "new" descriptor fields.
6.110 +
6.111 + desc.offset = 0;
6.112 + desc.page_width = 0;
6.113 + desc.command_position = (1U << Position_premultiply_lcd) |
6.114 + ((frame_enable ? 1U : 3U) << Position_coefficient) |
6.115 + _position_bpp();
6.116 + desc.fg_size = 0xff000000 |
6.117 + ((_panel->height - 1) << 12) |
6.118 + ((_panel->width - 1) << 0);
6.119 +}
6.120 +
6.121 +// HDMI-compatible JZ4780 configuration.
6.122 +// Remarks in the Ingenic Linux 3.0.8 driver suggest that the JZ4775 and JZ4780
6.123 +// do not support palettes. Here, multiple panels are also not supported.
6.124 +
6.125 +void
6.126 +Lcd_jz4780_chip::config(struct Jz4740_lcd_descriptor *desc_vaddr,
6.127 + struct Jz4740_lcd_descriptor *desc_paddr,
6.128 + l4_addr_t fb_paddr)
6.129 +{
6.130 + // Provide the first framebuffer descriptor in single and dual modes.
6.131 + // Flip back and forth between any palette and the framebuffer.
6.132 +
6.133 + _set_descriptor(desc_vaddr[0], get_framebuffer(0, fb_paddr),
6.134 + get_aligned_size(),
6.135 + desc_paddr,
6.136 + _command_irq());
6.137 +
6.138 + // Provide the second framebuffer descriptor only in dual-panel mode.
6.139 + // Only employ this descriptor in the second DMA channel.
6.140 +
6.141 + _set_descriptor(desc_vaddr[1], get_framebuffer(1, fb_paddr),
6.142 + get_aligned_size(),
6.143 + desc_paddr + 1,
6.144 + _command_irq(),
6.145 + false);
6.146 +
6.147 + // Flush cached structure data.
6.148 +
6.149 + l4_cache_clean_data((unsigned long) desc_vaddr,
6.150 + (unsigned long) desc_vaddr + get_descriptors_size());
6.151 +
6.152 + // Configure DMA by setting frame descriptor addresses.
6.153 +
6.154 + // Provide the palette descriptor address first, if employed.
6.155 +
6.156 + _regs[Desc_address_0] = (uint32_t) desc_paddr;
6.157 +
6.158 + // Provide a descriptor for the second DMA channel, providing foreground 1.
6.159 +
6.160 + _regs[Desc_address_1] = (uint32_t) (desc_paddr + 1);
6.161 +
6.162 + // Initialise panel-related registers.
6.163 +
6.164 + _init_panel();
6.165 +
6.166 + // Initialise the control and configuration registers.
6.167 + // JZ4780 does not support bpp setting here. Otherwise, this is the same as
6.168 + // with earlier SoCs.
6.169 +
6.170 + _regs[Lcd_control] = _control_panel() | _control_transfer() | _control_irq();
6.171 + _regs[Lcd_config] = _panel->config;
6.172 +
6.173 + // JZ4780-specific configuration.
6.174 + // The RGB control register usage may be superfluous.
6.175 +
6.176 + _regs[Rgb_control] = (1U << Rgb_format_enable) | Rgb_odd_line_rgb | Rgb_even_line_rgb;
6.177 + _regs[Priority_level] = _priority_transfer();
6.178 +
6.179 + // Employ whole image alpha levels by default.
6.180 +
6.181 + _regs[Osd_config] = (1U << Osd_config_enable) |
6.182 + (1U << Osd_config_alpha_enable);
6.183 + _regs[Alpha_levels] = ((255U << Alpha_level_fg1) & Alpha_level_fg1_mask) |
6.184 + ((255U << Alpha_level_fg0) & Alpha_level_fg0_mask);
6.185 +}
6.186 +
6.187 +
6.188 +
6.189 +// C language interface functions.
6.190 +
6.191 +void *
6.192 +jz4780_lcd_init(l4_addr_t lcd_base, struct Jz4740_lcd_panel *panel)
6.193 +{
6.194 + return (void *) new Lcd_jz4780_chip(lcd_base, panel);
6.195 +}
7.1 --- a/pkg/landfall-examples/ci20_hdmi_i2c/ci20_hdmi_i2c.c Sat Jun 06 00:04:50 2020 +0200
7.2 +++ b/pkg/landfall-examples/ci20_hdmi_i2c/ci20_hdmi_i2c.c Sat Jun 06 01:22:18 2020 +0200
7.3 @@ -23,7 +23,7 @@
7.4 #include <l4/devices/gpio-jz4780.h>
7.5 #include <l4/devices/hdmi-jz4780.h>
7.6
7.7 -#include <l4/devices/lcd-jz4740.h>
7.8 +#include <l4/devices/lcd-jz4780.h>
7.9 #include <l4/devices/lcd-jz4740-config.h>
7.10 #include <l4/devices/lcd-jz4740-panel.h>
7.11
7.12 @@ -330,7 +330,7 @@
7.13
7.14 printf("Set up LCD...\n");
7.15
7.16 - lcd = jz4740_lcd_init(lcd_base, &panel);
7.17 + lcd = jz4780_lcd_init(lcd_base, &panel);
7.18
7.19 /* Test initialisation with a frequency appropriate for the test panel. */
7.20