1.1 --- a/pkg/devices/include/clocks.h Sat Oct 28 00:28:42 2023 +0200
1.2 +++ b/pkg/devices/include/clocks.h Sat Oct 28 01:15:45 2023 +0200
1.3 @@ -90,6 +90,7 @@
1.4 Clock_udc,
1.5 Clock_uhc,
1.6 Clock_uprt,
1.7 + Clock_vpu,
1.8 Clock_identifier_count, /* not a clock: limit for array definition */
1.9 Clock_undefined, /* not a clock: special value */
1.10 };
2.1 --- a/pkg/devices/lib/cpm/include/cpm-common.h Sat Oct 28 00:28:42 2023 +0200
2.2 +++ b/pkg/devices/lib/cpm/include/cpm-common.h Sat Oct 28 01:15:45 2023 +0200
2.3 @@ -161,7 +161,7 @@
2.4
2.5 // Clock source frequency.
2.6
2.7 - uint32_t get_frequency(Cpm_regs ®s);
2.8 + uint64_t get_frequency(Cpm_regs ®s);
2.9 };
2.10
2.11
2.12 @@ -227,6 +227,10 @@
2.13 {
2.14 Field _enable, _stable, _bypass;
2.15
2.16 + // Frequency change sequence state.
2.17 +
2.18 + bool _enabled = false;
2.19 +
2.20 // PLL_specific control.
2.21
2.22 int have_pll(Cpm_regs ®s);
2.23 @@ -245,6 +249,9 @@
2.24 void pll_bypass(Cpm_regs ®s);
2.25 void pll_engage(Cpm_regs ®s);
2.26
2.27 + void change_disable(Cpm_regs ®s);
2.28 + void change_enable(Cpm_regs ®s);
2.29 +
2.30 void wait_busy(Cpm_regs ®s);
2.31 int have_clock(Cpm_regs ®s);
2.32 void start_clock(Cpm_regs ®s);
2.33 @@ -262,8 +269,8 @@
2.34
2.35 // Output frequency.
2.36
2.37 - virtual uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency) = 0;
2.38 - virtual int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency) = 0;
2.39 + virtual uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency) = 0;
2.40 + virtual int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency) = 0;
2.41
2.42 // Other operations.
2.43
2.44 @@ -298,8 +305,8 @@
2.45
2.46 // Output frequency.
2.47
2.48 - uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency);
2.49 - int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency);
2.50 + uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency);
2.51 + int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency);
2.52
2.53 // Other operations.
2.54
2.55 @@ -351,8 +358,8 @@
2.56
2.57 // Output frequency.
2.58
2.59 - uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency);
2.60 - int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency);
2.61 + uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency);
2.62 + int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency);
2.63
2.64 // Other operations.
2.65
2.66 @@ -384,8 +391,8 @@
2.67
2.68 // Output frequency.
2.69
2.70 - uint32_t get_frequency(Cpm_regs ®s, uint32_t source_frequency);
2.71 - int set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency);
2.72 + uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency);
2.73 + int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency);
2.74
2.75 // Other operations.
2.76
2.77 @@ -413,7 +420,7 @@
2.78
2.79 // Output frequency.
2.80
2.81 - virtual uint32_t get_frequency(Cpm_regs ®s) = 0;
2.82 + virtual uint64_t get_frequency(Cpm_regs ®s) = 0;
2.83 };
2.84
2.85
2.86 @@ -433,7 +440,7 @@
2.87
2.88 // Output frequency.
2.89
2.90 - uint32_t get_frequency(Cpm_regs ®s);
2.91 + uint64_t get_frequency(Cpm_regs ®s);
2.92 };
2.93
2.94
2.95 @@ -443,10 +450,10 @@
2.96 class Clock_passive : public Clock_base
2.97 {
2.98 protected:
2.99 - uint32_t _frequency;
2.100 + uint64_t _frequency;
2.101
2.102 public:
2.103 - explicit Clock_passive(uint32_t frequency)
2.104 + explicit Clock_passive(uint64_t frequency)
2.105 : _frequency(frequency)
2.106 {
2.107 }
2.108 @@ -461,7 +468,7 @@
2.109
2.110 // Output frequency.
2.111
2.112 - uint32_t get_frequency(Cpm_regs ®s);
2.113 + uint64_t get_frequency(Cpm_regs ®s);
2.114 };
2.115
2.116
2.117 @@ -506,11 +513,11 @@
2.118
2.119 // Clock source frequency.
2.120
2.121 - virtual uint32_t get_source_frequency(Cpm_regs ®s);
2.122 + virtual uint64_t get_source_frequency(Cpm_regs ®s);
2.123
2.124 // Output frequency.
2.125
2.126 - virtual uint32_t get_frequency(Cpm_regs ®s);
2.127 + virtual uint64_t get_frequency(Cpm_regs ®s);
2.128 };
2.129
2.130
2.131 @@ -535,8 +542,8 @@
2.132
2.133 // Output frequency.
2.134
2.135 - uint32_t get_frequency(Cpm_regs ®s);
2.136 - virtual int set_frequency(Cpm_regs ®s, uint32_t frequency);
2.137 + virtual uint64_t get_frequency(Cpm_regs ®s);
2.138 + virtual int set_frequency(Cpm_regs ®s, uint64_t frequency);
2.139 };
2.140
2.141
2.142 @@ -563,8 +570,8 @@
2.143
2.144 // Output frequency.
2.145
2.146 - uint32_t get_frequency(Cpm_regs ®s);
2.147 - int set_frequency(Cpm_regs ®s, uint32_t frequency);
2.148 + uint64_t get_frequency(Cpm_regs ®s);
2.149 + int set_frequency(Cpm_regs ®s, uint64_t frequency);
2.150 };
2.151
2.152
3.1 --- a/pkg/devices/lib/cpm/include/cpm-jz4780.h Sat Oct 28 00:28:42 2023 +0200
3.2 +++ b/pkg/devices/lib/cpm/include/cpm-jz4780.h Sat Oct 28 01:15:45 2023 +0200
3.3 @@ -63,9 +63,9 @@
3.4 enum Clock_identifiers jz4780_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock);
3.5 void jz4780_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source);
3.6
3.7 -uint32_t jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock);
3.8 +uint64_t jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock);
3.9
3.10 -uint32_t jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock);
3.11 -int jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency);
3.12 +uint64_t jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock);
3.13 +int jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency);
3.14
3.15 EXTERN_C_END
4.1 --- a/pkg/devices/lib/cpm/include/cpm-x1600.h Sat Oct 28 00:28:42 2023 +0200
4.2 +++ b/pkg/devices/lib/cpm/include/cpm-x1600.h Sat Oct 28 01:15:45 2023 +0200
4.3 @@ -63,9 +63,9 @@
4.4 enum Clock_identifiers x1600_cpm_get_source_clock(void *cpm, enum Clock_identifiers clock);
4.5 void x1600_cpm_set_source_clock(void *cpm, enum Clock_identifiers clock, enum Clock_identifiers source);
4.6
4.7 -uint32_t x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock);
4.8 +uint64_t x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock);
4.9
4.10 -uint32_t x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock);
4.11 -int x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency);
4.12 +uint64_t x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock);
4.13 +int x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency);
4.14
4.15 EXTERN_C_END
5.1 --- a/pkg/devices/lib/cpm/src/common.cc Sat Oct 28 00:28:42 2023 +0200
5.2 +++ b/pkg/devices/lib/cpm/src/common.cc Sat Oct 28 01:15:45 2023 +0200
5.3 @@ -128,7 +128,7 @@
5.4
5.5 // Clock source frequencies.
5.6
5.7 -uint32_t
5.8 +uint64_t
5.9 Source::get_frequency(Cpm_regs ®s)
5.10 {
5.11 enum Clock_identifiers input = get_source_clock(regs);
5.12 @@ -266,8 +266,29 @@
5.13 void
5.14 Control_pll::wait_busy(Cpm_regs ®s)
5.15 {
5.16 - if (pll_enabled(regs) && !pll_bypassed(regs))
5.17 - while (!have_pll(regs));
5.18 + // NOTE: Could wait for some kind of stable or "lock" signal, but the chips
5.19 + // provide all sorts of differing signals.
5.20 +
5.21 + (void) regs;
5.22 +}
5.23 +
5.24 +void
5.25 +Control_pll::change_disable(Cpm_regs ®s)
5.26 +{
5.27 + if (_enabled)
5.28 + start_clock(regs);
5.29 +}
5.30 +
5.31 +void
5.32 +Control_pll::change_enable(Cpm_regs ®s)
5.33 +{
5.34 + // NOTE: Since the X1600 manual warns of changing the frequency while enabled,
5.35 + // it is easier to just stop and then start the PLL again.
5.36 +
5.37 + _enabled = have_clock(regs);
5.38 +
5.39 + if (_enabled)
5.40 + stop_clock(regs);
5.41 }
5.42
5.43
5.44 @@ -298,14 +319,14 @@
5.45
5.46 // Output clock frequencies.
5.47
5.48 -uint32_t
5.49 -Divider::get_frequency(Cpm_regs ®s, uint32_t source_frequency)
5.50 +uint64_t
5.51 +Divider::get_frequency(Cpm_regs ®s, uint64_t source_frequency)
5.52 {
5.53 return source_frequency / get_divider(regs);
5.54 }
5.55
5.56 int
5.57 -Divider::set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency)
5.58 +Divider::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency)
5.59 {
5.60 set_divider(regs, (uint32_t) round((double) source_frequency / (double) frequency));
5.61 return 1;
5.62 @@ -464,15 +485,15 @@
5.63 _output_divider1.set_field(regs, d1);
5.64 }
5.65
5.66 -uint32_t
5.67 -Divider_pll::get_frequency(Cpm_regs ®s, uint32_t source_frequency)
5.68 +uint64_t
5.69 +Divider_pll::get_frequency(Cpm_regs ®s, uint64_t source_frequency)
5.70 {
5.71 return (source_frequency * get_multiplier(regs)) /
5.72 (get_input_divider(regs) * get_output_divider(regs));
5.73 }
5.74
5.75 int
5.76 -Divider_pll::set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency)
5.77 +Divider_pll::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency)
5.78 {
5.79 double intermediate_multiplier, intermediate_input_divider;
5.80 uint32_t output_min, output_max, output0, output1;
5.81 @@ -515,7 +536,7 @@
5.82 // output frequency to obtain an intermediate frequency using the proposed
5.83 // divider.
5.84
5.85 - uint32_t intermediate_frequency = frequency * output_divider;
5.86 + double intermediate_frequency = frequency * output_divider;
5.87
5.88 // Calculate the required multiplier and divider.
5.89
5.90 @@ -595,8 +616,8 @@
5.91 return _divider_D.get_field(regs);
5.92 }
5.93
5.94 -uint32_t
5.95 -Divider_i2s::get_frequency(Cpm_regs ®s, uint32_t source_frequency)
5.96 +uint64_t
5.97 +Divider_i2s::get_frequency(Cpm_regs ®s, uint64_t source_frequency)
5.98 {
5.99 /* NOTE: Assuming that this is the formula, given that the manual does not
5.100 really describe how D is used. */
5.101 @@ -606,7 +627,7 @@
5.102 }
5.103
5.104 int
5.105 -Divider_i2s::set_frequency(Cpm_regs ®s, uint32_t source_frequency, uint32_t frequency)
5.106 +Divider_i2s::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency)
5.107 {
5.108 double m, n;
5.109
5.110 @@ -718,7 +739,7 @@
5.111
5.112 // Output clock frequencies.
5.113
5.114 -uint32_t
5.115 +uint64_t
5.116 Clock_null::get_frequency(Cpm_regs ®s)
5.117 {
5.118 (void) regs;
5.119 @@ -750,7 +771,7 @@
5.120
5.121 // Output clock frequencies.
5.122
5.123 -uint32_t
5.124 +uint64_t
5.125 Clock_passive::get_frequency(Cpm_regs ®s)
5.126 {
5.127 (void) regs;
5.128 @@ -818,7 +839,7 @@
5.129
5.130 // Clock source frequencies.
5.131
5.132 -uint32_t
5.133 +uint64_t
5.134 Clock_active::get_source_frequency(Cpm_regs ®s)
5.135 {
5.136 return _source.get_frequency(regs);
5.137 @@ -826,7 +847,7 @@
5.138
5.139 // Output clock frequencies.
5.140
5.141 -uint32_t
5.142 +uint64_t
5.143 Clock_active::get_frequency(Cpm_regs ®s)
5.144 {
5.145 return get_source_frequency(regs);
5.146 @@ -842,14 +863,14 @@
5.147
5.148 // Output clock frequencies.
5.149
5.150 -uint32_t
5.151 +uint64_t
5.152 Clock_divided_base::get_frequency(Cpm_regs ®s)
5.153 {
5.154 return _get_divider().get_frequency(regs, get_source_frequency(regs));
5.155 }
5.156
5.157 int
5.158 -Clock_divided_base::set_frequency(Cpm_regs ®s, uint32_t frequency)
5.159 +Clock_divided_base::set_frequency(Cpm_regs ®s, uint64_t frequency)
5.160 {
5.161 _get_control().change_enable(regs);
5.162 int result = _get_divider().set_frequency(regs, get_source_frequency(regs), frequency);
5.163 @@ -884,7 +905,7 @@
5.164 {
5.165 }
5.166
5.167 -uint32_t
5.168 +uint64_t
5.169 Pll::get_frequency(Cpm_regs ®s)
5.170 {
5.171 if (!_control.pll_bypassed(regs))
5.172 @@ -894,7 +915,7 @@
5.173 }
5.174
5.175 int
5.176 -Pll::set_frequency(Cpm_regs ®s, uint32_t frequency)
5.177 +Pll::set_frequency(Cpm_regs ®s, uint64_t frequency)
5.178 {
5.179 int result = Clock_divided_base::set_frequency(regs, frequency);
5.180 _control.pll_engage(regs);
6.1 --- a/pkg/devices/lib/cpm/src/jz4780.cc Sat Oct 28 00:28:42 2023 +0200
6.2 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Sat Oct 28 01:15:45 2023 +0200
6.3 @@ -426,9 +426,11 @@
6.4
6.5 clock_uhc(Source(mux_usb, Clock_source_uhc),
6.6 Control(Clock_gate_uhc, Clock_change_enable_uhc, Clock_busy_uhc),
6.7 - Divider(Clock_divider_uhc));
6.8 + Divider(Clock_divider_uhc)),
6.9
6.10 -
6.11 + clock_vpu(Source(mux_core, Clock_source_vpu),
6.12 + Control(Clock_gate_vpu, Clock_change_enable_vpu, Clock_busy_vpu),
6.13 + Divider(Clock_divider_vpu));
6.14
6.15 const double jz4780_pll_intermediate_min = 300000000,
6.16 jz4780_pll_intermediate_max = 1500000000;
6.17 @@ -525,6 +527,7 @@
6.18 &clock_none, // Clock_udc
6.19 &clock_uhc,
6.20 &clock_none, // Clock_uprt
6.21 + &clock_vpu,
6.22 };
6.23
6.24
6.25 @@ -600,20 +603,20 @@
6.26 static_cast<Cpm_jz4780_chip *>(cpm)->set_source_clock(clock, source);
6.27 }
6.28
6.29 -uint32_t
6.30 +uint64_t
6.31 jz4780_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock)
6.32 {
6.33 return static_cast<Cpm_jz4780_chip *>(cpm)->get_source_frequency(clock);
6.34 }
6.35
6.36 -uint32_t
6.37 +uint64_t
6.38 jz4780_cpm_get_frequency(void *cpm, enum Clock_identifiers clock)
6.39 {
6.40 return static_cast<Cpm_jz4780_chip *>(cpm)->get_frequency(clock);
6.41 }
6.42
6.43 int
6.44 -jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency)
6.45 +jz4780_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency)
6.46 {
6.47 return static_cast<Cpm_jz4780_chip *>(cpm)->set_frequency(clock, frequency);
6.48 }
7.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Sat Oct 28 00:28:42 2023 +0200
7.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Sat Oct 28 01:15:45 2023 +0200
7.3 @@ -463,6 +463,7 @@
7.4 &clock_none, // Clock_udc
7.5 &clock_none, // Clock_uhc
7.6 &clock_none, // Clock_uprt
7.7 + &clock_none, // Clock_vpu
7.8 };
7.9
7.10
7.11 @@ -544,20 +545,20 @@
7.12 static_cast<Cpm_x1600_chip *>(cpm)->set_source_clock(clock, source);
7.13 }
7.14
7.15 -uint32_t
7.16 +uint64_t
7.17 x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock)
7.18 {
7.19 return static_cast<Cpm_x1600_chip *>(cpm)->get_source_frequency(clock);
7.20 }
7.21
7.22 -uint32_t
7.23 +uint64_t
7.24 x1600_cpm_get_frequency(void *cpm, enum Clock_identifiers clock)
7.25 {
7.26 return static_cast<Cpm_x1600_chip *>(cpm)->get_frequency(clock);
7.27 }
7.28
7.29 int
7.30 -x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint32_t frequency)
7.31 +x1600_cpm_set_frequency(void *cpm, enum Clock_identifiers clock, uint64_t frequency)
7.32 {
7.33 return static_cast<Cpm_x1600_chip *>(cpm)->set_frequency(clock, frequency);
7.34 }
8.1 --- a/pkg/landfall-examples/ci20_cpm/ci20_cpm.c Sat Oct 28 00:28:42 2023 +0200
8.2 +++ b/pkg/landfall-examples/ci20_cpm/ci20_cpm.c Sat Oct 28 01:15:45 2023 +0200
8.3 @@ -1,7 +1,7 @@
8.4 /*
8.5 * (c) 2008-2009 Adam Lackorzynski <adam@os.inf.tu-dresden.de>
8.6 * economic rights: Technische Universität Dresden (Germany)
8.7 - * Copyright (C) 2017, 2018, 2021 Paul Boddie <paul@boddie.org.uk>
8.8 + * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk>
8.9 *
8.10 * This file is part of TUD:OS and distributed under the terms of the
8.11 * GNU General Public License 2.
8.12 @@ -130,59 +130,54 @@
8.13 /* Read information from the clock and power management unit. */
8.14
8.15 printf("Main source: %d\n", jz4780_cpm_get_source(cpm, Clock_main));
8.16 - printf(" Main frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_main));
8.17 - printf("APLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_A));
8.18 - printf("EPLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_E));
8.19 - printf("MPLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_M));
8.20 - printf("VPLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V));
8.21 - printf("CPU frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_cpu));
8.22 + printf(" Main frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_main));
8.23 + printf("APLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_A));
8.24 + printf("EPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_E));
8.25 + printf("MPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_M));
8.26 + printf("VPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V));
8.27 + printf("CPU frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_cpu));
8.28 printf("Memory source: %d\n", jz4780_cpm_get_source(cpm, Clock_ddr));
8.29 - printf(" Memory source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_ddr));
8.30 - printf(" Memory frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_ddr));
8.31 + printf(" Memory source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_ddr));
8.32 + printf(" Memory frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_ddr));
8.33 printf("APB source: %d\n", jz4780_cpm_get_source(cpm, Clock_pclock));
8.34 - printf(" APB source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_pclock));
8.35 - printf(" Slow peripheral (APB) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pclock));
8.36 + printf(" APB source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_pclock));
8.37 + printf(" Slow peripheral (APB) frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pclock));
8.38 printf("AHB0 source: %d\n", jz4780_cpm_get_source(cpm, Clock_hclock0));
8.39 - printf(" AHB0 source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock0));
8.40 - printf(" Fast peripheral (AHB0) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hclock0));
8.41 + printf(" AHB0 source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock0));
8.42 + printf(" Fast peripheral (AHB0) frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_hclock0));
8.43 printf("AHB2 source: %d\n", jz4780_cpm_get_source(cpm, Clock_hclock2));
8.44 - printf(" AHB2 source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock2));
8.45 - printf(" Fast peripheral (AHB2) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hclock2));
8.46 + printf(" AHB2 source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock2));
8.47 + printf(" Fast peripheral (AHB2) frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_hclock2));
8.48 printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd));
8.49 - printf(" LCD source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd));
8.50 - printf(" LCD frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd));
8.51 - printf(" LCD pixel clock frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0));
8.52 + printf(" LCD source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd));
8.53 + printf(" LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd));
8.54 + printf(" LCD pixel clock frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0));
8.55
8.56 /* Attempt to set the pixel clock frequency. */
8.57
8.58 jz4780_cpm_set_frequency(cpm, Clock_lcd_pixel0, 108000000);
8.59
8.60 printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd));
8.61 - printf(" LCD source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd));
8.62 - printf(" LCD frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd));
8.63 - printf(" LCD pixel clock frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0));
8.64 + printf(" LCD source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd));
8.65 + printf(" LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd));
8.66 + printf(" LCD pixel clock frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0));
8.67
8.68 - /* Attempt to set the peripheral clock frequency. */
8.69 + /* Change the pixel clock source. */
8.70
8.71 - jz4780_cpm_set_source(cpm, Clock_pclock, 1);
8.72 + jz4780_cpm_set_source_clock(cpm, Clock_lcd_pixel0, Clock_pll_V);
8.73
8.74 - printf("APB source: %d\n", jz4780_cpm_get_source(cpm, Clock_pclock));
8.75 - printf(" APB source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_pclock));
8.76 - printf(" Slow peripheral (APB) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pclock));
8.77 - printf("AHB2 source: %d\n", jz4780_cpm_get_source(cpm, Clock_hclock2));
8.78 - printf(" AHB2 source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock2));
8.79 - printf(" Fast peripheral (AHB2) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hclock2));
8.80 -
8.81 - /* Attempt to set the MPLL output to EXCLK divided by 4. */
8.82 + printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd));
8.83 + printf(" LCD source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_lcd));
8.84 + printf(" LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd));
8.85 + printf(" LCD pixel clock frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0));
8.86
8.87 - jz4780_cpm_set_parameters(cpm, Clock_pll_M, 3, (uint32_t []) {1, 4, 1});
8.88 + /* Attempt to set the VPLL output to EXCLK divided by 4. */
8.89 +
8.90 + jz4780_cpm_set_parameters(cpm, Clock_pll_V, 3, (uint32_t []) {1, 4, 1});
8.91
8.92 - printf("APB source: %d\n", jz4780_cpm_get_source(cpm, Clock_pclock));
8.93 - printf(" APB source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_pclock));
8.94 - printf(" Slow peripheral (APB) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pclock));
8.95 - printf("AHB2 source: %d\n", jz4780_cpm_get_source(cpm, Clock_hclock2));
8.96 - printf(" AHB2 source frequency: %d\n", jz4780_cpm_get_source_frequency(cpm, Clock_hclock2));
8.97 - printf(" Fast peripheral (AHB2) frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hclock2));
8.98 + printf("VPLL source: %d\n", jz4780_cpm_get_source(cpm, Clock_pll_V));
8.99 + printf(" VPLL source frequency: %lld\n", jz4780_cpm_get_source_frequency(cpm, Clock_pll_V));
8.100 + printf(" VPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V));
8.101
8.102 return 0;
8.103 }
9.1 --- a/pkg/landfall-examples/ci20_hdmi_i2c/ci20_hdmi_i2c.c Sat Oct 28 00:28:42 2023 +0200
9.2 +++ b/pkg/landfall-examples/ci20_hdmi_i2c/ci20_hdmi_i2c.c Sat Oct 28 01:15:45 2023 +0200
9.3 @@ -272,13 +272,13 @@
9.4
9.5 cpm = jz4780_cpm_init(cpm_base);
9.6
9.7 - printf("VPLL frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V));
9.8 - printf("HDMI frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hdmi));
9.9 + printf("VPLL frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pll_V));
9.10 + printf("HDMI frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_hdmi));
9.11
9.12 jz4780_cpm_stop_clock(cpm, Clock_hdmi);
9.13 jz4780_cpm_set_frequency(cpm, Clock_hdmi, 27000000);
9.14
9.15 - printf("HDMI frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_hdmi));
9.16 + printf("HDMI frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_hdmi));
9.17
9.18 jz4780_cpm_start_clock(cpm, Clock_hdmi);
9.19
9.20 @@ -339,7 +339,7 @@
9.21 /* Test initialisation with a frequency appropriate for the test panel. */
9.22
9.23 printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd));
9.24 - printf("LCD frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0));
9.25 + printf("LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0));
9.26 printf("Desired frequency: %d\n", jz4740_lcd_get_pixel_clock(lcd));
9.27
9.28 jz4780_cpm_stop_clock(cpm, Clock_lcd);
9.29 @@ -347,7 +347,7 @@
9.30 jz4780_cpm_set_frequency(cpm, Clock_lcd_pixel0, jz4740_lcd_get_pixel_clock(lcd));
9.31
9.32 printf("LCD source: %d\n", jz4780_cpm_get_source(cpm, Clock_lcd));
9.33 - printf("LCD frequency: %d\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0));
9.34 + printf("LCD frequency: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_lcd_pixel0));
9.35
9.36 /* With the LCD pixel clock set up, bring up the HDMI. */
9.37
10.1 --- a/pkg/landfall-examples/ci20_i2c/ci20_i2c.c Sat Oct 28 00:28:42 2023 +0200
10.2 +++ b/pkg/landfall-examples/ci20_i2c/ci20_i2c.c Sat Oct 28 01:15:45 2023 +0200
10.3 @@ -404,7 +404,7 @@
10.4 /* Attempt to set the PCLK source to SCLK_A. */
10.5
10.6 jz4780_cpm_set_source_clock(cpm, Clock_pclock, Clock_main);
10.7 - printf("Peripheral clock: %d\n", jz4780_cpm_get_frequency(cpm, Clock_pclock));
10.8 + printf("Peripheral clock: %lld\n", jz4780_cpm_get_frequency(cpm, Clock_pclock));
10.9
10.10 /* Obtain I2C reference. */
10.11