1.1 --- a/pkg/devices/lib/hdmi/src/jz4780.cc Fri Jun 05 23:42:35 2020 +0200
1.2 +++ b/pkg/devices/lib/hdmi/src/jz4780.cc Fri Jun 05 23:45:28 2020 +0200
1.3 @@ -207,7 +207,7 @@
1.4 // Video packetizer registers.
1.5
1.6 Packet_status = 0x0800, // VP_STATUS
1.7 - Packet_pixel_repeater = 0x0801, // VP_PR_CD
1.8 + Packet_pr_cd = 0x0801, // VP_PR_CD
1.9 Packet_stuffing = 0x0802, // VP_STUFF
1.10 Packet_remap = 0x0803, // VP_REMAP
1.11 Packet_config = 0x0804, // VP_CONF
1.12 @@ -215,7 +215,7 @@
1.13
1.14 // Identification values.
1.15
1.16 -enum Product_id_values : unsigned
1.17 +enum Product_id_values : uint8_t
1.18 {
1.19 Product_id0_transmitter = 0xa0, // PRODUCT_ID0_HDMI_TX
1.20
1.21 @@ -226,7 +226,7 @@
1.22
1.23 // Configuration values.
1.24
1.25 -enum Config_id_values : unsigned
1.26 +enum Config_id_values : uint8_t
1.27 {
1.28 Config_id0_i2s = 0x10, // CONFIG0_I2S
1.29 Config_id0_cec = 0x02, // CONFIG0_CEC
1.30 @@ -247,7 +247,7 @@
1.31
1.32 // Status and mask bits.
1.33
1.34 -enum Int_mask_bits : unsigned
1.35 +enum Int_mask_bits : uint8_t
1.36 {
1.37 Int_mask_wakeup = 0x02,
1.38 Int_mask_all = 0x01,
1.39 @@ -255,7 +255,7 @@
1.40
1.41 // I2C status and mask bits, also for PHY I2C.
1.42
1.43 -enum I2c_int_status_bits : unsigned
1.44 +enum I2c_int_status_bits : uint8_t
1.45 {
1.46 I2c_int_status_done = 0x02,
1.47 I2c_int_status_error = 0x01,
1.48 @@ -263,7 +263,7 @@
1.49
1.50 // I2C operation bits.
1.51
1.52 -enum I2c_operation_bits : unsigned
1.53 +enum I2c_operation_bits : uint8_t
1.54 {
1.55 I2c_operation_write = 0x10,
1.56 I2c_operation_segment_read = 0x02, // not PHY I2C
1.57 @@ -272,7 +272,7 @@
1.58
1.59 // Device addresses.
1.60
1.61 -enum I2c_phy_device_addresses : unsigned
1.62 +enum I2c_phy_device_addresses : uint8_t
1.63 {
1.64 I2c_phy_device_phy_gen2 = 0x69, // PHY_I2CM_SLAVE_ADDR_PHY_GEN2
1.65 I2c_phy_device_phy_heac = 0x49, // PHY_I2CM_SLAVE_ADDR_HEAC_PHY
1.66 @@ -280,7 +280,7 @@
1.67
1.68 // Device registers.
1.69
1.70 -enum I2c_phy_device_registers : unsigned
1.71 +enum I2c_phy_device_registers : uint8_t
1.72 {
1.73 I2c_phy_3d_tx_clock_cal_ctrl = 0x05, // 3D_TX_PHY_CKCALCTRL
1.74 I2c_phy_3d_tx_cpce_ctrl = 0x06, // 3D_TX_PHY_CPCE_CTRL
1.75 @@ -295,25 +295,25 @@
1.76
1.77 // PHY I2C register values.
1.78
1.79 -enum Msm_ctrl_bits : unsigned
1.80 +enum Msm_ctrl_bits : uint16_t
1.81 {
1.82 Msm_ctrl_clock_output_select_fb = 1 << 3, // 3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK
1.83 };
1.84
1.85 -enum Clock_cal_ctrl_bits : unsigned
1.86 +enum Clock_cal_ctrl_bits : uint16_t
1.87 {
1.88 Clock_cal_ctrl_override = 1 << 15, // 3D_TX_PHY_CKCALCTRL_OVERRIDE
1.89 };
1.90
1.91 // Interrupt configuration bits, also for PHY I2C.
1.92
1.93 -enum I2c_int_config0_bits : unsigned
1.94 +enum I2c_int_config0_bits : uint8_t
1.95 {
1.96 I2c_int_config0_done_polarity = 0x08,
1.97 I2c_int_config0_done_mask = 0x04,
1.98 };
1.99
1.100 -enum I2c_int_config1_bits : unsigned
1.101 +enum I2c_int_config1_bits : uint8_t
1.102 {
1.103 I2c_int_config1_nack_polarity = 0x80,
1.104 I2c_int_config1_nack_mask = 0x40,
1.105 @@ -323,7 +323,7 @@
1.106
1.107 // PHY configuration values.
1.108
1.109 -enum Phy_config_bits : unsigned
1.110 +enum Phy_config_bits : uint8_t
1.111 {
1.112 Phy_config_powerdown_disable = 0x80, // PHY_CONF0_PDZ_MASK
1.113 Phy_config_tmds = 0x40, // PHY_CONF0_ENTMDS_MASK
1.114 @@ -335,7 +335,7 @@
1.115 Phy_config_select_interface_control = 0x01, // PHY_CONF0_SELDIPIF_MASK
1.116 };
1.117
1.118 -enum Phy_test_bits : unsigned
1.119 +enum Phy_test_bits : uint8_t
1.120 {
1.121 Phy_test0_clear_mask = 0x20, // PHY_TST0_TSTCLR_MASK
1.122 Phy_test0_enable_mask = 0x10, // PHY_TST0_TSTEN_MASK
1.123 @@ -344,7 +344,7 @@
1.124
1.125 // PHY status and mask values.
1.126
1.127 -enum Phy_status_bits : unsigned
1.128 +enum Phy_status_bits : uint8_t
1.129 {
1.130 Phy_status_all = 0xf3,
1.131 Phy_status_rx_sense_all = 0xf0,
1.132 @@ -359,7 +359,7 @@
1.133
1.134 // PHY interrupt status and mask values.
1.135
1.136 -enum Phy_int_status_bits : unsigned
1.137 +enum Phy_int_status_bits : uint8_t
1.138 {
1.139 Phy_int_status_all = 0x3f,
1.140 Phy_int_status_rx_sense_all = 0x3c,
1.141 @@ -374,18 +374,18 @@
1.142
1.143 // PHY main register values.
1.144
1.145 -enum Main_heac_phy_reset_bits : unsigned
1.146 +enum Main_heac_phy_reset_bits : uint8_t
1.147 {
1.148 Main_heac_phy_reset_assert = 0x01, // MC_HEACPHY_RST_ASSERT
1.149 };
1.150
1.151 -enum Main_flow_control_bits : unsigned
1.152 +enum Main_flow_control_bits : uint8_t
1.153 {
1.154 Main_flow_control_csc_active = 0x01, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH
1.155 Main_flow_control_csc_inactive = 0x00, // MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS
1.156 };
1.157
1.158 -enum Main_clock_disable_bits : unsigned
1.159 +enum Main_clock_disable_bits : uint8_t
1.160 {
1.161 Main_clock_disable_hdcp = 0x40, // MC_CLKDIS_HDCPCLK_DISABLE
1.162 Main_clock_disable_cec = 0x20, // MC_CLKDIS_CECCLK_DISABLE
1.163 @@ -396,9 +396,14 @@
1.164 Main_clock_disable_pixel = 0x01, // MC_CLKDIS_PIXELCLK_DISABLE
1.165 };
1.166
1.167 +enum Main_software_reset_bits : uint8_t
1.168 +{
1.169 + Main_software_reset_tmds = 0x02, // MC_SWRSTZ_TMDSSWRST_REQ
1.170 +};
1.171 +
1.172 // Frame composer values.
1.173
1.174 -enum Fc_video_config_bits : unsigned
1.175 +enum Fc_video_config_bits : uint8_t
1.176 {
1.177 Fc_video_config_hdcp_keepout_active = 0x80, // FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE
1.178 Fc_video_config_hdcp_keepout_inactive = 0x00, // FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE
1.179 @@ -416,7 +421,7 @@
1.180 Fc_video_config_progressive = 0x00, // FC_INVIDCONF_IN_I_P_PROGRESSIVE
1.181 };
1.182
1.183 -enum Fc_int_status2_bits : unsigned
1.184 +enum Fc_int_status2_bits : uint8_t
1.185 {
1.186 Fc_int_status2_overflow = 0x03, // FC_STAT2_OVERFLOW_MASK
1.187 Fc_int_status2_overflow_low = 0x02, // FC_STAT2_LOW_PRIORITY_OVERFLOW
1.188 @@ -425,7 +430,7 @@
1.189
1.190 // Colour space conversion values.
1.191
1.192 -enum Csc_config_bits : unsigned
1.193 +enum Csc_config_bits : uint8_t
1.194 {
1.195 Csc_config_interpolation_mask = 0x30, // CSC_CFG_INTMODE_MASK
1.196 Csc_config_interpolation_disable = 0x00, // CSC_CFG_INTMODE_DISABLE
1.197 @@ -438,7 +443,7 @@
1.198 Csc_config_decimation_form3 = 0x3, // CSC_CFG_DECMODE_CHROMA_INT_FORMULA3
1.199 };
1.200
1.201 -enum Csc_scale_bits : unsigned
1.202 +enum Csc_scale_bits : uint8_t
1.203 {
1.204 Csc_scale_colour_depth_mask = 0xf0, // CSC_SCALE_CSC_COLORDE_PTH_MASK
1.205 Csc_scale_colour_depth_24bpp = 0x00, // CSC_SCALE_CSC_COLORDE_PTH_24BPP
1.206 @@ -450,30 +455,30 @@
1.207
1.208 // HDCP register values.
1.209
1.210 -enum Hdcp_config0_bits : unsigned
1.211 +enum Hdcp_config0_bits : uint8_t
1.212 {
1.213 Hdcp_config0_rxdetect_enable = 0x4, // A_HDCPCFG0_RXDETECT_ENABLE
1.214 };
1.215
1.216 -enum Hdcp_config1_bits : unsigned
1.217 +enum Hdcp_config1_bits : uint8_t
1.218 {
1.219 Hdcp_config1_encryption_disable = 0x2, // A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE
1.220 };
1.221
1.222 -enum Hdcp_video_polarity_bits : unsigned
1.223 +enum Hdcp_video_polarity_bits : uint8_t
1.224 {
1.225 Hdcp_video_polarity_data_enable_active_high = 0x10, // A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH
1.226 };
1.227
1.228 // Video sample register values.
1.229
1.230 -enum Sample_video_config_bits : unsigned
1.231 +enum Sample_video_config_bits : uint8_t
1.232 {
1.233 Sample_video_config_data_enable_active = 0x80, // TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE
1.234 Sample_video_config_mapping_mask = 0x1f, // TX_INVID0_VIDEO_MAPPING_MASK
1.235 };
1.236
1.237 -enum Sample_video_stuffing_bits : unsigned
1.238 +enum Sample_video_stuffing_bits : uint8_t
1.239 {
1.240 Sample_video_stuffing_bdb_data = 0x04, // TX_INSTUFFING_BDBDATA_STUFFING_ENABLE
1.241 Sample_video_stuffing_rcr_data = 0x02, // TX_INSTUFFING_RCRDATA_STUFFING_ENABLE
1.242 @@ -482,7 +487,7 @@
1.243
1.244 // Video packetizer register values.
1.245
1.246 -enum Packet_stuffing_bits : unsigned
1.247 +enum Packet_stuffing_bits : uint8_t
1.248 {
1.249 Packet_stuffing_default_phase = 0x20, // VP_STUFF_IDEFAULT_PHASE_MASK
1.250 Packet_stuffing_ifix_pp_to_last = 0x10, // VP_STUFF_IFIX_PP_TO_LAST_MASK
1.251 @@ -492,7 +497,7 @@
1.252 Packet_stuffing_pr = 0x01, // VP_STUFF_PR_STUFFING_STUFFING_MODE
1.253 };
1.254
1.255 -enum Packet_config_bits : unsigned
1.256 +enum Packet_config_bits : uint8_t
1.257 {
1.258 Packet_config_bypass_enable = 0x40, // VP_CONF_BYPASS_EN_ENABLE
1.259 Packet_config_pp_enable = 0x20, // VP_CONF_PP_EN_ENABLE
1.260 @@ -505,7 +510,7 @@
1.261 Packet_config_output_selector_pp = 0x0, // VP_CONF_OUTPUT_SELECTOR_PP
1.262 };
1.263
1.264 -enum Packet_remap_bits : unsigned
1.265 +enum Packet_remap_bits : uint8_t
1.266 {
1.267 Packet_remap_mask = 0x3, // VP_REMAP_MASK
1.268 Packet_remap_ycc422_24bit = 0x2, // VP_REMAP_YCC422_24bit
1.269 @@ -513,12 +518,12 @@
1.270 Packet_remap_ycc422_16bit = 0x0, // VP_REMAP_YCC422_16bit
1.271 };
1.272
1.273 -enum Packet_pixel_repeater_bits : unsigned
1.274 +enum Packet_pr_cd_bits : uint8_t
1.275 {
1.276 - Packet_pixel_repeater_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK
1.277 - Packet_pixel_repeater_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET
1.278 - Packet_pixel_repeater_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK
1.279 - Packet_pixel_repeater_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET
1.280 + Packet_pr_cd_depth_mask = 0xf0, // VP_PR_CD_COLOR_DEPTH_MASK
1.281 + Packet_pr_cd_depth_offset = 4, // VP_PR_CD_COLOR_DEPTH_OFFSET
1.282 + Packet_pr_cd_factor_mask = 0x0f, // VP_PR_CD_DESIRED_PR_FACTOR_MASK
1.283 + Packet_pr_cd_factor_offset = 0, // VP_PR_CD_DESIRED_PR_FACTOR_OFFSET
1.284 };
1.285
1.286
1.287 @@ -1192,7 +1197,20 @@
1.288
1.289 void Hdmi_jz4780_chip::enable_overflow_irq(bool enable)
1.290 {
1.291 - reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable);
1.292 + if (!enable)
1.293 + reg_update(Fc_int_mask2, Fc_int_status2_overflow, !enable);
1.294 +
1.295 + // Apparent workaround required.
1.296 +
1.297 + else
1.298 + {
1.299 + uint8_t config = _regs[Fc_video_config];
1.300 +
1.301 + _regs[Main_software_reset] = ~(Main_software_reset_tmds);
1.302 +
1.303 + for (int i = 0; i < 4; i++)
1.304 + _regs[Fc_video_config] = config;
1.305 + }
1.306 }
1.307
1.308 void Hdmi_jz4780_chip::frame_init()
1.309 @@ -1321,9 +1339,9 @@
1.310
1.311 int colour_depth = 4;
1.312
1.313 - _regs[Packet_pixel_repeater] =
1.314 - ((colour_depth << Packet_pixel_repeater_depth_offset) &
1.315 - Packet_pixel_repeater_depth_mask);
1.316 + _regs[Packet_pr_cd] =
1.317 + ((colour_depth << Packet_pr_cd_depth_offset) &
1.318 + Packet_pr_cd_depth_mask);
1.319
1.320 _regs[Packet_remap] = Packet_remap_ycc422_16bit;
1.321
1.322 @@ -1334,14 +1352,14 @@
1.323
1.324 // Disable pixel repeater.
1.325
1.326 - reg_update_field(Packet_config, Packet_config_pr_enable |
1.327 - Packet_config_bypass_select_packetizer |
1.328 - Packet_config_bypass_enable |
1.329 + reg_update_field(Packet_config, Packet_config_bypass_enable |
1.330 + Packet_config_pr_enable |
1.331 Packet_config_pp_enable |
1.332 Packet_config_ycc422_enable |
1.333 - Packet_config_output_selector_mask,
1.334 Packet_config_bypass_select_packetizer |
1.335 + Packet_config_output_selector_mask,
1.336 Packet_config_bypass_enable |
1.337 + Packet_config_bypass_select_packetizer |
1.338 Packet_config_output_selector_bypass);
1.339 }
1.340