1.1 --- a/pkg/devices/lib/cpm/src/jz4780.cc Thu Apr 04 00:31:36 2024 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Fri Apr 19 16:17:16 2024 +0200
1.3 @@ -3,7 +3,8 @@
1.4 * provided by the jz4780 and related SoCs. The power management
1.5 * functionality could be exposed using a separate driver.
1.6 *
1.7 - * Copyright (C) 2017, 2018, 2020, 2021, 2023 Paul Boddie <paul@boddie.org.uk>
1.8 + * Copyright (C) 2017, 2018, 2020, 2021, 2023,
1.9 + * 2024 Paul Boddie <paul@boddie.org.uk>
1.10 *
1.11 * This program is free software; you can redistribute it and/or
1.12 * modify it under the terms of the GNU General Public License as
1.13 @@ -222,20 +223,20 @@
1.14
1.15 // Multipliers and dividers yield 1-based values.
1.16
1.17 - Pll_multiplier_A (Pll_control_A, 0x1fff, 19, 1), // APLLM
1.18 - Pll_multiplier_E (Pll_control_E, 0x1fff, 19, 1), // EPLLM
1.19 - Pll_multiplier_M (Pll_control_M, 0x1fff, 19, 1), // MPLLM
1.20 - Pll_multiplier_V (Pll_control_V, 0x1fff, 19, 1), // VPLLM
1.21 + Pll_multiplier_A (Pll_control_A, 0x1fff, 19, false, 1), // APLLM
1.22 + Pll_multiplier_E (Pll_control_E, 0x1fff, 19, false, 1), // EPLLM
1.23 + Pll_multiplier_M (Pll_control_M, 0x1fff, 19, false, 1), // MPLLM
1.24 + Pll_multiplier_V (Pll_control_V, 0x1fff, 19, false, 1), // VPLLM
1.25
1.26 - Pll_input_division_A (Pll_control_A, 0x3f, 13, 1), // APLLN
1.27 - Pll_input_division_E (Pll_control_E, 0x3f, 13, 1), // EPLLN
1.28 - Pll_input_division_M (Pll_control_M, 0x3f, 13, 1), // MPLLN
1.29 - Pll_input_division_V (Pll_control_V, 0x3f, 13, 1), // VPLLN
1.30 + Pll_input_division_A (Pll_control_A, 0x3f, 13, false, 1), // APLLN
1.31 + Pll_input_division_E (Pll_control_E, 0x3f, 13, false, 1), // EPLLN
1.32 + Pll_input_division_M (Pll_control_M, 0x3f, 13, false, 1), // MPLLN
1.33 + Pll_input_division_V (Pll_control_V, 0x3f, 13, false, 1), // VPLLN
1.34
1.35 - Pll_output_division_A (Pll_control_A, 0x0f, 9, 1), // APLLOD
1.36 - Pll_output_division_E (Pll_control_E, 0x0f, 9, 1), // EPLLOD
1.37 - Pll_output_division_M (Pll_control_M, 0x0f, 9, 1), // MPLLOD
1.38 - Pll_output_division_V (Pll_control_V, 0x0f, 9, 1); // VPLLOD
1.39 + Pll_output_division_A (Pll_control_A, 0x0f, 9, false, 1), // APLLOD
1.40 + Pll_output_division_E (Pll_control_E, 0x0f, 9, false, 1), // EPLLOD
1.41 + Pll_output_division_M (Pll_control_M, 0x0f, 9, false, 1), // MPLLOD
1.42 + Pll_output_division_V (Pll_control_V, 0x0f, 9, false, 1); // VPLLOD
1.43
1.44
1.45