paul@62 | 1 | /* |
paul@90 | 2 | * CPU-specific routines originally from U-Boot. |
paul@62 | 3 | * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c |
paul@62 | 4 | * See: u-boot/arch/mips/include/asm/cacheops.h |
paul@62 | 5 | * |
paul@62 | 6 | * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@217 | 7 | * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk> |
paul@62 | 8 | * |
paul@62 | 9 | * This program is free software; you can redistribute it and/or |
paul@62 | 10 | * modify it under the terms of the GNU General Public License as |
paul@62 | 11 | * published by the Free Software Foundation; either version 2 of |
paul@62 | 12 | * the License, or (at your option) any later version. |
paul@62 | 13 | * |
paul@62 | 14 | * This program is distributed in the hope that it will be useful, |
paul@62 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@62 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@62 | 17 | * GNU General Public License for more details. |
paul@62 | 18 | * |
paul@62 | 19 | * You should have received a copy of the GNU General Public License |
paul@62 | 20 | * along with this program; if not, write to the Free Software |
paul@62 | 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@62 | 22 | * Boston, MA 02110-1301, USA |
paul@62 | 23 | */ |
paul@62 | 24 | |
paul@113 | 25 | #include "cpu.h" |
paul@186 | 26 | #include "cpu_op.h" |
paul@194 | 27 | #include "memory.h" |
paul@194 | 28 | #include "paging.h" |
paul@62 | 29 | #include "sdram.h" |
paul@62 | 30 | |
paul@195 | 31 | void flush_icache_all() |
paul@62 | 32 | { |
paul@217 | 33 | uint32_t addr; |
paul@62 | 34 | |
paul@186 | 35 | flush_icache_tag(); |
paul@62 | 36 | |
paul@186 | 37 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) |
paul@186 | 38 | flush_icache_region(addr); |
paul@62 | 39 | |
paul@186 | 40 | flush_icache_config(); |
paul@62 | 41 | } |
paul@62 | 42 | |
paul@195 | 43 | void flush_dcache_all() |
paul@62 | 44 | { |
paul@217 | 45 | uint32_t addr; |
paul@62 | 46 | |
paul@186 | 47 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) |
paul@186 | 48 | flush_dcache_region(addr); |
paul@62 | 49 | |
paul@62 | 50 | asm volatile ("sync"); |
paul@62 | 51 | } |
paul@62 | 52 | |
paul@195 | 53 | void flush_cache_all() |
paul@62 | 54 | { |
paul@62 | 55 | flush_dcache_all(); |
paul@62 | 56 | flush_icache_all(); |
paul@62 | 57 | } |
paul@67 | 58 | |
paul@217 | 59 | void init_registers(uint32_t *base, uint32_t got, void (*function)(), uint32_t args[], uint8_t nargs) |
paul@133 | 60 | { |
paul@217 | 61 | uint8_t i; |
paul@133 | 62 | |
paul@133 | 63 | /* Provide arguments to the function. */ |
paul@133 | 64 | |
paul@133 | 65 | for (i = 0; i < nargs; i++) |
paul@133 | 66 | { |
paul@145 | 67 | base[i+4] = args[i]; |
paul@133 | 68 | } |
paul@133 | 69 | |
paul@133 | 70 | /* Store essential data for the function environment. */ |
paul@133 | 71 | |
paul@217 | 72 | base[25] = (uint32_t) function - 0x80000000; /* store the function address as t9 */ |
paul@145 | 73 | base[26] = got - 0x80000000; /* store the global pointer */ |
paul@217 | 74 | base[29] = (uint32_t) function - 0x80000000; /* store the function address as EPC (for the handler) */ |
paul@133 | 75 | } |
paul@133 | 76 | |
paul@217 | 77 | void init_tlb(uint8_t first_random) |
paul@73 | 78 | { |
paul@217 | 79 | uint32_t limit = configure_tlb(first_random), i; |
paul@147 | 80 | |
paul@147 | 81 | /* Reset the mappings. The total number is bits 30..25 of Config1. */ |
paul@147 | 82 | |
paul@147 | 83 | for (i = 0; i < ((limit >> 25) & 0x3f); i++) |
paul@147 | 84 | { |
paul@157 | 85 | map_page_index(0, 0, 4096, 0, 0, i); |
paul@147 | 86 | } |
paul@117 | 87 | } |
paul@83 | 88 | |
paul@217 | 89 | void init_page_table(uint32_t page_table, uint32_t virtual, uint32_t physical, uint32_t pagesize, uint8_t flags, uint8_t asid) |
paul@136 | 90 | { |
paul@217 | 91 | uint32_t lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@217 | 92 | uint32_t upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@136 | 93 | |
paul@136 | 94 | /* |
paul@136 | 95 | With a complete address space mapping involving pairs of 4KB pages |
paul@136 | 96 | described by two values for each entry, there would be... |
paul@136 | 97 | |
paul@136 | 98 | an address space of 0x100000000 requiring... |
paul@136 | 99 | |
paul@136 | 100 | 0x100000000 / (8 * 1024) == 0x100000000 >> 13 |
paul@136 | 101 | == 524288 entries |
paul@136 | 102 | == 0x80000 entries |
paul@136 | 103 | |
paul@136 | 104 | Thus, each task's entries would require... |
paul@136 | 105 | |
paul@136 | 106 | 0x80000 * 8 == 0x400000 bytes |
paul@136 | 107 | |
paul@136 | 108 | The kseg2 region thus permits 256 tasks occupying 0x40000000 bytes. |
paul@136 | 109 | |
paul@136 | 110 | However, for more modest address spaces occupying as much as 32MB there |
paul@136 | 111 | would be... |
paul@136 | 112 | |
paul@136 | 113 | an address space of 0x02000000 requiring... |
paul@136 | 114 | |
paul@136 | 115 | 0x02000000 / (8 * 1024) == 0x02000000 >> 13 |
paul@136 | 116 | == 4096 entries |
paul@136 | 117 | == 0x1000 entries |
paul@136 | 118 | |
paul@136 | 119 | Thus, each task's entries would only require... |
paul@136 | 120 | |
paul@136 | 121 | 0x1000 * 8 == 0x8000 bytes |
paul@136 | 122 | */ |
paul@136 | 123 | |
paul@217 | 124 | uint32_t base = page_table + STAGE2_PAGE_TABLE_TASK * asid; |
paul@136 | 125 | |
paul@136 | 126 | /* Each page table entry corresponds to a pair of 4KB pages and holds two values. */ |
paul@136 | 127 | |
paul@217 | 128 | uint32_t entry = ((virtual & 0xffffe000) >> 13) * 8; |
paul@217 | 129 | uint32_t *address = (uint32_t *) (base + entry); |
paul@136 | 130 | |
paul@136 | 131 | /* The page tables should be permanently mapped to avoid hierarchical TLB miss handling. */ |
paul@136 | 132 | |
paul@185 | 133 | *address = lower; |
paul@185 | 134 | *(address + 1) = upper; |
paul@136 | 135 | } |
paul@136 | 136 | |
paul@217 | 137 | void map_page(uint32_t virtual, uint32_t physical, uint32_t pagesize, uint8_t flags, uint8_t asid) |
paul@113 | 138 | { |
paul@217 | 139 | uint32_t start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ |
paul@217 | 140 | uint32_t lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@217 | 141 | uint32_t upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@217 | 142 | uint32_t pagemask = ((pagesize - 1) & 0xfffff000) << 1; |
paul@113 | 143 | |
paul@186 | 144 | map_page_op(lower, upper, start, pagemask); |
paul@135 | 145 | } |
paul@187 | 146 | |
paul@217 | 147 | void map_page_index(uint32_t virtual, uint32_t physical, uint32_t pagesize, uint8_t flags, uint8_t asid, uint32_t index) |
paul@187 | 148 | { |
paul@217 | 149 | uint32_t start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ |
paul@217 | 150 | uint32_t lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@217 | 151 | uint32_t upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@217 | 152 | uint32_t pagemask = ((pagesize - 1) & 0xfffff000) << 1; |
paul@187 | 153 | |
paul@187 | 154 | map_page_set_index(index); |
paul@187 | 155 | map_page_index_op(lower, upper, start, pagemask); |
paul@187 | 156 | } |