paul@0 | 1 | /* |
paul@0 | 2 | * Ben NanoNote board initialisation, based on uboot-xburst and xburst-tools. |
paul@0 | 3 | * |
paul@0 | 4 | * Copyright (C) 2015 Paul Boddie <paul@boddie.org.uk> |
paul@0 | 5 | * Copyright (C) Xiangfu Liu <xiangfu.z@gmail.com> |
paul@9 | 6 | * Copyright (C) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn> |
paul@9 | 7 | * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@0 | 8 | * |
paul@0 | 9 | * This program is free software; you can redistribute it and/or modify it under |
paul@0 | 10 | * the terms of the GNU General Public License as published by the Free Software |
paul@0 | 11 | * Foundation; either version 3 of the License, or (at your option) any later |
paul@0 | 12 | * version. |
paul@0 | 13 | * |
paul@0 | 14 | * This program is distributed in the hope that it will be useful, but WITHOUT |
paul@0 | 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS |
paul@0 | 16 | * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more |
paul@0 | 17 | * details. |
paul@0 | 18 | * |
paul@0 | 19 | * You should have received a copy of the GNU General Public License along with |
paul@0 | 20 | * this program. If not, see <http://www.gnu.org/licenses/>. |
paul@0 | 21 | */ |
paul@0 | 22 | |
paul@0 | 23 | #include "jz4740.h" |
paul@0 | 24 | #include "configs.h" |
paul@2 | 25 | #include "nanonote.h" |
paul@0 | 26 | |
paul@0 | 27 | void gpio_init(void) |
paul@0 | 28 | { |
paul@0 | 29 | /* |
paul@0 | 30 | * Initialize NAND Flash Pins |
paul@0 | 31 | */ |
paul@0 | 32 | __gpio_as_nand(); |
paul@0 | 33 | |
paul@0 | 34 | /* |
paul@0 | 35 | * Initialize SDRAM pins |
paul@0 | 36 | */ |
paul@0 | 37 | __gpio_as_sdram_32bit(); |
paul@6 | 38 | } |
paul@0 | 39 | |
paul@6 | 40 | void gpio_init2(void) |
paul@6 | 41 | { |
paul@0 | 42 | /* |
paul@0 | 43 | * Initialize LCD pins |
paul@0 | 44 | */ |
paul@2 | 45 | __gpio_as_slcd_8bit(); |
paul@0 | 46 | |
paul@0 | 47 | /* |
paul@0 | 48 | * Initialize MSC pins |
paul@0 | 49 | */ |
paul@0 | 50 | __gpio_as_msc(); |
paul@0 | 51 | |
paul@0 | 52 | /* |
paul@0 | 53 | * Initialize Other pins |
paul@0 | 54 | */ |
paul@0 | 55 | unsigned int i; |
paul@0 | 56 | for (i = 0; i < 7; i++){ |
paul@0 | 57 | __gpio_as_input(GPIO_KEYIN_BASE + i); |
paul@0 | 58 | __gpio_enable_pull(GPIO_KEYIN_BASE + i); |
paul@0 | 59 | } |
paul@0 | 60 | |
paul@0 | 61 | for (i = 0; i < 8; i++) { |
paul@0 | 62 | __gpio_as_output(GPIO_KEYOUT_BASE + i); |
paul@0 | 63 | __gpio_clear_pin(GPIO_KEYOUT_BASE + i); |
paul@0 | 64 | } |
paul@0 | 65 | |
paul@0 | 66 | /* enable the TP4, TP5 as UART0 */ |
paul@0 | 67 | __gpio_jtag_to_uart0(); |
paul@0 | 68 | |
paul@0 | 69 | __gpio_as_input(GPIO_KEYIN_8); |
paul@0 | 70 | __gpio_enable_pull(GPIO_KEYIN_8); |
paul@0 | 71 | |
paul@0 | 72 | __gpio_as_output(GPIO_AUDIO_POP); |
paul@0 | 73 | __gpio_set_pin(GPIO_AUDIO_POP); |
paul@0 | 74 | |
paul@0 | 75 | __gpio_as_output(GPIO_LCD_CS); |
paul@0 | 76 | __gpio_clear_pin(GPIO_LCD_CS); |
paul@0 | 77 | |
paul@0 | 78 | __gpio_as_output(GPIO_AMP_EN); |
paul@0 | 79 | __gpio_clear_pin(GPIO_AMP_EN); |
paul@0 | 80 | |
paul@0 | 81 | __gpio_as_output(GPIO_SDPW_EN); |
paul@0 | 82 | __gpio_disable_pull(GPIO_SDPW_EN); |
paul@0 | 83 | __gpio_clear_pin(GPIO_SDPW_EN); |
paul@0 | 84 | |
paul@0 | 85 | __gpio_as_input(GPIO_SD_DETECT); |
paul@0 | 86 | __gpio_disable_pull(GPIO_SD_DETECT); |
paul@0 | 87 | |
paul@0 | 88 | __gpio_as_input(GPIO_USB_DETECT); |
paul@0 | 89 | __gpio_enable_pull(GPIO_USB_DETECT); |
paul@0 | 90 | } |
paul@0 | 91 | |
paul@0 | 92 | void cpm_init(void) |
paul@0 | 93 | { |
paul@0 | 94 | __cpm_stop_ipu(); |
paul@0 | 95 | __cpm_stop_cim(); |
paul@0 | 96 | __cpm_stop_i2c(); |
paul@0 | 97 | __cpm_stop_ssi(); |
paul@0 | 98 | __cpm_stop_uart1(); |
paul@0 | 99 | __cpm_stop_sadc(); |
paul@0 | 100 | __cpm_stop_uhc(); |
paul@0 | 101 | __cpm_stop_udc(); |
paul@0 | 102 | __cpm_stop_aic1(); |
paul@0 | 103 | /* __cpm_stop_aic2();*/ |
paul@0 | 104 | } |
paul@0 | 105 | |
paul@0 | 106 | void pll_init(void) |
paul@0 | 107 | { |
paul@0 | 108 | register unsigned int cfcr, plcr1; |
paul@0 | 109 | int n2FR[33] = { |
paul@0 | 110 | 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, |
paul@0 | 111 | 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, |
paul@0 | 112 | 9 |
paul@0 | 113 | }; |
paul@0 | 114 | int nf, pllout2; |
paul@0 | 115 | |
paul@0 | 116 | cfcr = CPM_CPCCR_CLKOEN | |
paul@0 | 117 | (n2FR[PHM_DIV] << CPM_CPCCR_CDIV_BIT) | |
paul@0 | 118 | (n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | |
paul@0 | 119 | (n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) | |
paul@0 | 120 | (n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) | |
paul@0 | 121 | (n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT); |
paul@0 | 122 | |
paul@0 | 123 | pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2); |
paul@0 | 124 | |
paul@0 | 125 | /* Init USB Host clock, pllout2 must be n*48MHz */ |
paul@0 | 126 | REG_CPM_UHCCDR = pllout2 / 48000000 - 1; |
paul@0 | 127 | |
paul@0 | 128 | nf = CFG_CPU_SPEED * 2 / CFG_EXTAL; |
paul@0 | 129 | plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ |
paul@0 | 130 | (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ |
paul@0 | 131 | (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ |
paul@0 | 132 | (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ |
paul@0 | 133 | CPM_CPPCR_PLLEN; /* enable PLL */ |
paul@0 | 134 | |
paul@0 | 135 | /* init PLL */ |
paul@0 | 136 | REG_CPM_CPCCR = cfcr; |
paul@0 | 137 | REG_CPM_CPPCR = plcr1; |
paul@0 | 138 | } |
paul@0 | 139 | |
paul@0 | 140 | void sdram_init(void) |
paul@0 | 141 | { |
paul@0 | 142 | register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; |
paul@0 | 143 | |
paul@0 | 144 | unsigned int cas_latency_sdmr[2] = { |
paul@0 | 145 | EMC_SDMR_CAS_2, |
paul@0 | 146 | EMC_SDMR_CAS_3, |
paul@0 | 147 | }; |
paul@0 | 148 | |
paul@0 | 149 | unsigned int cas_latency_dmcr[2] = { |
paul@0 | 150 | 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ |
paul@0 | 151 | 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ |
paul@0 | 152 | }; |
paul@0 | 153 | |
paul@0 | 154 | int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; |
paul@0 | 155 | |
paul@0 | 156 | cpu_clk = CFG_CPU_SPEED; |
paul@0 | 157 | mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; |
paul@0 | 158 | |
paul@0 | 159 | REG_EMC_BCR = 0; /* Disable bus release */ |
paul@0 | 160 | REG_EMC_RTCSR = 0; /* Disable clock for counting */ |
paul@0 | 161 | |
paul@0 | 162 | /* Fault DMCR value for mode register setting*/ |
paul@0 | 163 | #define SDRAM_ROW0 11 |
paul@0 | 164 | #define SDRAM_COL0 8 |
paul@0 | 165 | #define SDRAM_BANK40 0 |
paul@0 | 166 | |
paul@0 | 167 | dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) | |
paul@0 | 168 | ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) | |
paul@0 | 169 | (SDRAM_BANK40<<EMC_DMCR_BA_BIT) | |
paul@0 | 170 | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
paul@0 | 171 | EMC_DMCR_EPIN | |
paul@0 | 172 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 173 | |
paul@0 | 174 | /* Basic DMCR value */ |
paul@0 | 175 | dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) | |
paul@0 | 176 | ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) | |
paul@0 | 177 | (SDRAM_BANK4<<EMC_DMCR_BA_BIT) | |
paul@0 | 178 | (SDRAM_BW16<<EMC_DMCR_BW_BIT) | |
paul@0 | 179 | EMC_DMCR_EPIN | |
paul@0 | 180 | cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 181 | |
paul@0 | 182 | /* SDRAM timimg */ |
paul@0 | 183 | ns = 1000000000 / mem_clk; |
paul@0 | 184 | tmp = SDRAM_TRAS/ns; |
paul@0 | 185 | if (tmp < 4) tmp = 4; |
paul@0 | 186 | if (tmp > 11) tmp = 11; |
paul@0 | 187 | dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT); |
paul@0 | 188 | tmp = SDRAM_RCD/ns; |
paul@0 | 189 | if (tmp > 3) tmp = 3; |
paul@0 | 190 | dmcr |= (tmp << EMC_DMCR_RCD_BIT); |
paul@0 | 191 | tmp = SDRAM_TPC/ns; |
paul@0 | 192 | if (tmp > 7) tmp = 7; |
paul@0 | 193 | dmcr |= (tmp << EMC_DMCR_TPC_BIT); |
paul@0 | 194 | tmp = SDRAM_TRWL/ns; |
paul@0 | 195 | if (tmp > 3) tmp = 3; |
paul@0 | 196 | dmcr |= (tmp << EMC_DMCR_TRWL_BIT); |
paul@0 | 197 | tmp = (SDRAM_TRAS + SDRAM_TPC)/ns; |
paul@0 | 198 | if (tmp > 14) tmp = 14; |
paul@0 | 199 | dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT); |
paul@0 | 200 | |
paul@0 | 201 | /* SDRAM mode value */ |
paul@0 | 202 | sdmode = EMC_SDMR_BT_SEQ | |
paul@0 | 203 | EMC_SDMR_OM_NORMAL | |
paul@0 | 204 | EMC_SDMR_BL_4 | |
paul@0 | 205 | cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; |
paul@0 | 206 | |
paul@0 | 207 | /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ |
paul@0 | 208 | REG_EMC_DMCR = dmcr; |
paul@0 | 209 | REG8(EMC_SDMR0|sdmode) = 0; |
paul@0 | 210 | |
paul@0 | 211 | /* Wait for precharge, > 200us */ |
paul@0 | 212 | tmp = (cpu_clk / 1000000) * 1000; |
paul@0 | 213 | while (tmp--); |
paul@0 | 214 | |
paul@0 | 215 | /* Stage 2. Enable auto-refresh */ |
paul@0 | 216 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH; |
paul@0 | 217 | |
paul@0 | 218 | tmp = SDRAM_TREF/ns; |
paul@0 | 219 | tmp = tmp/64 + 1; |
paul@0 | 220 | if (tmp > 0xff) tmp = 0xff; |
paul@0 | 221 | REG_EMC_RTCOR = tmp; |
paul@0 | 222 | REG_EMC_RTCNT = 0; |
paul@0 | 223 | REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */ |
paul@0 | 224 | |
paul@0 | 225 | /* Wait for number of auto-refresh cycles */ |
paul@0 | 226 | tmp = (cpu_clk / 1000000) * 1000; |
paul@0 | 227 | while (tmp--); |
paul@0 | 228 | |
paul@0 | 229 | /* Stage 3. Mode Register Set */ |
paul@0 | 230 | REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
paul@0 | 231 | REG8(EMC_SDMR0|sdmode) = 0; |
paul@0 | 232 | |
paul@0 | 233 | /* Set back to basic DMCR value */ |
paul@0 | 234 | REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET; |
paul@0 | 235 | |
paul@0 | 236 | /* everything is ok now */ |
paul@0 | 237 | } |
paul@9 | 238 | |
paul@9 | 239 | void rtc_init(void) |
paul@9 | 240 | { |
paul@9 | 241 | while ( !__rtc_write_ready()) ; |
paul@9 | 242 | __rtc_enable_alarm(); /* enable alarm */ |
paul@9 | 243 | |
paul@9 | 244 | while ( !__rtc_write_ready()) |
paul@9 | 245 | ; |
paul@9 | 246 | REG_RTC_RGR = 0x00007fff; /* type value */ |
paul@9 | 247 | |
paul@9 | 248 | while ( !__rtc_write_ready()) |
paul@9 | 249 | ; |
paul@9 | 250 | REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */ |
paul@9 | 251 | |
paul@9 | 252 | while ( !__rtc_write_ready()) |
paul@9 | 253 | ; |
paul@9 | 254 | REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */ |
paul@9 | 255 | } |
paul@9 | 256 | |
paul@9 | 257 | /* |
paul@9 | 258 | * Timer routines |
paul@9 | 259 | */ |
paul@9 | 260 | |
paul@9 | 261 | #define TIMER_CHAN 0 |
paul@9 | 262 | #define TIMER_FDATA 0xffff /* Timer full data value */ |
paul@9 | 263 | #define TIMER_HZ CONFIG_SYS_HZ |
paul@9 | 264 | |
paul@9 | 265 | #define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */ |
paul@9 | 266 | |
paul@9 | 267 | static unsigned long timestamp; |
paul@9 | 268 | static unsigned long lastdec; |
paul@9 | 269 | |
paul@9 | 270 | void reset_timer_masked(void); |
paul@9 | 271 | unsigned long get_timer_masked(void); |
paul@9 | 272 | void udelay_masked(unsigned long usec); |
paul@9 | 273 | |
paul@9 | 274 | /* |
paul@9 | 275 | * timer without interrupts |
paul@9 | 276 | */ |
paul@9 | 277 | |
paul@9 | 278 | int timer_init(void) |
paul@9 | 279 | { |
paul@9 | 280 | REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN; |
paul@9 | 281 | REG_TCU_TCNT(TIMER_CHAN) = 0; |
paul@9 | 282 | REG_TCU_TDHR(TIMER_CHAN) = 0; |
paul@9 | 283 | REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA; |
paul@9 | 284 | |
paul@9 | 285 | REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */ |
paul@9 | 286 | REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */ |
paul@9 | 287 | REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */ |
paul@9 | 288 | |
paul@9 | 289 | lastdec = 0; |
paul@9 | 290 | timestamp = 0; |
paul@9 | 291 | |
paul@9 | 292 | return 0; |
paul@9 | 293 | } |
paul@9 | 294 | |
paul@9 | 295 | void reset_timer(void) |
paul@9 | 296 | { |
paul@9 | 297 | reset_timer_masked (); |
paul@9 | 298 | } |
paul@9 | 299 | |
paul@9 | 300 | unsigned long get_timer(unsigned long base) |
paul@9 | 301 | { |
paul@9 | 302 | return get_timer_masked () - base; |
paul@9 | 303 | } |
paul@9 | 304 | |
paul@9 | 305 | void set_timer(unsigned long t) |
paul@9 | 306 | { |
paul@9 | 307 | timestamp = t; |
paul@9 | 308 | } |
paul@9 | 309 | |
paul@9 | 310 | void udelay (unsigned long usec) |
paul@9 | 311 | { |
paul@9 | 312 | unsigned long tmo,tmp; |
paul@9 | 313 | |
paul@9 | 314 | /* normalize */ |
paul@9 | 315 | if (usec >= 1000) { |
paul@9 | 316 | tmo = usec / 1000; |
paul@9 | 317 | tmo *= TIMER_HZ; |
paul@9 | 318 | tmo /= 1000; |
paul@9 | 319 | } |
paul@9 | 320 | else { |
paul@9 | 321 | if (usec >= 1) { |
paul@9 | 322 | tmo = usec * TIMER_HZ; |
paul@9 | 323 | tmo /= (1000*1000); |
paul@9 | 324 | } |
paul@9 | 325 | else |
paul@9 | 326 | tmo = 1; |
paul@9 | 327 | } |
paul@9 | 328 | |
paul@9 | 329 | /* check for rollover during this delay */ |
paul@9 | 330 | tmp = get_timer (0); |
paul@9 | 331 | if ((tmp + tmo) < tmp ) |
paul@9 | 332 | reset_timer_masked(); /* timer would roll over */ |
paul@9 | 333 | else |
paul@9 | 334 | tmo += tmp; |
paul@9 | 335 | |
paul@9 | 336 | while (get_timer_masked () < tmo); |
paul@9 | 337 | } |
paul@9 | 338 | |
paul@9 | 339 | void reset_timer_masked (void) |
paul@9 | 340 | { |
paul@9 | 341 | /* reset time */ |
paul@9 | 342 | lastdec = READ_TIMER; |
paul@9 | 343 | timestamp = 0; |
paul@9 | 344 | } |
paul@9 | 345 | |
paul@9 | 346 | unsigned long get_timer_masked (void) |
paul@9 | 347 | { |
paul@9 | 348 | unsigned long now = READ_TIMER; |
paul@9 | 349 | |
paul@9 | 350 | if (lastdec <= now) { |
paul@9 | 351 | /* normal mode */ |
paul@9 | 352 | timestamp += (now - lastdec); |
paul@9 | 353 | } else { |
paul@9 | 354 | /* we have an overflow ... */ |
paul@9 | 355 | timestamp += TIMER_FDATA + now - lastdec; |
paul@9 | 356 | } |
paul@9 | 357 | lastdec = now; |
paul@9 | 358 | |
paul@9 | 359 | return timestamp; |
paul@9 | 360 | } |
paul@9 | 361 | |
paul@9 | 362 | void udelay_masked (unsigned long usec) |
paul@9 | 363 | { |
paul@9 | 364 | unsigned long tmo; |
paul@9 | 365 | unsigned long endtime; |
paul@9 | 366 | signed long diff; |
paul@9 | 367 | |
paul@9 | 368 | /* normalize */ |
paul@9 | 369 | if (usec >= 1000) { |
paul@9 | 370 | tmo = usec / 1000; |
paul@9 | 371 | tmo *= TIMER_HZ; |
paul@9 | 372 | tmo /= 1000; |
paul@9 | 373 | } else { |
paul@9 | 374 | if (usec > 1) { |
paul@9 | 375 | tmo = usec * TIMER_HZ; |
paul@9 | 376 | tmo /= (1000*1000); |
paul@9 | 377 | } else { |
paul@9 | 378 | tmo = 1; |
paul@9 | 379 | } |
paul@9 | 380 | } |
paul@9 | 381 | |
paul@9 | 382 | endtime = get_timer_masked () + tmo; |
paul@9 | 383 | |
paul@9 | 384 | do { |
paul@9 | 385 | unsigned long now = get_timer_masked (); |
paul@9 | 386 | diff = endtime - now; |
paul@9 | 387 | } while (diff >= 0); |
paul@9 | 388 | } |
paul@9 | 389 | |
paul@9 | 390 | /* |
paul@9 | 391 | * This function is derived from PowerPC code (read timebase as long long). |
paul@9 | 392 | * On MIPS it just returns the timer value. |
paul@9 | 393 | */ |
paul@9 | 394 | unsigned long long get_ticks(void) |
paul@9 | 395 | { |
paul@9 | 396 | return get_timer(0); |
paul@9 | 397 | } |
paul@9 | 398 | |
paul@9 | 399 | /* |
paul@9 | 400 | * This function is derived from PowerPC code (timebase clock frequency). |
paul@9 | 401 | * On MIPS it returns the number of timer ticks per second. |
paul@9 | 402 | */ |
paul@9 | 403 | unsigned long get_tbclk (void) |
paul@9 | 404 | { |
paul@9 | 405 | return TIMER_HZ; |
paul@9 | 406 | } |
paul@9 | 407 | |
paul@9 | 408 | /* CPU-specific routines from U-Boot. |
paul@9 | 409 | See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c |
paul@9 | 410 | See: u-boot/arch/mips/include/asm/cacheops.h |
paul@9 | 411 | */ |
paul@9 | 412 | |
paul@9 | 413 | #define Index_Store_Tag_I 0x08 |
paul@9 | 414 | #define Index_Writeback_Inv_D 0x15 |
paul@9 | 415 | |
paul@9 | 416 | void flush_icache_all(void) |
paul@9 | 417 | { |
paul@9 | 418 | u32 addr, t = 0; |
paul@9 | 419 | |
paul@9 | 420 | asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ |
paul@9 | 421 | asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ |
paul@9 | 422 | |
paul@9 | 423 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; |
paul@9 | 424 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@9 | 425 | asm volatile ( |
paul@9 | 426 | ".set mips3\n\t" |
paul@9 | 427 | " cache %0, 0(%1)\n\t" |
paul@9 | 428 | ".set mips2\n\t" |
paul@9 | 429 | : |
paul@9 | 430 | : "I" (Index_Store_Tag_I), "r"(addr)); |
paul@9 | 431 | } |
paul@9 | 432 | |
paul@9 | 433 | /* invalicate btb */ |
paul@9 | 434 | asm volatile ( |
paul@9 | 435 | ".set mips32\n\t" |
paul@9 | 436 | "mfc0 %0, $16, 7\n\t" |
paul@9 | 437 | "nop\n\t" |
paul@9 | 438 | "ori %0,2\n\t" |
paul@9 | 439 | "mtc0 %0, $16, 7\n\t" |
paul@9 | 440 | ".set mips2\n\t" |
paul@9 | 441 | : |
paul@9 | 442 | : "r" (t)); |
paul@9 | 443 | } |
paul@9 | 444 | |
paul@9 | 445 | void flush_dcache_all(void) |
paul@9 | 446 | { |
paul@9 | 447 | u32 addr; |
paul@9 | 448 | |
paul@9 | 449 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; |
paul@9 | 450 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@9 | 451 | asm volatile ( |
paul@9 | 452 | ".set mips3\n\t" |
paul@9 | 453 | " cache %0, 0(%1)\n\t" |
paul@9 | 454 | ".set mips2\n\t" |
paul@9 | 455 | : |
paul@9 | 456 | : "I" (Index_Writeback_Inv_D), "r"(addr)); |
paul@9 | 457 | } |
paul@9 | 458 | |
paul@9 | 459 | asm volatile ("sync"); |
paul@9 | 460 | } |
paul@9 | 461 | |
paul@9 | 462 | void flush_cache_all(void) |
paul@9 | 463 | { |
paul@9 | 464 | flush_dcache_all(); |
paul@9 | 465 | flush_icache_all(); |
paul@9 | 466 | } |