paul@33 | 1 | /* |
paul@224 | 2 | * jz4740 LCD controller configuration. |
paul@33 | 3 | * |
paul@33 | 4 | * Copyright (C) Xiangfu Liu <xiangfu@sharism.cc> |
paul@217 | 5 | * Copyright (C) 2015, 2016, 2017 Paul Boddie <paul@boddie.org.uk> |
paul@33 | 6 | * |
paul@33 | 7 | * This program is free software; you can redistribute it and/or |
paul@33 | 8 | * modify it under the terms of the GNU General Public License as |
paul@33 | 9 | * published by the Free Software Foundation; either version 2 of |
paul@33 | 10 | * the License, or (at your option) any later version. |
paul@33 | 11 | * |
paul@33 | 12 | * This program is distributed in the hope that it will be useful, |
paul@33 | 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@33 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@33 | 15 | * GNU General Public License for more details. |
paul@33 | 16 | * |
paul@33 | 17 | * You should have received a copy of the GNU General Public License |
paul@33 | 18 | * along with this program; if not, write to the Free Software |
paul@42 | 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@42 | 20 | * Boston, MA 02110-1301, USA |
paul@33 | 21 | */ |
paul@33 | 22 | |
paul@33 | 23 | #include "sdram.h" |
paul@33 | 24 | #include "jzlcd.h" |
paul@33 | 25 | #include "board.h" |
paul@33 | 26 | |
paul@223 | 27 | extern vidinfo_t panel_info; |
paul@223 | 28 | |
paul@223 | 29 | /* Useful alignment operations. */ |
paul@223 | 30 | |
paul@223 | 31 | static inline void align2(uint32_t *n) |
paul@223 | 32 | { |
paul@223 | 33 | *n = (((*n)+1)>>1)<<1; |
paul@223 | 34 | } |
paul@223 | 35 | |
paul@223 | 36 | static inline void align4(uint32_t *n) |
paul@223 | 37 | { |
paul@223 | 38 | *n = (((*n)+3)>>2)<<2; |
paul@223 | 39 | } |
paul@223 | 40 | |
paul@223 | 41 | static inline void align8(uint32_t *n) |
paul@223 | 42 | { |
paul@223 | 43 | *n = (((*n)+7)>>3)<<3; |
paul@223 | 44 | } |
paul@33 | 45 | |
paul@223 | 46 | |
paul@223 | 47 | |
paul@223 | 48 | /* Register operations. */ |
paul@223 | 49 | |
paul@223 | 50 | static inline uint32_t lcd_ctrl_get(vidinfo_t *vid, uint32_t reg) |
paul@223 | 51 | { |
paul@223 | 52 | return REG32(vid->lcd + reg); |
paul@223 | 53 | } |
paul@223 | 54 | |
paul@223 | 55 | static inline void lcd_ctrl_set(vidinfo_t *vid, uint32_t reg, uint32_t value) |
paul@223 | 56 | { |
paul@223 | 57 | REG32(vid->lcd + reg) = value; |
paul@223 | 58 | } |
paul@223 | 59 | |
paul@223 | 60 | |
paul@223 | 61 | |
paul@223 | 62 | /* Configuration operations. */ |
paul@223 | 63 | |
paul@223 | 64 | /* Return the number of panels available. */ |
paul@33 | 65 | |
paul@224 | 66 | static uint8_t lcd_get_panels(vidinfo_t *vid) |
paul@100 | 67 | { |
paul@221 | 68 | struct jzfb_info *jzfb = vid->jz_fb; |
paul@221 | 69 | return ((jzfb->cfg & MODE_MASK) == MODE_STN_MONO_DUAL) || |
paul@221 | 70 | ((jzfb->cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ? 2 : 1; |
paul@100 | 71 | } |
paul@100 | 72 | |
paul@223 | 73 | /* Calculate and return the pixel clock frequency. */ |
paul@223 | 74 | |
paul@224 | 75 | static uint32_t lcd_get_pixel_clock(vidinfo_t *vid) |
paul@223 | 76 | { |
paul@223 | 77 | struct jzfb_info *jzfb = vid->jz_fb; |
paul@223 | 78 | uint32_t pclk, width_cycles, mode = jzfb->cfg & MODE_MASK; |
paul@223 | 79 | |
paul@223 | 80 | /* |
paul@223 | 81 | Serial mode: 3 pixel clock cycles per pixel (one per channel). |
paul@223 | 82 | Parallel mode: 1 pixel clock cycle per pixel. |
paul@223 | 83 | */ |
paul@223 | 84 | |
paul@223 | 85 | if (mode == MODE_8BIT_SERIAL_TFT) |
paul@223 | 86 | width_cycles = jzfb->w * 3; |
paul@223 | 87 | else |
paul@223 | 88 | width_cycles = jzfb->w; |
paul@223 | 89 | |
paul@223 | 90 | /* Derive pixel clock from frame clock. */ |
paul@223 | 91 | |
paul@223 | 92 | pclk = jzfb->fclk * |
paul@223 | 93 | (width_cycles + jzfb->hsw + jzfb->elw + jzfb->blw) * |
paul@223 | 94 | (jzfb->h + jzfb->vsw + jzfb->efw + jzfb->bfw); |
paul@223 | 95 | |
paul@223 | 96 | if ((mode == MODE_STN_COLOR_SINGLE) || (mode == MODE_STN_COLOR_DUAL)) |
paul@223 | 97 | pclk = (pclk * 3); |
paul@223 | 98 | |
paul@223 | 99 | if ((mode == MODE_STN_COLOR_SINGLE) || (mode == MODE_STN_COLOR_DUAL) || |
paul@223 | 100 | (mode == MODE_STN_MONO_SINGLE) || (mode == MODE_STN_MONO_DUAL)) |
paul@223 | 101 | pclk = pclk >> ((jzfb->cfg & STN_DAT_PINMASK) >> 4); |
paul@223 | 102 | |
paul@223 | 103 | if ((mode == MODE_STN_COLOR_DUAL) || (mode == MODE_STN_MONO_DUAL)) |
paul@223 | 104 | pclk >>= 1; |
paul@223 | 105 | |
paul@223 | 106 | return pclk; |
paul@223 | 107 | } |
paul@223 | 108 | |
paul@102 | 109 | |
paul@102 | 110 | |
paul@102 | 111 | /* Functions returning region sizes. */ |
paul@102 | 112 | |
paul@217 | 113 | static uint32_t lcd_get_size(vidinfo_t *vid) |
paul@33 | 114 | { |
paul@100 | 115 | /* Lines must be aligned to a word boundary. */ |
paul@227 | 116 | |
paul@221 | 117 | uint32_t line_length = ALIGN((vid->jz_fb->w * vid->jz_fb->bpp) / 8, sizeof(uint32_t)); |
paul@221 | 118 | return line_length * vid->jz_fb->h; |
paul@33 | 119 | } |
paul@33 | 120 | |
paul@217 | 121 | static uint32_t lcd_get_aligned_size(vidinfo_t *vid) |
paul@100 | 122 | { |
paul@100 | 123 | /* LCD_CTRL_BST_16 requires 16-word alignment. */ |
paul@227 | 124 | |
paul@217 | 125 | return ALIGN(lcd_get_size(vid), 16 * sizeof(uint32_t)); |
paul@100 | 126 | } |
paul@100 | 127 | |
paul@217 | 128 | static uint32_t lcd_get_min_size(vidinfo_t *vid) |
paul@100 | 129 | { |
paul@100 | 130 | /* Lines must be aligned to a word boundary. */ |
paul@227 | 131 | |
paul@221 | 132 | uint32_t line_length = ALIGN((vid->jz_fb->w * 32) / 8, sizeof(uint32_t)); |
paul@221 | 133 | return line_length * vid->jz_fb->h; |
paul@100 | 134 | } |
paul@100 | 135 | |
paul@217 | 136 | static uint32_t lcd_get_aligned_min_size(vidinfo_t *vid) |
paul@100 | 137 | { |
paul@100 | 138 | /* LCD_CTRL_BST_16 requires 16-word alignment. */ |
paul@227 | 139 | |
paul@217 | 140 | return ALIGN(lcd_get_min_size(vid), 16 * sizeof(uint32_t)); |
paul@100 | 141 | } |
paul@100 | 142 | |
paul@217 | 143 | static uint32_t lcd_get_palette_size(vidinfo_t *vid) |
paul@97 | 144 | { |
paul@224 | 145 | /* Get a collection of two-byte entries, one per colour. */ |
paul@224 | 146 | |
paul@221 | 147 | if (vid->jz_fb->bpp < 12) |
paul@221 | 148 | return (1 << (vid->jz_fb->bpp)) * sizeof(uint16_t); |
paul@102 | 149 | else |
paul@102 | 150 | return 0; |
paul@97 | 151 | } |
paul@97 | 152 | |
paul@217 | 153 | static uint32_t lcd_get_aligned_palette_size(vidinfo_t *vid) |
paul@100 | 154 | { |
paul@100 | 155 | /* LCD_CTRL_BST_16 requires 16-word alignment. */ |
paul@217 | 156 | return ALIGN(lcd_get_palette_size(vid), 16 * sizeof(uint32_t)); |
paul@100 | 157 | } |
paul@100 | 158 | |
paul@217 | 159 | static uint32_t lcd_get_descriptors_size() |
paul@98 | 160 | { |
paul@98 | 161 | return 3 * sizeof(struct jz_fb_dma_descriptor); |
paul@98 | 162 | } |
paul@98 | 163 | |
paul@102 | 164 | |
paul@102 | 165 | |
paul@102 | 166 | /* Functions returning addresses of each data region. */ |
paul@102 | 167 | |
paul@224 | 168 | static uint32_t lcd_get_palette(vidinfo_t *vid) |
paul@93 | 169 | { |
paul@224 | 170 | /* Use memory at the end of the allocated region for the palette. */ |
paul@224 | 171 | |
paul@227 | 172 | return vid->jz_mem.screen + vid->jz_mem.total - lcd_get_aligned_palette_size(vid); |
paul@98 | 173 | } |
paul@98 | 174 | |
paul@224 | 175 | static uint32_t lcd_get_descriptors(vidinfo_t *vid) |
paul@98 | 176 | { |
paul@224 | 177 | /* Use memory before the palette for the descriptor array. */ |
paul@224 | 178 | |
paul@224 | 179 | return lcd_get_palette(vid) - lcd_get_descriptors_size(); |
paul@48 | 180 | } |
paul@48 | 181 | |
paul@227 | 182 | static uint32_t lcd_get_framebuffer(uint8_t panel, vidinfo_t *vid) |
paul@97 | 183 | { |
paul@224 | 184 | /* Framebuffers for panels are allocated at the start of the region. */ |
paul@224 | 185 | |
paul@227 | 186 | return vid->jz_mem.screen + (panel * lcd_get_aligned_size(vid)); |
paul@97 | 187 | } |
paul@97 | 188 | |
paul@102 | 189 | |
paul@102 | 190 | |
paul@102 | 191 | /* Initialisation functions. */ |
paul@102 | 192 | |
paul@221 | 193 | static uint32_t jz_lcd_stn_init(uint32_t stnH, vidinfo_t *vid) |
paul@96 | 194 | { |
paul@221 | 195 | struct jzfb_info *jzfb = vid->jz_fb; |
paul@217 | 196 | uint32_t val = 0; |
paul@96 | 197 | |
paul@221 | 198 | switch (jzfb->bpp) { |
paul@223 | 199 | case 1: |
paul@96 | 200 | /* val |= LCD_CTRL_PEDN; */ |
paul@223 | 201 | case 2: |
paul@96 | 202 | val |= LCD_CTRL_FRC_2; |
paul@96 | 203 | break; |
paul@223 | 204 | |
paul@223 | 205 | case 4: |
paul@96 | 206 | val |= LCD_CTRL_FRC_4; |
paul@96 | 207 | break; |
paul@223 | 208 | |
paul@223 | 209 | case 8: |
paul@223 | 210 | default: |
paul@96 | 211 | val |= LCD_CTRL_FRC_16; |
paul@96 | 212 | break; |
paul@96 | 213 | } |
paul@96 | 214 | |
paul@221 | 215 | switch (jzfb->cfg & STN_DAT_PINMASK) { |
paul@223 | 216 | case STN_DAT_PIN1: |
paul@96 | 217 | /* Do not adjust the hori-param value. */ |
paul@96 | 218 | break; |
paul@223 | 219 | |
paul@223 | 220 | case STN_DAT_PIN2: |
paul@223 | 221 | align2(&jzfb->hsw); |
paul@223 | 222 | align2(&jzfb->elw); |
paul@223 | 223 | align2(&jzfb->blw); |
paul@96 | 224 | break; |
paul@223 | 225 | |
paul@223 | 226 | case STN_DAT_PIN4: |
paul@223 | 227 | align4(&jzfb->hsw); |
paul@223 | 228 | align4(&jzfb->elw); |
paul@223 | 229 | align4(&jzfb->blw); |
paul@96 | 230 | break; |
paul@223 | 231 | |
paul@223 | 232 | case STN_DAT_PIN8: |
paul@223 | 233 | align8(&jzfb->hsw); |
paul@223 | 234 | align8(&jzfb->elw); |
paul@223 | 235 | align8(&jzfb->blw); |
paul@96 | 236 | break; |
paul@96 | 237 | } |
paul@96 | 238 | |
paul@223 | 239 | lcd_ctrl_set(vid, LCD_VSYNC, jzfb->vsw); |
paul@224 | 240 | lcd_ctrl_set(vid, LCD_HSYNC, ((jzfb->blw + jzfb->w) << 16) | (jzfb->blw + jzfb->w + jzfb->hsw)); |
paul@96 | 241 | |
paul@96 | 242 | /* Screen setting */ |
paul@223 | 243 | lcd_ctrl_set(vid, LCD_VAT, ((jzfb->blw + jzfb->w + jzfb->hsw + jzfb->elw) << 16) | (stnH + jzfb->vsw + jzfb->bfw + jzfb->efw)); |
paul@223 | 244 | lcd_ctrl_set(vid, LCD_DAH, (jzfb->blw << 16) | (jzfb->blw + jzfb->w)); |
paul@223 | 245 | lcd_ctrl_set(vid, LCD_DAV, stnH); |
paul@96 | 246 | |
paul@96 | 247 | /* AC BIAs signal */ |
paul@223 | 248 | lcd_ctrl_set(vid, LCD_PS, stnH+jzfb->vsw+jzfb->efw+jzfb->bfw); |
paul@96 | 249 | |
paul@96 | 250 | return val; |
paul@96 | 251 | } |
paul@96 | 252 | |
paul@221 | 253 | static void jz_lcd_tft_init(vidinfo_t *vid) |
paul@96 | 254 | { |
paul@221 | 255 | struct jzfb_info *jzfb = vid->jz_fb; |
paul@224 | 256 | |
paul@223 | 257 | lcd_ctrl_set(vid, LCD_VSYNC, jzfb->vsw); |
paul@223 | 258 | lcd_ctrl_set(vid, LCD_HSYNC, jzfb->hsw); |
paul@224 | 259 | lcd_ctrl_set(vid, LCD_DAV, ((jzfb->vsw + jzfb->bfw) << 16) | (jzfb->vsw + jzfb->bfw + jzfb->h)); |
paul@223 | 260 | lcd_ctrl_set(vid, LCD_DAH, ((jzfb->hsw + jzfb->blw) << 16) | (jzfb->hsw + jzfb->blw + jzfb->w)); |
paul@223 | 261 | lcd_ctrl_set(vid, LCD_VAT, (((jzfb->blw + jzfb->w + jzfb->elw + jzfb->hsw)) << 16) | |
paul@223 | 262 | (jzfb->vsw + jzfb->bfw + jzfb->h + jzfb->efw)); |
paul@96 | 263 | } |
paul@96 | 264 | |
paul@223 | 265 | static void jz_lcd_samsung_init(vidinfo_t *vid) |
paul@106 | 266 | { |
paul@221 | 267 | struct jzfb_info *jzfb = vid->jz_fb; |
paul@224 | 268 | uint32_t pclk = lcd_get_pixel_clock(vid); |
paul@217 | 269 | uint32_t total, tp_s, tp_e, ckv_s, ckv_e; |
paul@217 | 270 | uint32_t rev_s, rev_e, inv_s, inv_e; |
paul@106 | 271 | |
paul@221 | 272 | jz_lcd_tft_init(vid); |
paul@106 | 273 | |
paul@221 | 274 | total = jzfb->blw + jzfb->w + jzfb->elw + jzfb->hsw; |
paul@221 | 275 | tp_s = jzfb->blw + jzfb->w + 1; |
paul@106 | 276 | tp_e = tp_s + 1; |
paul@106 | 277 | /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */ |
paul@106 | 278 | ckv_s = tp_s - pclk/(1000000000/4100); |
paul@106 | 279 | ckv_e = tp_s + total; |
paul@106 | 280 | rev_s = tp_s - 11; /* -11.5 clk */ |
paul@106 | 281 | rev_e = rev_s + total; |
paul@106 | 282 | inv_s = tp_s; |
paul@106 | 283 | inv_e = inv_s + total; |
paul@223 | 284 | lcd_ctrl_set(vid, LCD_CLS, (tp_s << 16) | tp_e); |
paul@223 | 285 | lcd_ctrl_set(vid, LCD_PS, (ckv_s << 16) | ckv_e); |
paul@223 | 286 | lcd_ctrl_set(vid, LCD_SPL, (rev_s << 16) | rev_e); |
paul@223 | 287 | lcd_ctrl_set(vid, LCD_REV, (inv_s << 16) | inv_e); |
paul@221 | 288 | jzfb->cfg |= STFT_REVHI | STFT_SPLHI; |
paul@106 | 289 | } |
paul@106 | 290 | |
paul@221 | 291 | static void jz_lcd_sharp_init(vidinfo_t *vid) |
paul@106 | 292 | { |
paul@221 | 293 | struct jzfb_info *jzfb = vid->jz_fb; |
paul@217 | 294 | uint32_t total, cls_s, cls_e, ps_s, ps_e; |
paul@217 | 295 | uint32_t spl_s, spl_e, rev_s, rev_e; |
paul@106 | 296 | |
paul@221 | 297 | jz_lcd_tft_init(vid); |
paul@106 | 298 | |
paul@221 | 299 | total = jzfb->blw + jzfb->w + jzfb->elw + jzfb->hsw; |
paul@106 | 300 | spl_s = 1; |
paul@106 | 301 | spl_e = spl_s + 1; |
paul@106 | 302 | cls_s = 0; |
paul@106 | 303 | cls_e = total - 60; /* > 4us (pclk = 80ns) */ |
paul@106 | 304 | ps_s = cls_s; |
paul@106 | 305 | ps_e = cls_e; |
paul@106 | 306 | rev_s = total - 40; /* > 3us (pclk = 80ns) */ |
paul@106 | 307 | rev_e = rev_s + total; |
paul@221 | 308 | jzfb->cfg |= STFT_PSHI; |
paul@223 | 309 | lcd_ctrl_set(vid, LCD_SPL, (spl_s << 16) | spl_e); |
paul@223 | 310 | lcd_ctrl_set(vid, LCD_CLS, (cls_s << 16) | cls_e); |
paul@223 | 311 | lcd_ctrl_set(vid, LCD_PS, (ps_s << 16) | ps_e); |
paul@223 | 312 | lcd_ctrl_set(vid, LCD_REV, (rev_s << 16) | rev_e); |
paul@98 | 313 | } |
paul@98 | 314 | |
paul@33 | 315 | |
paul@96 | 316 | |
paul@223 | 317 | /* Palette initialisation. */ |
paul@102 | 318 | |
paul@217 | 319 | static inline uint16_t rgb8_to_rgb16(uint8_t rgb) |
paul@102 | 320 | { |
paul@103 | 321 | return ((((rgb & 0xe0) >> 5) * 4) << 11) | ((((rgb & 0x1c) >> 2) * 9) << 6) | ((rgb & 0x03) * 10); |
paul@103 | 322 | } |
paul@103 | 323 | |
paul@217 | 324 | static inline uint16_t rgb4_to_rgb16(uint8_t rgb) |
paul@103 | 325 | { |
paul@103 | 326 | return ((((rgb & 8) >> 3) * 0x1f) << 11) | ((((rgb & 6) >> 1) * 0x15) << 5) | ((rgb & 1) * 0x1f); |
paul@102 | 327 | } |
paul@102 | 328 | |
paul@102 | 329 | static void lcd_init_palette(vidinfo_t *vid) |
paul@102 | 330 | { |
paul@223 | 331 | uint16_t *palette = (uint16_t *) vid->jz_mem.palette; |
paul@221 | 332 | uint16_t *end = (uint16_t *) palette + (1 << (vid->jz_fb->bpp)); |
paul@217 | 333 | uint8_t value = 0; |
paul@102 | 334 | |
paul@102 | 335 | while (palette < end) |
paul@102 | 336 | { |
paul@221 | 337 | switch (vid->jz_fb->bpp) |
paul@103 | 338 | { |
paul@221 | 339 | case 4: |
paul@103 | 340 | *palette = rgb4_to_rgb16(value); |
paul@103 | 341 | break; |
paul@103 | 342 | |
paul@221 | 343 | case 8: |
paul@103 | 344 | default: |
paul@103 | 345 | *palette = rgb8_to_rgb16(value); |
paul@103 | 346 | break; |
paul@103 | 347 | } |
paul@103 | 348 | |
paul@102 | 349 | value++; |
paul@102 | 350 | palette++; |
paul@102 | 351 | } |
paul@33 | 352 | } |
paul@33 | 353 | |
paul@223 | 354 | |
paul@223 | 355 | |
paul@227 | 356 | /* Public functions. */ |
paul@227 | 357 | |
paul@227 | 358 | /* Return the total size of the required memory. */ |
paul@223 | 359 | |
paul@227 | 360 | uint32_t jz4740_lcd_get_total_size(vidinfo_t *vid) |
paul@227 | 361 | { |
paul@227 | 362 | uint32_t size = lcd_get_aligned_size(vid) * lcd_get_panels(vid); |
paul@227 | 363 | uint32_t min_size = lcd_get_aligned_min_size(vid); |
paul@227 | 364 | |
paul@227 | 365 | /* Round up to nearest full page, or MMU section if defined. */ |
paul@223 | 366 | |
paul@227 | 367 | return ALIGN((size >= min_size ? size : min_size) + |
paul@227 | 368 | lcd_get_aligned_palette_size(vid) + lcd_get_descriptors_size(), |
paul@227 | 369 | PAGE_SIZE); |
paul@227 | 370 | } |
paul@223 | 371 | |
paul@227 | 372 | /* Return the calculated pixel clock frequency for the display. */ |
paul@227 | 373 | |
paul@227 | 374 | uint32_t jz4740_lcd_get_pixel_clock(vidinfo_t *vid) |
paul@227 | 375 | { |
paul@227 | 376 | return lcd_get_pixel_clock(vid); |
paul@223 | 377 | } |
paul@223 | 378 | |
paul@224 | 379 | /* Initialise the LCD controller with the memory, panel and framebuffer details. |
paul@224 | 380 | Return the pixel clock frequency. */ |
paul@224 | 381 | |
paul@227 | 382 | void jz4740_lcd_ctrl_init(void *lcd_base, void *fb_vaddr, vidinfo_t *vid) |
paul@224 | 383 | { |
paul@224 | 384 | struct jz_mem_info *fbi = &vid->jz_mem; |
paul@227 | 385 | struct jz_fb_dma_descriptor *descriptors; |
paul@224 | 386 | |
paul@224 | 387 | /* Set the LCD controller address. */ |
paul@224 | 388 | |
paul@224 | 389 | vid->lcd = lcd_base; |
paul@224 | 390 | |
paul@227 | 391 | /* Initialise the total region size. */ |
paul@227 | 392 | |
paul@227 | 393 | fbi->total = jz4740_lcd_get_total_size(vid); |
paul@227 | 394 | |
paul@227 | 395 | /* Obtain a reference to the descriptors. */ |
paul@227 | 396 | |
paul@227 | 397 | descriptors = (struct jz_fb_dma_descriptor *) lcd_get_descriptors(vid); |
paul@227 | 398 | |
paul@224 | 399 | /* Position framebuffer regions at the given address. */ |
paul@224 | 400 | |
paul@224 | 401 | fbi->screen = (uint32_t) fb_vaddr; |
paul@224 | 402 | |
paul@224 | 403 | /* Obtain the palette address. */ |
paul@224 | 404 | |
paul@224 | 405 | fbi->palette = lcd_get_palette(vid); |
paul@224 | 406 | |
paul@224 | 407 | /* Initialise a palette for lower colour depths. */ |
paul@224 | 408 | |
paul@224 | 409 | if (vid->jz_fb->bpp < 12) |
paul@224 | 410 | lcd_init_palette(vid); |
paul@224 | 411 | |
paul@224 | 412 | /* Reference the descriptors in memory. */ |
paul@224 | 413 | |
paul@224 | 414 | fbi->dmadesc_fb0 = &descriptors[0]; |
paul@224 | 415 | fbi->dmadesc_fb1 = &descriptors[1]; |
paul@224 | 416 | fbi->dmadesc_palette = &descriptors[2]; |
paul@224 | 417 | |
paul@224 | 418 | /* Populate descriptors. */ |
paul@224 | 419 | |
paul@224 | 420 | /* Provide the first framebuffer descriptor in single and dual modes. */ |
paul@224 | 421 | |
paul@224 | 422 | fbi->dmadesc_fb0->fsadr = lcd_get_framebuffer(0, vid); |
paul@224 | 423 | fbi->dmadesc_fb0->fidr = 0; |
paul@224 | 424 | fbi->dmadesc_fb0->ldcmd = lcd_get_size(vid) / 4; /* length in words */ |
paul@224 | 425 | |
paul@224 | 426 | /* Provide the second framebuffer descriptor only in dual-panel mode. */ |
paul@224 | 427 | |
paul@224 | 428 | if (lcd_get_panels(vid) == 2) |
paul@224 | 429 | { |
paul@224 | 430 | fbi->dmadesc_fb1->fdadr = fbi->dmadesc_fb1; |
paul@224 | 431 | fbi->dmadesc_fb1->fsadr = lcd_get_framebuffer(1, vid); |
paul@224 | 432 | fbi->dmadesc_fb1->fidr = 0; |
paul@224 | 433 | fbi->dmadesc_fb1->ldcmd = lcd_get_size(vid) / 4; |
paul@224 | 434 | |
paul@224 | 435 | /* Note the address to be provided for the second channel. */ |
paul@224 | 436 | |
paul@224 | 437 | fbi->fdadr1 = fbi->dmadesc_fb1; |
paul@224 | 438 | } |
paul@224 | 439 | |
paul@224 | 440 | /* Initialise palette descriptor details if a palette is to be used. */ |
paul@224 | 441 | |
paul@224 | 442 | /* Assume any mode with <12 bpp is palette driven. */ |
paul@224 | 443 | |
paul@224 | 444 | if (vid->jz_fb->bpp < 12) |
paul@224 | 445 | { |
paul@224 | 446 | fbi->dmadesc_palette->fsadr = fbi->palette; |
paul@224 | 447 | fbi->dmadesc_palette->fidr = 0; |
paul@224 | 448 | fbi->dmadesc_palette->ldcmd = (lcd_get_palette_size(vid) / 4) | LCD_CMD_PAL; |
paul@224 | 449 | |
paul@224 | 450 | /* Flip back and forth between the palette and framebuffer. */ |
paul@224 | 451 | |
paul@224 | 452 | fbi->dmadesc_palette->fdadr = fbi->dmadesc_fb0; |
paul@224 | 453 | fbi->dmadesc_fb0->fdadr = fbi->dmadesc_palette; |
paul@224 | 454 | |
paul@224 | 455 | /* Provide the palette descriptor address first. */ |
paul@224 | 456 | |
paul@224 | 457 | fbi->fdadr0 = fbi->dmadesc_palette; |
paul@224 | 458 | } |
paul@224 | 459 | else |
paul@224 | 460 | { |
paul@224 | 461 | /* No palette: always use the framebuffer descriptor. */ |
paul@224 | 462 | |
paul@224 | 463 | fbi->dmadesc_fb0->fdadr = fbi->dmadesc_fb0; |
paul@224 | 464 | fbi->fdadr0 = fbi->dmadesc_fb0; |
paul@224 | 465 | } |
paul@224 | 466 | } |
paul@224 | 467 | |
paul@224 | 468 | /* Initialise the LCD registers. */ |
paul@224 | 469 | |
paul@227 | 470 | void jz4740_lcd_hw_init(vidinfo_t *vid) |
paul@223 | 471 | { |
paul@223 | 472 | struct jzfb_info *jzfb = vid->jz_fb; |
paul@223 | 473 | uint32_t val = 0; |
paul@223 | 474 | |
paul@223 | 475 | /* Compute control register flags. */ |
paul@223 | 476 | |
paul@223 | 477 | switch (jzfb->bpp) { |
paul@223 | 478 | case 1: |
paul@223 | 479 | val |= LCD_CTRL_BPP_1; |
paul@223 | 480 | break; |
paul@223 | 481 | |
paul@223 | 482 | case 2: |
paul@223 | 483 | val |= LCD_CTRL_BPP_2; |
paul@223 | 484 | break; |
paul@223 | 485 | |
paul@223 | 486 | case 4: |
paul@223 | 487 | val |= LCD_CTRL_BPP_4; |
paul@223 | 488 | break; |
paul@223 | 489 | |
paul@223 | 490 | case 8: |
paul@223 | 491 | val |= LCD_CTRL_BPP_8; |
paul@223 | 492 | break; |
paul@223 | 493 | |
paul@223 | 494 | case 15: |
paul@223 | 495 | val |= LCD_CTRL_RGB555; |
paul@223 | 496 | case 16: |
paul@223 | 497 | val |= LCD_CTRL_BPP_16; |
paul@223 | 498 | break; |
paul@223 | 499 | |
paul@223 | 500 | case 17 ... 32: |
paul@223 | 501 | val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */ |
paul@223 | 502 | break; |
paul@223 | 503 | |
paul@223 | 504 | default: |
paul@223 | 505 | val |= LCD_CTRL_BPP_16; /* default to 16bpp */ |
paul@223 | 506 | break; |
paul@223 | 507 | } |
paul@223 | 508 | |
paul@223 | 509 | /* Set various configuration registers for the panel. */ |
paul@223 | 510 | |
paul@223 | 511 | switch (jzfb->cfg & MODE_MASK) { |
paul@223 | 512 | case MODE_STN_MONO_DUAL: |
paul@223 | 513 | case MODE_STN_COLOR_DUAL: |
paul@223 | 514 | val |= jz_lcd_stn_init(jzfb->h >> 1, vid); |
paul@223 | 515 | break; |
paul@223 | 516 | |
paul@223 | 517 | case MODE_STN_MONO_SINGLE: |
paul@223 | 518 | case MODE_STN_COLOR_SINGLE: |
paul@223 | 519 | val |= jz_lcd_stn_init(jzfb->h, vid); |
paul@223 | 520 | break; |
paul@223 | 521 | |
paul@223 | 522 | case MODE_TFT_GEN: |
paul@223 | 523 | case MODE_TFT_CASIO: |
paul@223 | 524 | case MODE_8BIT_SERIAL_TFT: |
paul@223 | 525 | case MODE_TFT_18BIT: |
paul@223 | 526 | jz_lcd_tft_init(vid); |
paul@223 | 527 | break; |
paul@223 | 528 | |
paul@223 | 529 | case MODE_TFT_SAMSUNG: |
paul@223 | 530 | jz_lcd_samsung_init(vid); |
paul@223 | 531 | break; |
paul@223 | 532 | |
paul@223 | 533 | case MODE_TFT_SHARP: |
paul@223 | 534 | jz_lcd_sharp_init(vid); |
paul@223 | 535 | break; |
paul@223 | 536 | |
paul@223 | 537 | default: |
paul@223 | 538 | break; |
paul@223 | 539 | } |
paul@223 | 540 | |
paul@224 | 541 | /* Further control register and panel configuration. */ |
paul@223 | 542 | |
paul@223 | 543 | val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */ |
paul@223 | 544 | val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */ |
paul@223 | 545 | |
paul@223 | 546 | lcd_ctrl_set(vid, LCD_CTRL, val); |
paul@223 | 547 | lcd_ctrl_set(vid, LCD_CFG, jzfb->cfg); |
paul@223 | 548 | } |
paul@223 | 549 | |
paul@223 | 550 | /* Initialise DMA for the driver. */ |
paul@223 | 551 | |
paul@227 | 552 | void jz4740_lcd_dma_init(vidinfo_t *vid) |
paul@223 | 553 | { |
paul@224 | 554 | struct jz_mem_info *fbi = &vid->jz_mem; |
paul@224 | 555 | uint32_t mode = vid->jz_fb->cfg & MODE_MASK; |
paul@223 | 556 | |
paul@224 | 557 | /* Configure DMA by setting frame descriptor addresses. */ |
paul@223 | 558 | |
paul@223 | 559 | lcd_ctrl_set(vid, LCD_DA0, (uint32_t) fbi->fdadr0); |
paul@223 | 560 | |
paul@223 | 561 | if ((mode == MODE_STN_COLOR_DUAL) || (mode == MODE_STN_MONO_DUAL)) |
paul@223 | 562 | lcd_ctrl_set(vid, LCD_DA1, (uint32_t) fbi->fdadr1); |
paul@223 | 563 | } |
paul@223 | 564 | |
paul@224 | 565 | /* Set the colour depth. */ |
paul@223 | 566 | |
paul@223 | 567 | void lcd_set_bpp(uint8_t bpp) |
paul@223 | 568 | { |
paul@223 | 569 | vidinfo_t *vid = &panel_info; |
paul@224 | 570 | vid->jz_fb->bpp = bpp; |
paul@223 | 571 | } |
paul@223 | 572 | |
paul@223 | 573 | void lcd_enable() |
paul@223 | 574 | { |
paul@223 | 575 | vidinfo_t *vid = &panel_info; |
paul@223 | 576 | |
paul@223 | 577 | /* Clear the disable bit (DIS) and set the enable bit (ENA). */ |
paul@223 | 578 | |
paul@223 | 579 | lcd_ctrl_set(vid, LCD_CTRL, (lcd_ctrl_get(vid, LCD_CTRL) & ~LCD_CTRL_DIS) | LCD_CTRL_ENA); |
paul@223 | 580 | } |
paul@223 | 581 | |
paul@223 | 582 | void lcd_disable() |
paul@223 | 583 | { |
paul@223 | 584 | vidinfo_t *vid = &panel_info; |
paul@223 | 585 | |
paul@223 | 586 | /* Set the disable bit (DIS). */ |
paul@223 | 587 | |
paul@223 | 588 | lcd_ctrl_set(vid, LCD_CTRL, lcd_ctrl_get(vid, LCD_CTRL) | LCD_CTRL_DIS); |
paul@223 | 589 | } |
paul@223 | 590 | |
paul@223 | 591 | void lcd_quick_disable() |
paul@223 | 592 | { |
paul@223 | 593 | vidinfo_t *vid = &panel_info; |
paul@223 | 594 | |
paul@223 | 595 | /* Clear the enable bit (ENA) for quick disable. */ |
paul@223 | 596 | |
paul@223 | 597 | lcd_ctrl_set(vid, LCD_CTRL, lcd_ctrl_get(vid, LCD_CTRL) & ~LCD_CTRL_ENA); |
paul@223 | 598 | } |