paul@62 | 1 | /* |
paul@90 | 2 | * CPU-specific routines originally from U-Boot. |
paul@62 | 3 | * See: uboot-xburst/files/arch/mips/cpu/xburst/cpu.c |
paul@62 | 4 | * See: u-boot/arch/mips/include/asm/cacheops.h |
paul@62 | 5 | * |
paul@62 | 6 | * Copyright (C) 2000-2009 Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
paul@90 | 7 | * Copyright (C) 2015, 2016 Paul Boddie <paul@boddie.org.uk> |
paul@62 | 8 | * |
paul@62 | 9 | * This program is free software; you can redistribute it and/or |
paul@62 | 10 | * modify it under the terms of the GNU General Public License as |
paul@62 | 11 | * published by the Free Software Foundation; either version 2 of |
paul@62 | 12 | * the License, or (at your option) any later version. |
paul@62 | 13 | * |
paul@62 | 14 | * This program is distributed in the hope that it will be useful, |
paul@62 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
paul@62 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
paul@62 | 17 | * GNU General Public License for more details. |
paul@62 | 18 | * |
paul@62 | 19 | * You should have received a copy of the GNU General Public License |
paul@62 | 20 | * along with this program; if not, write to the Free Software |
paul@62 | 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, |
paul@62 | 22 | * Boston, MA 02110-1301, USA |
paul@62 | 23 | */ |
paul@62 | 24 | |
paul@113 | 25 | #include "cpu.h" |
paul@62 | 26 | #include "sdram.h" |
paul@62 | 27 | |
paul@62 | 28 | void flush_icache_all(void) |
paul@62 | 29 | { |
paul@62 | 30 | u32 addr, t = 0; |
paul@62 | 31 | |
paul@62 | 32 | asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ |
paul@62 | 33 | asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ |
paul@62 | 34 | |
paul@62 | 35 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_ICACHE_SIZE; |
paul@62 | 36 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 37 | asm volatile ( |
paul@62 | 38 | ".set mips3\n\t" |
paul@62 | 39 | " cache %0, 0(%1)\n\t" |
paul@62 | 40 | ".set mips2\n\t" |
paul@62 | 41 | : |
paul@62 | 42 | : "I" (Index_Store_Tag_I), "r"(addr)); |
paul@62 | 43 | } |
paul@62 | 44 | |
paul@62 | 45 | /* invalicate btb */ |
paul@62 | 46 | asm volatile ( |
paul@62 | 47 | ".set mips32\n\t" |
paul@62 | 48 | "mfc0 %0, $16, 7\n\t" |
paul@62 | 49 | "nop\n\t" |
paul@62 | 50 | "ori %0,2\n\t" |
paul@62 | 51 | "mtc0 %0, $16, 7\n\t" |
paul@62 | 52 | ".set mips2\n\t" |
paul@62 | 53 | : |
paul@62 | 54 | : "r" (t)); |
paul@62 | 55 | } |
paul@62 | 56 | |
paul@62 | 57 | void flush_dcache_all(void) |
paul@62 | 58 | { |
paul@62 | 59 | u32 addr; |
paul@62 | 60 | |
paul@62 | 61 | for (addr = KSEG0; addr < KSEG0 + CONFIG_SYS_DCACHE_SIZE; |
paul@62 | 62 | addr += CONFIG_SYS_CACHELINE_SIZE) { |
paul@62 | 63 | asm volatile ( |
paul@62 | 64 | ".set mips3\n\t" |
paul@62 | 65 | " cache %0, 0(%1)\n\t" |
paul@62 | 66 | ".set mips2\n\t" |
paul@62 | 67 | : |
paul@62 | 68 | : "I" (Index_Writeback_Inv_D), "r"(addr)); |
paul@62 | 69 | } |
paul@62 | 70 | |
paul@62 | 71 | asm volatile ("sync"); |
paul@62 | 72 | } |
paul@62 | 73 | |
paul@62 | 74 | void flush_cache_all(void) |
paul@62 | 75 | { |
paul@62 | 76 | flush_dcache_all(); |
paul@62 | 77 | flush_icache_all(); |
paul@62 | 78 | } |
paul@67 | 79 | |
paul@73 | 80 | void handle_error_level(void) |
paul@73 | 81 | { |
paul@73 | 82 | asm volatile( |
paul@117 | 83 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@117 | 84 | "li $t4, 0xfffffffb\n" /* ERL = 0 */ |
paul@115 | 85 | "and $t3, $t3, $t4\n" |
paul@115 | 86 | "mtc0 $t3, $12\n" |
paul@115 | 87 | "nop\n"); |
paul@115 | 88 | } |
paul@115 | 89 | |
paul@67 | 90 | void enable_interrupts(void) |
paul@67 | 91 | { |
paul@67 | 92 | asm volatile( |
paul@117 | 93 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@117 | 94 | "li $t4, 0x0000fc01\n" /* IE = enable interrupts */ |
paul@67 | 95 | "or $t3, $t3, $t4\n" |
paul@67 | 96 | "mtc0 $t3, $12\n" |
paul@67 | 97 | "nop\n"); |
paul@67 | 98 | } |
paul@73 | 99 | |
paul@73 | 100 | void init_interrupts(void) |
paul@73 | 101 | { |
paul@73 | 102 | /* Set exception registers. */ |
paul@73 | 103 | |
paul@73 | 104 | asm volatile( |
paul@73 | 105 | "mtc0 $zero, $18\n" /* CP0_WATCHLO */ |
paul@73 | 106 | "li $t3, 0x00800000\n" /* IV = 1 (use 0x80000200 for interrupts) */ |
paul@73 | 107 | "mtc0 $t3, $13\n" /* CP0_CAUSE */ |
paul@111 | 108 | "mfc0 $t4, $12\n" /* CP0_STATUS */ |
paul@111 | 109 | "li $t3, 0xffbfffff\n" /* BEV=0 */ |
paul@84 | 110 | "and $t3, $t3, $t4\n" |
paul@84 | 111 | "mtc0 $t3, $12\n" |
paul@73 | 112 | "nop\n"); |
paul@73 | 113 | } |
paul@73 | 114 | |
paul@117 | 115 | void enter_user_mode(void) |
paul@117 | 116 | { |
paul@117 | 117 | asm volatile( |
paul@117 | 118 | "mfc0 $t3, $12\n" /* CP0_STATUS */ |
paul@124 | 119 | "li $t4, 0x00000010\n" /* KSU = 2 (UM = 1) */ |
paul@124 | 120 | "or $t3, $t3, $t4\n" |
paul@117 | 121 | "mtc0 $t3, $12\n" |
paul@117 | 122 | "nop\n"); |
paul@117 | 123 | } |
paul@117 | 124 | |
paul@73 | 125 | void init_tlb(void) |
paul@73 | 126 | { |
paul@73 | 127 | asm volatile( |
paul@116 | 128 | "li $t1, 1\n" /* index of first randomly-replaced entry */ |
paul@111 | 129 | "mtc0 $t1, $6\n" /* CP0_WIRED */ |
paul@117 | 130 | "nop\n"); |
paul@73 | 131 | |
paul@119 | 132 | map_page_index(0x80000000, 0x00000000, 16 * 1024 * 1024, 0x1f, 0, 0); |
paul@117 | 133 | } |
paul@83 | 134 | |
paul@117 | 135 | void map_page_index(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid, u32 index) |
paul@117 | 136 | { |
paul@130 | 137 | u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ |
paul@117 | 138 | u32 lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@117 | 139 | u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@117 | 140 | u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; |
paul@117 | 141 | |
paul@117 | 142 | asm volatile( |
paul@117 | 143 | "mtc0 %3, $5\n" /* CP0_PAGEMASK */ |
paul@117 | 144 | |
paul@117 | 145 | /* Set the index. */ |
paul@117 | 146 | |
paul@117 | 147 | "mtc0 %4, $0\n" /* CP0_INDEX */ |
paul@83 | 148 | |
paul@73 | 149 | /* Set physical address. */ |
paul@73 | 150 | |
paul@117 | 151 | "mtc0 %0, $2\n" /* CP0_ENTRYLO0 */ |
paul@117 | 152 | "mtc0 %1, $3\n" /* CP0_ENTRYLO1 */ |
paul@73 | 153 | |
paul@73 | 154 | /* Set virtual address. */ |
paul@73 | 155 | |
paul@130 | 156 | "mtc0 %2, $10\n" /* CP0_ENTRYHI */ |
paul@73 | 157 | "nop\n" |
paul@73 | 158 | |
paul@83 | 159 | "tlbwi\n" |
paul@117 | 160 | "nop" |
paul@117 | 161 | : |
paul@117 | 162 | : "r" (lower), "r" (upper), "r" (start), "r" (pagemask), "r" (index) |
paul@117 | 163 | ); |
paul@113 | 164 | } |
paul@83 | 165 | |
paul@117 | 166 | void map_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid) |
paul@113 | 167 | { |
paul@130 | 168 | u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ |
paul@116 | 169 | u32 lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@116 | 170 | u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@113 | 171 | u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; |
paul@113 | 172 | |
paul@113 | 173 | asm volatile( |
paul@113 | 174 | "mtc0 %3, $5\n" /* CP0_PAGEMASK */ |
paul@83 | 175 | |
paul@83 | 176 | /* Set physical address. */ |
paul@83 | 177 | |
paul@113 | 178 | "mtc0 %0, $2\n" /* CP0_ENTRYLO0 */ |
paul@113 | 179 | "mtc0 %1, $3\n" /* CP0_ENTRYLO1 */ |
paul@83 | 180 | |
paul@83 | 181 | /* Set virtual address. */ |
paul@83 | 182 | |
paul@113 | 183 | "mtc0 %2, $10\n" /* CP0_ENTRYHI */ |
paul@83 | 184 | "nop\n" |
paul@83 | 185 | |
paul@113 | 186 | "tlbwr\n" |
paul@113 | 187 | "nop" |
paul@113 | 188 | : |
paul@113 | 189 | : "r" (lower), "r" (upper), "r" (start), "r" (pagemask) |
paul@113 | 190 | ); |
paul@73 | 191 | } |
paul@114 | 192 | |
paul@117 | 193 | void unmap_page(u32 virtual, u32 physical, u32 pagesize, u8 flags, u8 asid) |
paul@117 | 194 | { |
paul@130 | 195 | u32 start = (virtual & 0xffffe000) | asid; /* VPN2 | ASID*/ |
paul@117 | 196 | u32 lower = ((physical & 0xfffff000) >> 6) | flags; |
paul@117 | 197 | u32 upper = (((physical + pagesize) & 0xfffff000) >> 6) | flags; |
paul@117 | 198 | u32 pagemask = ((pagesize - 1) & 0xfffff000) << 1; |
paul@117 | 199 | u32 index = 0; |
paul@117 | 200 | |
paul@117 | 201 | asm volatile( |
paul@117 | 202 | "mtc0 %4, $5\n" /* CP0_PAGEMASK */ |
paul@117 | 203 | |
paul@117 | 204 | /* Set physical address. */ |
paul@117 | 205 | |
paul@117 | 206 | "mtc0 %1, $2\n" /* CP0_ENTRYLO0 */ |
paul@117 | 207 | "mtc0 %2, $3\n" /* CP0_ENTRYLO1 */ |
paul@117 | 208 | |
paul@117 | 209 | /* Set virtual address. */ |
paul@117 | 210 | |
paul@117 | 211 | "mtc0 %3, $10\n" /* CP0_ENTRYHI */ |
paul@117 | 212 | "nop\n" |
paul@117 | 213 | |
paul@117 | 214 | /* Find an existing mapping. */ |
paul@117 | 215 | |
paul@117 | 216 | "tlbp\n" |
paul@117 | 217 | "nop\n" |
paul@117 | 218 | |
paul@117 | 219 | /* Read the index register to see if a match was found. */ |
paul@117 | 220 | |
paul@117 | 221 | "mfc0 %0, $0\n" /* CP0_INDEX */ |
paul@117 | 222 | "nop" |
paul@117 | 223 | : "=r" (index) |
paul@117 | 224 | : "r" (lower), "r" (upper), "r" (start), "r" (pagemask) |
paul@117 | 225 | ); |
paul@117 | 226 | |
paul@117 | 227 | /* Return if the page is not mapped. */ |
paul@117 | 228 | |
paul@117 | 229 | if (index & 0x80000000) |
paul@117 | 230 | return; |
paul@117 | 231 | |
paul@117 | 232 | /* Otherwise, invalidate the mapping. */ |
paul@117 | 233 | |
paul@117 | 234 | map_page_index(virtual, physical, pagesize, flags & 0xfd, asid, index); |
paul@117 | 235 | } |